DETAILED ACTION
Claims 1 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 8-10, filed 2/20/2026, with respect to the rejection(s) of claim(s) 1 and 14 under 35 U.S.C. 103 have been fully considered and are persuasive in view of the applicant’s amendment.
Applicant's arguments, see pages 9-10, filed 2/20/2026, with respect to the rejection of claim 9 under 35 U.S.C. 103 have been fully considered but they are not persuasive. Applicant argues the combination of Toh and Hsu does not teach or suggest a control gate comprises a first section and a second section, injecting electrons to the storage node by applying a first control voltage on the first section and the second section of the control gate; and removing electrons from the storage node by applying a second control voltage on the first section and the second section of the control gate.
Hsu does not teach or suggest a control gate includes two sections as claimed. However, applicant concedes Toh discloses a control gate may include two sub-gates that can be separately biased (FIG. 1c and 1d; paragraph [0037])—at least teaching a control gate comprising a first and second section. Moreover, claim 9 recites the first control voltage is applied to both the first and second control gate to inject electrons into the storage node, and the second control voltage is applied to both the first and second control gate to remove electrons from the storage node—thereby, reciting the same voltage level is applied to the different sections during an operation (injection or removal of electrons). This is no different than applying a voltage to a single, conjoined gate structure, besides the structural significance of the split gate.
Therefore, Toh teaches the necessary structural elements of the recited memory cell’s gate structure and a difference in voltage levels applied to the gate structure during the different operations (Table 1A: MC voltages during programming and erasing). The rejection has been maintained below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh et al. (US 20140048867 A1; hereinafter "Toh") in view of Hsu et al. (US 20080087942 A1; hereinafter "Hsu").
Regarding claim 9, Toh discloses a method for operating a memory cell, comprising: providing a multi-time programmable memory cell comprising: a source region (FIG. 1b: common S/D region 126); a drain region (FIG. 1b: first/second cell terminals 122 124); a channel region connected between the source region and the drain region (para. [0023]: “The FinFETs include a common fin structure 420 disposed on the substrate.”; para. [0025]: ”The doped fin forms channels of the transistors below the gate.”); a storage node formed on the channel region (FIG. 1b: nitride layer 461; para. [0027]: “The charge storage dielectric layers 134 are capable of storing charge corresponding to the bits of the memory cell. In one embodiment, a charge storage dielectric layer is a composite charge storage layers or stack. The charge storage stack, for example, includes an oxide-nitride-oxide (ONO) sandwich 460, 461 and 462.”), wherein the channel region comprises a semiconductor fin having a first sidewall, a second sidewall and a top surface connecting the first sidewall and the second sidewall (FIG. 1a and 1b: the channel formed by the common fin structure 420 clearly has a first sidewall, a second sidewall, and a top surface); and a control gate on the storage node (FIGs. 1a and 1b: first and second gate electrodes 136a-b), wherein the control qate comprises a first section and a second section (para. 0037): “a gate electrode includes first and second sub-gates which are separated by the fin sidewalls, charge storage dielectric layer and gate dielectric layers 150”); injecting electrons to the storage node by applying a first control voltage on the first section and the second section of the control gate (Table 1A: MC programming voltages Vg, pgm); and removing electrons from the storage node by applying a second control voltage on the first section and the second section of the control gate (Table 1A: MC erase voltage Vg, ers).
However, Toh does not disclose the storage node is disposed on the first sidewall, the second sidewall, and the top surface of the channel region.
Hsu, in the same field of endeavor, discloses a storage node (FIG. 4B: nitride layer 162) disposed on a first sidewall (FIG. 4B: vertical surface 112b), a second sidewall (FIG. 4B: vertical surface 112b), and a top surface (FIG. 4B: top surface 112a) of a channel region (FIG. 4B: channel 112).
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the first gate dielectric layer and the storage gate electrode layer of Toh to overlap the first sidewall, the second sidewall, and the top surface of the channel region as taught by Hsu. One of ordinary skill in the art would have been motivated to make this modification for the benefit forming a tri-gate on a FINFET channel for better efficiency than a planar channel transistor (Hsu at para. [0006]).
Regarding claim 11, Toh discloses injecting electrons to the storage node comprising: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the first control voltage is a positive voltage (Table 1b: under n-type cell, Vg, pgm = 5V), the source voltage is about 0V (Table 1b: under n-type cell, Vs = 0V), and the drain voltage is a positive voltage (Table 1b: under n-type cell, Vd, pgm = 6V).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Toh et al. (US 20140048867 A1; hereinafter "Toh") in view of Hsu et al. (US 20080087942 A1; hereinafter "Hsu") as applied to claim 9 above, and further in view of Ching et al. (US 20140177338 A1; hereinafter "Ching").
Regarding claim 10, Toh and Hsu teaches the method for operating a memory cell as set forth in the obviousness rejection of claim 9.
However, Toh and Hsu do not teach injecting electrons to the storage node comprising: applying a source voltage on the source region; and applying a drain voltage on the drain region, wherein the first control voltage is a positive voltage, and the source voltage and drain voltage are about 0V.
Ching, in the same field of endeavor, provides a table in FIG. 4 showing programming, erase, and read voltages for the non-volatile memory cell 40 of FIG. 2 and FIG. 3. Ching discloses a control line voltage in a range from 5 Volts to 20 Volts may be applied to the control line (CL), and he source line (SL), the bit line (BL) may be grounded (0V) (para. [0026]). Thereby, teaching a programming voltage scheme that utilizes Fowler-Nordheim (FN) electron tunneling injection, as shown in FIG. 3B in the instant application.
Therefore, it would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have used a voltage scheme as taught by Ching with the memory cell of Toh. One of ordinary skill in the art would have been motivated to make this modification for the benefit of performing Fowler-Nordheim (FN) electron tunneling injection to program the memory cell (Ching at para. [0026]).
Allowable Subject Matter
Claims 1-2, 4-8, and 14-21 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding independent claim 1, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "the storage gate electrode layer includes a first sidewall, a second sidewall opposing the first sidewall, a third sidewall connecting the first and second sidewalls, a fourth sidewall opposing the third sidewall, and the first gate dielectric layer are disposed on the first, second, third, and fourth sidewalls of the storage gate electrode layer," in combination with the other limitations recited in the claim. Claims 2, 4-8, and 21 depend on claim 1; and therefore, are allowable for at least these reasons.
Regarding independent claim 14, the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed limitation(s) of "a control gate disposed over the isolation region, wherein the control gate interfaces with the storage node from the upper surface of the isolation region to an upper surface of the storage node," in combination with the other limitations recited in the claim. Claims 15-20 depend on claim 14; and therefore, are allowable for at least these reasons.
Claims 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUSTIN BRYCE HEISTERKAMP whose telephone number is (703)756-1095. The examiner can normally be reached M-F 0800-1700.
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/JUSTIN BRYCE HEISTERKAMP/Examiner, Art Unit 2827 /AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827