DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-15, 17-18, and 23-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 March 2026.
Applicant has stated that claims 17-18 and 23-26 read on the elected species, however, the claims contain language which differentiate them from the elected species 2 for at least the following reasons:
With regards to claims 17-18 and 23-26, the claims feature or are dependent upon claims which feature the limitation “a third work function metal layer”, whereas the elected species 3 as depicted in FIG. 17A-17B is drawn to a semiconductor device having only two work function metal layers.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 436 in Fig. 17B. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 31 is objected to because of the following informalities: missing “comprises” in “wherein the work function metal film stack comprises an amorphous portion and a polycrystalline portion”. For the purpose of examination, the examiner will interpret the claim as including the term. Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 20 recites the limitation "wherein the amorphous portion is formed on the polycrystalline film above the top surface of the fin structure". There is insufficient antecedent basis for “the amorphous portion” in the claim. For the purpose of examination, the examiner interprets the claim as instead reciting “an amorphous portion”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-35 are rejected under 35 U.S.C. 103 as being unpatentable over Savant et al. (US 20220130677 A1, hereinafter S1), and further in view of Kuo et al. (US 9472638 B2, hereinafter K1).
Regarding independent claim 16, S1 discloses in FIG. 1A-5C and associated text A method, comprising: forming a fin structure (fin structure 110); forming a sacrificial gate structure over the fin structure (not shown, but a sacrificial gate stack is disclosed in S1 [0019] and [0030], stating that gate stack opening 155 is left after its removal. Gate stack opening 155 is over fin structure 110 therefore the sacrificial gate structure is formed over fin structure 110); removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin structure (removing the sacrificial gate stack is disclosed in S1 [0019] and [0030], leaving the sidewalls and top surface of fin structure 110 exposed in gate stack opening 155, as shown in S1 FIG. 1B); depositing a gate dielectric layer on the top surface and two sidewalls of the fin structure (gate dielectric layer 303, S1 FIG. 5A); depositing a work function metal film stack over the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack), and depositing a gate fill layer over the work function metal film stack (metal layer 531, S1 FIG. 5A). S1 does not explicitly disclose etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses; forming source/drain regions in source/drain recesses; or the work function metal film stack has a first thickness over the top surface of the fin structure and a second thickness of along the two sidewalls of the fin structure, and the first thickness is greater than the second thickness.
However, in the same field of endeavor, K1 discloses in K1 FIG. 6A-6B and associated text etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses (K1 (14): the formation of source and drain regions 48 may also comprise etching portions of fin 24 that are not covered by metal layers 34, 40, and 42); forming source/drain regions in source/drain recesses (K1 (14): performing an epitaxy to grow stressors (referring to the etched portion/recess previously described)…. The stressors are then implanted to form source/drain regions 48); and the work function metal film stack (capping layer 30 and metal layers 34 and 40 analogous to the work function metal stack components in S1 as described above) has a first thickness over the top surface of the fin structure and a second thickness of along the two sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain region formation steps and the dimensions of the work function metal film stack of K1 to provide a FinFET with source/drain regions to make a functional transistor and different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 19, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text the method of claim 16, wherein depositing the work function metal film stack comprises: forming an amorphous portion over the gate dielectric layer (diffusion barrier 523 is an amorphous portion (S1 [0045]) and formed over gate dielectric layer 303).
Regarding dependent claim 20, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text the method of claim 16, wherein depositing the work function metal film stack further comprises: depositing a polycrystalline film on the gate dielectric layer (work function stacks 411A-411B include work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline, and are over gate dielectric layer 303, as shown in S1 FIG. 5C), wherein an amorphous portion is formed on the polycrystalline film above the top surface of the fin structure (diffusion barrier 523 is an amorphous portion (S1 [0045]) and formed over work function layers 413A-413B.
Regarding independent claim 21, S1 discloses in S1 FIG. 1A-5C a method, comprising: forming a semiconductor device comprising: a fin structure (fin structures 110); and a gate structure disposed over a top surface and sidewalls of the fin structure (the following elements comprise the claimed gate structure and are all formed over fin structures 110 as shown in S1 FIG. 5A-5C), wherein the gate structure comprises: a gate dielectric layer (gate dielectric layer 303); and a work function metal film stack (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack). S1 does not explicitly disclose a first source/drain region; a second source/drain region; the fin structure is disposed between the first source/drain region and the second source/drain region or the work function metal film stack is non-conformal in at least one of thickness and phase.
However, in the same field of endeavor, K1 discloses in K1 FIG. 6A-6B and associated text a first source/drain region and a second source/drain region (source and drain regions 48); the fin structure is disposed between the first source/drain region and the second source/drain region (fin24 is between source and drain regions 48 as shown in K1 FIG. 6A) or the work function metal film stack is non-conformal in at least one of thickness and phase (capping layer 30 and metal layers 34 and 40 analogous to the work function metal stack components in S1 as described above are non-conformal in thickness as shown in FIG. 6B and the annotated figure below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain regions and the non-conformal thicknesses of the work function metal film stack of K1 to provide a FinFET with source/drain regions to make a functional transistor and different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 22, S1, as modified by K1, further discloses in K1 FIG. 6A-6B and associated text the method of claim 21, wherein forming the semiconductor device comprises forming the work function metal film stack has a first thickness over the top surface of the fin structure and a second thickness along the sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure above).
Regarding dependent claim 27, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 21, wherein the work function metal film stack has an amorphous portion (diffusion barrier 523 is an amorphous portion (S1 [0045])) and a polycrystalline portion (work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline).
Regarding dependent claim 28, S1, as modified by K1, further discloses in S1 The method of claim 27, wherein the work function metal film stack comprises: a first work function metal layer disposed on the gate dielectric layer, wherein the amorphous portion is in the first work function metal layer (diffusion barrier 523, which is amorphous (S1 [0045]), and work function stacks 411A-411B together are considered a first work function metal layer); and a second work function metal layer disposed on the first work function metal layer (glue layer 529 is considered a second work function metal layer and is disposed on diffusion barrier 523 and work function stacks 411A-411B).
Regarding dependent claim 29, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 28, wherein the first work function metal layer is amorphous over the top surface and the sidewalls of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and sidewalls of fin structure 110).
Regarding dependent claim 30, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 28, wherein the first work function metal layer is amorphous over the top surface of the fin structure and polycrystalline over the sidewalls of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and polycrystalline portions work function layers 413A-413B are over sidewalls of fin structure 110).
Regarding independent claim 31, S1 discloses in S1 FIG. 1A-5C and associated text A method, comprising: forming a fin structure (fin structures 110); forming a sacrificial gate structure over the fin structure (not shown, but a sacrificial gate stack is disclosed in S1 [0019] and [0030], stating that gate stack opening 155 is left after its removal. Gate stack opening 155 is over fin structure 110 therefore the sacrificial gate structure is formed over fin structure 110); removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin structure (removing the sacrificial gate stack is disclosed in S1 [0019] and [0030], leaving the sidewalls and top surface of fin structure 110 exposed in gate stack opening 155, as shown in S1 FIG. 1B); depositing a gate dielectric layer on the top surface and two sidewalls of the fin structure (gate dielectric layer 303); depositing a work function metal film stack over the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack), wherein the work function metal film stack comprises an amorphous portion (diffusion barrier 523 is an amorphous portion (S1 [0045])) and a polycrystalline portion (work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline); and depositing a gate fill layer over the work function metal film stack (metal layer 531, S1 FIG. 5A). S1 does not explicitly disclose etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses or forming source/drain regions in source/drain recesses.
However, in the same field of endeavor, K1 discloses etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses (K1 (14): the formation of source and drain regions 48 may also comprise etching portions of fin 24 that are not covered by metal layers 34, 40, and 42); forming source/drain regions in source/drain recesses (K1 (14): performing an epitaxy to grow stressors (referring to the etched portion/recess previously described)…. The stressors are then implanted to form source/drain regions 48).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain region formation steps of K1 to provide a FinFET with source/drain regions to make a functional transistor.
Regarding dependent claim 32, S1, as previously modified by K1, discloses the method of claim 31. As previously combined, they do not explicitly disclose the work function metal film stack has a first thickness over the top surface of the fin structure and a second thickness of along the first and second sidewalls of the fin structure, and the first thickness is greater than the second thickness.
However, in the same field of endeavor, K1 discloses the work function metal film stack (capping layer 30 and metal layers 34 and 40 analogous to the work function metal stack components in S1 as described above) has a first thickness over the top surface of the fin structure and a second thickness of along the first and second sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure below).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the dimensions of the work function metal film stack of K1 to provide a FinFET with different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 33, S1, as modified by K1, further discloses in K1 FIG. 6B and associated text The method of claim 32, wherein a ratio of the first thickness over the second thickness is in a range between about 1.1 and about 1.5 (the work function metal film stack of K1 appears to have a thickness ratio of approximately between 1.5 and 2.0 in K1 FIG. 6B and the annotated figure above which is considered to be “about” 1.5 as claimed). Additionally, the thicknesses of layers 30, 34, and 40 which the work function metal film stack comprises are identified as affecting the threshold voltage of the resulting FinFET (K1 (9)). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to form the work function metal film stack such that the ratio of first and second thicknesses falls within a range which produces a semiconductor with their desired relationship between top and side threshold voltages including those which fall within the claimed range of thicknesses with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding dependent claim 34, S1, as modified by K1, further discloses in S1 FIG. 5A and associated text The method of claim 33, wherein the fin structure has a width from the first sidewall to the second sidewall, and a ratio of the second thickness over the width is in a range between about 0.5 and about 1.0 (the work function metal film stack comprising layers 411A-411B, 523, and 529 of S1 has a sidewall thickness which appears to be less than or approximately equal to a width of the fin structures 110 and falling within the claimed range as shown in S1 FIG. 5A and the annotated figure below).
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Regarding dependent claim 35, S1, as modified by K1, further discloses in K1 FIG. 5A-5C and associated text The method of claim 31, wherein the work function metal film stack comprises: an amorphous portion disposed over the top surface of the fin structure and a polycrystalline portion disposed on the first sidewall, the second sidewall, and the top surface of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and polycrystalline portions work function layers 413A-413B are over both sidewalls and the top surface of fin structure 110).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20080157212 A1, pertaining to an amorphous work function metal layer disposed as a diffusion barrier over another work function metal layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571) 272-9559. The examiner can normally be reached Mon - Thu 8:30 am - 6:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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