DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made of the amendment filed 07/23/2026, in which: claim(s) 16, 20-22, 27-28, 31, and 35 is/are amended; claim(s) 24 is/are cancelled; claim(s) 36 is/are new; and the rejection of the claims are traversed. Claim(s) 16, 19-22, and 27-36 is/are currently pending an Office action on the merits as follows.
Response to Arguments
Applicant's arguments filed 07/23/2026, with respect to the rejection(s) of claim(s) 16, 21, and 31, as amended, have been fully considered but they are not persuasive. Applicant has not set forth a specific argument as to the reason for the patentability of the amended claims over the prior art of record. Examiner respectfully disagrees that S1, as modified by K1, fails to disclose the limitations of the amended claims. A full rejection of the claims, as amended, follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-35 are rejected under 35 U.S.C. 103 as being unpatentable over Savant et al. (US 20220130677 A1, hereinafter S1), and further in view of Kuo et al. (US 9472638 B2, hereinafter K1).
Regarding independent claim 16, S1 discloses in FIG. 1A-5C and associated text A method, comprising: forming a fin structure (fin structure 110); forming a sacrificial gate structure over the fin structure (not shown, but a sacrificial gate stack is disclosed in S1 [0019] and [0030], stating that gate stack opening 155 is left after its removal. Gate stack opening 155 is over fin structure 110 therefore the sacrificial gate structure is formed over fin structure 110); removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin structure (removing the sacrificial gate stack is disclosed in S1 [0019] and [0030], leaving the sidewalls and top surface of fin structure 110 exposed in gate stack opening 155, as shown in S1 FIG. 1B); depositing a gate dielectric layer on the top surface and two sidewalls of the fin structure (gate dielectric layer 303, S1 FIG. 5A); depositing a work function metal film stack over the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack), wherein depositing the work function metal film stack comprises depositing a first work function metal layer in contact with the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 altogether are considered the first work function metal layer and are in contact with gate dielectric layer 303), and depositing a gate fill layer over the work function metal film stack (metal layer 531, S1 FIG. 5A). S1 does not explicitly disclose etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses; forming source/drain regions in source/drain recesses; or the first work function metal layer has a first thickness over the top surface of the fin structure and a second thickness of along the two sidewalls of the fin structure, and the first thickness is greater than the second thickness.
However, in the same field of endeavor, K1 discloses in K1 FIG. 6A-6B and associated text etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses (K1 (14): the formation of source and drain regions 48 may also comprise etching portions of fin 24 that are not covered by metal layers 34, 40, and 42); forming source/drain regions in source/drain recesses (K1 (14): performing an epitaxy to grow stressors (referring to the etched portion/recess previously described)…. The stressors are then implanted to form source/drain regions 48); and the first work function metal layer (capping layer 30 and metal layer 34 together are analogous to the first work function metal layer components in S1 as described above) has a first thickness over the top surface of the fin structure and a second thickness of along the two sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure below).
PNG
media_image1.png
534
549
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain region formation steps and the dimensions of the first work function metal layer of K1 to provide a FinFET with source/drain regions to make a functional transistor and different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 19, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text the method of claim 16, wherein depositing the work function metal film stack comprises: forming an amorphous portion over the gate dielectric layer (diffusion barrier 523 is an amorphous portion (S1 [0045]) and formed over gate dielectric layer 303).
Regarding dependent claim 20, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text the method of claim 19, wherein depositing the work function metal film stack further comprises: depositing a polycrystalline film on the gate dielectric layer (work function stacks 411A-411B include work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline, and are over gate dielectric layer 303, as shown in S1 FIG. 5C), wherein the amorphous portion is formed on the polycrystalline film above the top surface of the fin structure (diffusion barrier 523 is an amorphous portion (S1 [0045]) and formed over work function layers 413A-413B).
Regarding independent claim 21, S1 discloses in S1 FIG. 1A-5C a method, comprising: forming a semiconductor device comprising: a fin structure (fin structures 110); and a gate structure disposed over a top surface and sidewalls of the fin structure (the following elements comprise the claimed gate structure and are all formed over fin structures 110 as shown in S1 FIG. 5A-5C), wherein the gate structure comprises: a gate dielectric layer (gate dielectric layer 303); and a work function metal film stack (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack) wherein the work function metal film stack comprises a first work function metal layer in contact with the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 altogether are considered the first work function metal layer and are in contact with gate dielectric layer 303), wherein the first work function metal layer is disposed over the top surface and sidewalls of the fin structure (411A-411B and 523 are over the top surface and sidewalls of 110). S1 does not explicitly disclose a first source/drain region; a second source/drain region; the fin structure is disposed between the first source/drain region and the second source/drain region or the first work function metal layer is non-conformal in at least one of thickness and phase.
However, in the same field of endeavor, K1 discloses in K1 FIG. 6A-6B and associated text a first source/drain region and a second source/drain region (source and drain regions 48); the fin structure is disposed between the first source/drain region and the second source/drain region (fin24 is between source and drain regions 48 as shown in K1 FIG. 6A) or the first work function metal layer is non-conformal in at least one of thickness and phase (capping layer 30 and metal layer 34 together are analogous to the first work function metal layer components in S1 as described above and are non-conformal in thickness as shown in FIG. 6B and the annotated figure below).
PNG
media_image1.png
534
549
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain regions and the non-conformal thicknesses of the first work function metal layer of K1 to provide a FinFET with source/drain regions to make a functional transistor and different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 22, S1, as modified by K1, further discloses in K1 FIG. 6A-6B and associated text the method of claim 21, wherein forming the semiconductor device comprises forming the first work function metal layer having a first thickness over the top surface of the fin structure and a second thickness along the sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure above).
Regarding dependent claim 27, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 21, wherein the first work function metal layer has an amorphous portion (diffusion barrier 523 is an amorphous portion (S1 [0045])) and a polycrystalline portion (work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline).
Regarding dependent claim 28, S1, as modified by K1, further discloses in S1 The method of claim 27, wherein the work function metal film stack comprises: the first work function metal layer disposed on the gate dielectric layer, wherein the amorphous portion is in the first work function metal layer (diffusion barrier 523, which is amorphous (S1 [0045]), and work function stacks 411A-411B together are considered a first work function metal layer); and a second work function metal layer disposed on the first work function metal layer (glue layer 529 is considered a second work function metal layer and is disposed on diffusion barrier 523 and work function stacks 411A-411B).
Regarding dependent claim 29, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 28, wherein the first work function metal layer is amorphous over the top surface and the sidewalls of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and sidewalls of fin structure 110).
Regarding dependent claim 30, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 28, wherein the first work function metal layer is amorphous over the top surface of the fin structure and polycrystalline over the sidewalls of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and polycrystalline portions work function layers 413A-413B are over sidewalls of fin structure 110).
Regarding independent claim 31, S1 discloses in S1 FIG. 1A-5C and associated text A method, comprising: forming a fin structure (fin structures 110); forming a sacrificial gate structure over the fin structure (not shown, but a sacrificial gate stack is disclosed in S1 [0019] and [0030], stating that gate stack opening 155 is left after its removal. Gate stack opening 155 is over fin structure 110 therefore the sacrificial gate structure is formed over fin structure 110); removing the sacrificial gate structure to expose two sidewalls and a top surface of the fin structure (removing the sacrificial gate stack is disclosed in S1 [0019] and [0030], leaving the sidewalls and top surface of fin structure 110 exposed in gate stack opening 155, as shown in S1 FIG. 1B); depositing a gate dielectric layer on the top surface and two sidewalls of the fin structure (gate dielectric layer 303); depositing a work function metal film stack over the gate dielectric layer (work function stacks 411A-411B and diffusion barrier layer 523 and glue layer 529 (S1 FIG. 5A) which are similarly considered work function metal layers and part of the claimed work function metal film stack) comprising depositing a first work function metal layer (work function stacks 411A-411B and diffusion barrier layer 523 altogether are considered the first work function metal layer) comprising an amorphous portion (diffusion barrier 523 is an amorphous portion (S1 [0045])) and a polycrystalline portion (work function layers 413A-413B, which have crystallinity of 65% to 100% (S1 [0037]), making them polycrystalline), wherein the first work function metal layer is in contact with the gate dielectric layer (411A-411B and 523 are in contact with gate dielectric layer 303); and depositing a gate fill layer over the work function metal film stack (metal layer 531, S1 FIG. 5A). S1 does not explicitly disclose etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses or forming source/drain regions in source/drain recesses.
However, in the same field of endeavor, K1 discloses etching the fin structure on both sides of the sacrificial gate structure to form source/drain recesses (K1 (14): the formation of source and drain regions 48 may also comprise etching portions of fin 24 that are not covered by metal layers 34, 40, and 42); forming source/drain regions in source/drain recesses (K1 (14): performing an epitaxy to grow stressors (referring to the etched portion/recess previously described)…. The stressors are then implanted to form source/drain regions 48).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the source/drain region formation steps of K1 to provide a FinFET with source/drain regions to make a functional transistor.
Regarding dependent claim 32, S1, as previously modified by K1, discloses the method of claim 31. As previously combined, they do not explicitly disclose the work function metal film stack has a first thickness over the top surface of the fin structure and a second thickness of along the first and second sidewalls of the fin structure, and the first thickness is greater than the second thickness.
However, in the same field of endeavor, K1 discloses the work function metal film stack (capping layer 30 and metal layers 34 and 40 analogous to the work function metal stack components in S1 as described above) has a first thickness over the top surface of the fin structure and a second thickness of along the first and second sidewalls of the fin structure, and the first thickness is greater than the second thickness (the claimed relationship between thicknesses is shown in K1 FIG. 6B and the annotated figure below).
PNG
media_image2.png
534
549
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the overall fin structure and work function metal film stack of S1 with the dimensions of the work function metal film stack of K1 to provide a FinFET with different threshold voltages for top and side regions of the fin so that the saturation current of the resulting transistor may be adjusted by the gate voltage (K1 (23)).
Regarding dependent claim 33, S1, as modified by K1, further discloses in K1 FIG. 6B and associated text The method of claim 32, wherein a ratio of the first thickness over the second thickness is in a range between about 1.1 and about 1.5 (the work function metal film stack of K1 appears to have a thickness ratio of approximately between 1.5 and 2.0 in K1 FIG. 6B and the annotated figure above which is considered to be “about” 1.5 as claimed). Additionally, the thicknesses of layers 30, 34, and 40 which the work function metal film stack comprises are identified as affecting the threshold voltage of the resulting FinFET (K1 (9)). Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to form the work function metal film stack such that the ratio of first and second thicknesses falls within a range which produces a semiconductor with their desired relationship between top and side threshold voltages including those which fall within the claimed range of thicknesses with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding dependent claim 34, S1, as modified by K1, further discloses in S1 FIG. 5A and associated text The method of claim 33, wherein the fin structure has a width from the first sidewall to the second sidewall, and a ratio of the second thickness over the width is in a range between about 0.5 and about 1.0 (the work function metal film stack comprising layers 411A-411B, 523, and 529 of S1 has a sidewall thickness which appears to be less than or approximately equal to a width of the fin structures 110 and falling within the claimed range as shown in S1 FIG. 5A and the annotated figure below).
PNG
media_image3.png
547
444
media_image3.png
Greyscale
Regarding dependent claim 35, S1, as modified by K1, further discloses in S1 FIG. 5A-5C and associated text The method of claim 31, wherein the amorphous portion of the first work function metal layer is disposed over the top surface of the fin structure, and the polycrystalline portion disposed on the first sidewall, the second sidewall, and the top surface of the fin structure (amorphous portion diffusion barrier 523 is over the top surface and polycrystalline portions work function layers 413A-413B are over both sidewalls and the top surface of fin structure 110).
Regarding dependent claim 36, S1, as modified by K1, further discloses in S1 FIG. 3A-5C and associated text The method of claim 31, wherein depositing the first work function metal layer comprises: depositing the polycrystalline portion on the gate dielectric layer (polycrystalline work function layers 413A-413B are deposited); and adjusting deposition temperature or pressure to deposit the amorphous portion over the polycrystalline portion (amorphous diffusion barrier layer 523 is deposited over 413A-413B, as shown, at a temperature range of 150° C to 600° C (S1 [0043]), which is different from the temperature range for deposition of 413A-413B, which are deposited at a temperature range of 300° C to 550° C (S1 [0037]), therefore deposition temperature is adjusted to deposit 523).
Conclusion
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to the applicant’s disclosure:
US 20080157212 A1, pertaining to an amorphous work function metal layer disposed as a diffusion barrier over another work function metal layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVERETT TRAJAN RIRIE whose telephone number is (571)272-9559. The examiner can normally be reached Mon - Thu: 8:30 am - 6:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVERETT T RIRIE/Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights