DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-18, 21, and 22) in the reply filed on 2/20/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21, and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification does not describe “at least one alternating current terminal”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 thru 4, 11, and 12 is/are rejected under 35 U.S.C. 102(a0(1) as being anticipated by Hoegerl et al. US 2017/0316994 A1. Hoegerl discloses (see, for example, FIG 16) an assembly 100 comprising a panel of organic substrate core material 116, cavity (i.e. area between the organic substrate core material 116), module substrate 102/126, semiconductor die 108, layer of prepreg organic substrate material 180, and metal layer 182. In paragraph [0070], Hoegerl discloses the organic substrate core material 116 including FR4, a type of organic substrate, and in paragraph [0068], Hoegerl discloses the layer of organic substrate material 180 being prepreg.
Regarding claim 2, see, for example, FIG. 16, and paragraph [0068] wherein Hoegerl
discloses the layer of prepreg organic substrate material includes a plurality of layers 180 of prepreg organic substrate material.
Regarding claim 3, see, for example, FIG. 16 wherein Hoegerl discloses the cavity including an opening defined through the panel of organic substrate core material 116.
Regarding claim 4, see, for example, paragraph [0065] wherein Hoegerl discloses the module structure 102 being a copper substrate.
Regarding claim 11, see, for example, FIG 16 wherein Hoegerl discloses the patterned metal layer 182.
Regarding claim 12, see, for example, FIG 16 wherein Hoegerl discloses conductive via 130.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In view of the 112 rejection above, claim(s) 5 thru 7, 10, 13, 14, 21, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl et al. US 2017/0316994 A1 as applied to claims 1-4, and 11-12 above, and further in view of Palm et al. US 2022/0230982. Hoegerl does not disclose the layer of prepreg organic substrate material being a first layer of prepreg organic substrate material; and the metal layer being a first metal layer, the assembly further comprising: a second layer of prepreg organic substrate material; and a second metal layer, the module substrate and the semiconductor die being further embedded in the cavity by the second layer of prepreg organic substrate material and the second metal layer. However, Palm discloses (see, for example, FIG. 5A) an assembly 300 comprising a first layer of prepreg organic substrate material 304, a first metal layer 310T, second layer of prepreg organic substrate material 304, and second metal layer 312T. In FIG. 5A, Palm discloses multiple layers of organic substrate material on top of metal layers in succession to create stacks for making extensive routing electrical networks. In paragraph [0094], Palm discloses the substrate material 304 including prepreg material. It would have been obvious to one of ordinary skill in the art to have the layer of prepreg organic substrate material being a first layer of prepreg organic substrate material; and the metal layer being a first metal layer, the assembly further comprising: a second layer of prepreg organic substrate material; and a second metal layer, the module substrate and the semiconductor die being further embedded in the cavity by the second layer of prepreg organic substrate material and the second metal layer in order to make further connections to the semiconductor die, and create a more robust routing network according to the preferences of the user.
Regarding claim 6, see, for example, FIG. 5A wherein Palm discloses the second metal
layer 312T being electrically coupled to the first metal layer 310T.
Regarding claim 7, see, for example, FIG. 5D wherein Palm discloses a second metal layer 314T being exposed through a second layer of prepreg organic substrate material 304.
Regarding claim 10, see, for example, FIG. 5A wherein Palm discloses a socket 330 including a signal pin 330 that is electrically coupled with a semiconductor die 201 via a metal layer 310T. It would have been obvious to one of ordinary skill in the art to have a metal-plated socket, and a signal pin in order to have an external connection for making multiple electrical connections between the semiconductor die and other structures within the assembly.
Regarding claim 13, see, for example, FIG. 2B wherein Palm discloses a layer of prepreg material 230 and a first metal layer 232T on a first side of the panel of the panel of organic substrate core material, and a second metal layer 232B1 on a second side of the panel of organic substrate core material. It would have been obvious to one of ordinary skill in the art to have a first metal layer on a first side of the panel of the panel of organic substrate core material and a second metal layer on a second side of the panel of organic substrate core material in order to make further connections to the semiconductor die around the limited space of the assembly according to the preferences of the user.
Regarding claim 14, see, for example, FIG. 5A wherein Palm discloses a second layer prepreg material organic substrate material 304, second metal layer 310B, and plurality of vias 310B. It would have been obvious to one of ordinary skill in the art to have a second layer prepreg material organic substrate material, second metal layer, and plurality of vias in order to make further connections to the semiconductor die around the limited space of the assembly according to the preferences of the user.
Regarding claim 21, see, for example, paragraph [0119], and FIG. 3B wherein Palm discloses chips including functional blocks such as a half-bridge circuit wherein the metal layer 310T/330 may comprise at least one current terminal, which may serve as a direct current terminal or alternating current terminal. Further, it has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex Parte Masham, 2 USPQ F. 2d 1647 (1987). Also see 112 rejection above.
Regarding claim 22, see, for example, FIG. 3B wherein Palm discloses a passive device 126 on top of the assembly 300, and is coupled to the semiconductor module 200 through the metal layer 310T.
Claim(s) 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl et al. US 2017/0316994 A1 as applied to claims 1-4, and 11-12 above, and further in view of CN109427744 A as disclosed by IDS filed 3/27/24. Hoegerl does not disclose the cavity is a first cavity, the panel of organic substrate core material including a second cavity; the module substrate is a first module substrate; and the semiconductor die is a first semiconductor die, the assembly further comprising: a second module substrate disposed in the second cavity; and a second semiconductor die disposed on the second module substrate; the second module substrate and the second semiconductor die being embedded in the second cavity by the layer of prepreg organic substrate material and the metal layer. However, CN109427744A discloses (see, for example, figure 4) an assembly comprising a first cavity, first module substrate 3, second cavity, first semiconductor die 7, and second semiconductor die 7. It would have been obvious to one of ordinary skill in the art to have the cavity being a first cavity, the panel of organic substrate core material including a second cavity; the module substrate being a first module substrate; and the semiconductor die being a first semiconductor die, the assembly further comprising: a second module substrate disposed in the second cavity; and a second semiconductor die disposed on the second module substrate; the second module substrate and the second semiconductor die being embedded in the second cavity by the layer of prepreg organic substrate material and the metal layer in order to accommodate multiple chips within the same assembly, and, therefore, form more robust electronic devices according to the preferences of the user. Further, it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St, Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 9, see, for example, figure 4 wherein CN109427744A discloses a metal
layer 83 couples a first semiconductor die 7 with a second module substrate 3.
Claim(s) 15 thru 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hoegerl et al. US 2017/0316994 A1 in view of CN 109427755A as applied to claims 8, and 9 above, and further in view of Palm et al. US 2022/0230982. Hoegerl in view of CN 109427755A does not disclose the layer of prepreg organic substrate material being a first layer of prepreg organic substrate material; and the metal layer being a first metal layer, the assembly further comprising: a second layer of prepreg organic substrate material; and a second metal layer, the module substrate and the semiconductor die being further embedded in the cavity by the second layer of prepreg organic substrate material and the second metal layer. However, Palm discloses (see, for example, FIG. 5A) an assembly 300 comprising a first layer of prepreg organic substrate material 304, a first metal layer 310T, second layer of prepreg organic substrate material 304, and second metal layer 312T. In FIG. 5A, Palm discloses multiple layers of organic substrate material on top of metal layers in succession to create stacks for making extensive routing electrical networks. In paragraph [0094], Palm discloses the substrate material 304 including prepreg material. It would have been obvious to one of ordinary skill in the art to have the layer of prepreg organic substrate material being a first layer of prepreg organic substrate material; and the metal layer being a first metal layer, the assembly further comprising: a second layer of prepreg organic substrate material; and a second metal layer, the module substrate and the semiconductor die being further embedded in the cavity by the second layer of prepreg organic substrate material and the second metal layer in order to make further connections to the semiconductor die, and create a more robust routing network according to the preferences of the user.
Regarding claim 16, see, for example, FIG. 5D wherein Palm discloses a second metal layer 314T being exposed through a second layer of prepreg organic substrate material 304.
Regarding claim 17, see, for example, FIG. 16, and paragraph [0068] wherein Hoegerl
discloses the layer of prepreg organic substrate material includes a plurality of layers 180 of prepreg organic substrate material.
Regarding claim 18, see, for example, FIG. 5A wherein Palm discloses a first layer of prepreg material 304, first metal layer 310T, second layer of prepreg material 304, second metal layer 312T, and third metal layer 314B. It would have been obvious to one of ordinary skill in the art to have a first layer of prepreg material, first metal layer, second layer of prepreg material, second metal layer, and third metal layer in order to make further connections to the semiconductor die according to the preferences of the user.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Eugene Lee
March 1, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815