Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 13 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
Amendment to the Specification filed on 03/30/2026 has been reviewed and entered.
Allowable Subject Matter
Claims 1-12 are allowed.
The following is an examiner’s statement of reasons for allowance:
The primary reason for the allowance of the claim is the inclusion of the limitation “a second source/drain layer having a different dopant concentration than the first source/drain layer and separated from the channels by the first source/drain layer;
a silicide layer in contact with a top surface of the first source/drain layer, in contact with a sidewall of the first source/drain layer, in contact with a top surface of the second source/drain layer, in contact with a sidewall of the second source/drain layer,” as recited in independent claim 1, in all of the claims which is not found in the prior art references.
Claims 2-12 are allowed for the same reasons as claim 1, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. et al. (U.S. 2019/0348498 A1, hereinafter refer to Cheng).
Regarding Claim 13: Cheng discloses an integrated circuit (see Cheng, Fig.17C as shown below and ¶ [0023]), comprising:
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a first transistor (see Cheng, Fig.17C as shown above) including:
a plurality of stacked channels (232) (see Cheng, Fig.17C as shown above);
a gate spacer layer (211) above the channels (232) (see Cheng, Fig.17C as shown above);
a first source/drain region (220, note: layer 220 which is formed on the first transistor region is considered as a first source/drain region) in contact with a sidewall of the gate spacer layer (211) (see Cheng, Fig.17C as shown above and ¶ [0033]); and
a first silicide layer (270) on a top surface and a on sidewall of the first source/drain region (220) and in contact with the sidewall of the gate spacer layer (211) above the first source/drain region (220) (see Cheng, Fig.17C as shown above and ¶ [0043]);
a second transistor (see Cheng, Fig.17C as shown above) including:
a second source/drain region (220, note: layer 220 which is formed on the second transistor region is considered as a second source/drain region) (see Cheng, Fig.17C as shown above); and
a second silicide layer (270) on a top surface and on a sidewall of the second source/drain region (220) (see Cheng, Fig.17C as shown above and ¶ [0043]); and
a source/drain contact (280) in contact with a top surface of the first silicide layer (270), a sidewall of the first silicide layer (270), a top surface of the second silicide layer (270), and a sidewall of the second silicide layer (270) (see Cheng, Fig.17C as shown above).
Regarding Claim 14: Cheng discloses an integrated circuit as set forth in claim 13 as above. Cheng further teaches wherein the source/drain contact (280) has a T shape (see Cheng, Fig.17C as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. et al. (U.S. 2019/0348498 A1, hereinafter refer to Cheng) as applied to claim 13 above, and further in view of Hall et al. (U.S. 2023/0290862 A1, hereinafter refer to Hall).
Regarding Claim 15: Cheng discloses an integrated circuit as applied to claim 13 above. Cheng is silent upon explicitly disclosing wherein a bottom dielectric layer in contact with a bottom of the first source/drain region, a bottom of the first silicide layer, a bottom of the second silicide layer, and a bottom of the second source/drain region.
For support see Hall, which teaches wherein a bottom dielectric layer (50) in contact with a bottom of the first source/drain region (51), a bottom of the first silicide layer (63) (see Hall, Fig.23 as shown below and ¶ [0073]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Cheng and Hall to enable a bottom dielectric layer in contact with a bottom of the source/drain region and a bottom of the silicide layer as taught by Hall in order to improve the performance of the final nanosheet FET device.
The combination of Cheng and Hall is silent upon explicitly disclosing wherein a bottom dielectric layer in contact with a bottom of the second silicide layer, and a bottom of the second source/drain region.
However, practicing the combination of Cheng and Hall to modify Cheng to enable the bottom dielectric layer to be in contact with the bottom of the first source/drain region and bottom of the first silicide layer as taught by Hall necessarily results “bottom dielectric layer in contact with a bottom of the second silicide layer, and a bottom of the second source/drain region” as now specified in claim 15.
Regarding Claim 16: Cheng as modified teaches an integrated circuit as set forth in claim 13 as above. The combination of Cheng and Hall further teaches wherein the bottom dielectric layer (50) is in contact with a bottom of the source/drain contact (64) (see Hall, Fig.23 as shown above).
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. et al. (U.S. 2019/0348498 A1, hereinafter refer to Cheng) as applied to claim 13 above, and further in view of Lin et al. (U.S. 2023/0061857 A1, hereinafter refer to Lin).
Regarding Claim 17: Cheng discloses an integrated circuit as applied to claim 13 above. Cheng is silent upon explicitly disclosing wherein a backside conductive via extending through a substrate below the first and second transistors and contacting a bottom of the source/drain contact.
For support see Lin, which teaches wherein a backside conductive via (280) extending through a substrate (270) below the first and second transistors and contacting a bottom of the source/drain contact (264/261/260) (see Lin, Fig.16 as shown below and ¶ [0012]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Cheng and Lin to enable a backside conductive via extending through a substrate below the first and second transistors and contacting a bottom of the source/drain contact as taught by Lin in order to improve contact resistance and has larger interface with the metal silicide layer.
Claim(s) 20-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. et al. (U.S. 2019/0348498 A1, hereinafter refer to Cheng) in view of Lin et al. (U.S. 2023/0061857 A1, hereinafter refer to Lin) and Hall et al. (U.S. 2023/0290862 A1, hereinafter refer to Hall).
Regarding Claim 18: Cheng discloses a method (see Cheng, Fig.17C as shown above and ¶ [0023]), comprising:
forming a plurality of vertically stacked first channels (232) of a first transistor over a substrate (202) (see Cheng, Fig.17C as shown above);
forming a plurality of vertically stacked second channels (232) of a second transistor over the substrate (202) (see Cheng, Fig.17C as shown above);
forming a plurality of first inner spacers (211) interleaved with the first channels (232) (see Cheng, Fig.17C as shown above);
forming a plurality of second inner spacers (211) interleaved with the second channels (232) (see Cheng, Fig.17C as shown above);
forming a first source/drain region (220, note: layer 220 which is formed on the first transistor region is considered as a first source/drain region) in contact with sidewalls of the first channels (232) (see Cheng, Fig.17C as shown above);
forming a first silicide layer (270, note: layer 270 which is formed on the first transistor region is considered as a first silicide layer) in contact with a top surface of the first source/drain region (220), in contact with a first sidewall of the source/drain region (220), and extending lower than at least one of the first channels (232) (see Cheng, Fig.17C as shown above);
forming a second source/drain region (220, note: layer 220 which is formed on the second transistor region is considered as a second source/drain region) in contact with sidewalls of the second channels (232) (see Cheng, Fig.17C as shown above);
forming a second silicide layer (270, note: layer 270 which is formed on the second transistor region is considered as a second silicide layer) in contact with a top surface of the second source/drain region (220), in contact with a sidewall of the second source/drain region (220), and extending lower than at least one of the second channels (232) (see Cheng, Fig.17C as shown above); and
forming a source/drain contact (280) between and in contact with the first silicide layer (270) and the second silicide layer (270) (see Cheng, Fig.17C as shown above).
Cheng is silent upon explicitly disclosing wherein forming a bottom dielectric structure coupled to a sidewall of a lowest first inner spacer and a lowest second inner spacer;
forming a backside conductive via in the substrate and contacting a bottom of the source/drain contact and in contact a sidewall of the bottom dielectric structure between the lowest first channel and the lowest second channel.
For support see Lin, which teaches wherein forming a bottom dielectric structure (270) coupled to a sidewall of a lowest first inner spacer (218) and a lowest second inner spacer (218) (see Lin, Fig.16 as shown above and ¶ [0012]);
forming a backside conductive via (280) in the substrate (270, note: the Lin integral layer 270 is equivalent to the claimed limitation of separable layers of “bottom dielectric structure” and “substrate” because making duplication of layer has no patentable significance unless a new and unexpected result is produced. Furthermore, see Hall, Fig.23 as shown above, which teaches duplicated layer of bottom dielectric structure 50 and substrate 10) and contacting a bottom of the source/drain contact (261) and in contact a sidewall of the bottom dielectric structure (270) between the lowest first channel (2080) and the lowest second channel (2080) (see Lin, Fig.16 as shown above and ¶ [0012]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Cheng, Lin, and Hall to enable forming a bottom dielectric structure coupled to a sidewall of a lowest first inner spacer and a lowest second inner spacer and forming a backside conductive via in the substrate and contacting a bottom of the source/drain contact and in contact a sidewall of the bottom dielectric structure between the lowest first channel and the lowest second channel as taught by Lin in order to improve contact resistance and has larger interface with the metal silicide layer.
Regarding Claim 19: Cheng as modified teaches a method as set forth in claim 18 as above. The combination of Cheng, Lin, and Hall further teaches wherein the source/drain contact has a T- shape (see Cheng, Fig.17C as shown above).
Regarding Claim 21: Cheng as modified teaches a method as set forth in claim 18 as above. The combination of Cheng, Lin, and Hall further teaches wherein the first source/drain region and the first silicide layer are in contact with the top surface of the bottom dielectric structure (see Lin, Fig.16 as shown above and/or see Hall Fig.23 as shown above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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