DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/29/2025 has been entered.
Response to Amendments
Entry of Amendments
Claim(s) 1, 8-12, 14 and 20 have been amended.
For further details see the rejections/objections for Claim(s) 1-20 herein.
Claim Objections
Claim(s) 1 and 10 are objected to because of the following informalities:
Claim(s) 1 and 10 recite a term “DFT scanning” in last line. Examiner suggests amending the term to recite “the DFT scanning” to restore antecedent clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Baroughi et al. (US 20180090059; hereinafter Baroughi).
Regarding claim 1, Baroughi teaches in figure(s) 1-18 a light-emitting diode (LED) package comprising:
at least one LED chip (82/18; figs. 1,5);
an active electrical element (12, 18; figs. 1,5) electrically connected to the at least one LED chip (82/18), the active electrical element configured to implement design for test (DFT) scanning (para. 51 :- scanning techniques (e.g., DFT) may be used in conjunction with the scanning test mode; fig. 11) of scanned system circuitry (229,239,249; figs. 11-14) of the active electrical element; and
a data input port (inputs of figs. 11-14) configured to receive commands (Scanen, scanmode) and data (data) for controlling operation of the at least one LED chip (18), the data input port configured to receive a scan initiation command (init; fig. 14, step 502 for setting a scan testing mode in fig. 18) to initiate DFT scanning within the active electrical element (12; clm. 16 - An electronic device comprising: a processor; and an array of microdrivers configured to: set a testing mode of a microdriver of the array of microdrivers using the plurality of pins of the microdriver, wherein the microdriver is configured to light one or more connected micro light emitting diode pixels coupled to the microdriver during the testing mode).
Baroughi teaches above claim limitations in different embodiments. However, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine different featured embodiments of Baroughi since such an implementation can increase the effectiveness of the testing of LED with suitable and combinable feature mix as suggested by “In an effort to provide a concise description of these embodiments …It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure” (para. 26 of Baroughi).
Regarding claim 10, Baroughi teaches in figure(s) 1-18 a method of testing for a light-emitting diode (LED) device, the method comprising:
receiving commands and data at a data input port (inputs of figs. 11-14), the commands (Scanen, scanmode) and data (data) configured for controlling operation of at least one LED chip (82/18; figs. 1,5);
receiving a scan initiation command (init; fig. 14, step 502 for setting a scan testing mode in fig. 18) for initiation of design for test (DFT) scanning (para. 51 :- scanning techniques (e.g., DFT) may be used in conjunction with the scanning test mode; fig. 11) at the data input port; and
generating a test mode select (TMS) signal (set test mode; fig. 18) based on the scan initiation command (init; fig. 14, step 502 for setting a scan testing mode in fig. 18) for initiating DFT scanning (para. 51 :- scanning techniques (e.g., DFT) may be used in conjunction with the scanning test mode; fig. 11) of scanned system circuitry (229,239,249; figs. 11-14) of an active electrical element (12, 18; figs. 1,5); and
halting operation of the at least one LED chip according to the commands and data during DFT scanning (choosing/setting between scan testing mode or operation mode step 502 in fig. 18 implies halting operation mode when scan testing mode is selected).
Baroughi teaches above claim limitations in different embodiments. However, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine different featured embodiments of Baroughi since such an implementation can increase the effectiveness of the testing of LED with suitable and combinable feature mix as suggested by “In an effort to provide a concise description of these embodiments …It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure” (para. 26 of Baroughi).
Regarding claim 14, Baroughi teaches in figure(s) 1-18 An active electrical element (12, 18; figs. 1,5) for controlling operation of at least one a light-emitting diode (LED) chip (82/80/60/18), the active electrical element comprising:
a serial interface (para. 36 - serial-to-parallel circuitry 68 may collect the image data 64 into the particular data signals 70 that are passed on to specific columns among a total of M respective columns in the display panel 60; fig. 5) configured to receive commands (Scanen, scanmode; figs. 11-14) and data (data) for controlling operation of the at least one LED chip (82/80/60/18) and a scan initiation command (init; fig. 14, step 502 for setting a scan testing mode in fig. 18) to initiate design for test (DFT) scanning (para. 51 :- scanning techniques (e.g., DFT) may be used in conjunction with the scanning test mode; fig. 11);
scanner circuitry (66, 72; fig. 5) coupled to the serial interface (68); and
scanned system circuitry (229,239,249; figs. 11-14) coupled to the scanner circuitry, the scanned system circuitry configured to generate a test mode select (TMS) signal (set test mode; fig. 18) based on the scan initiation command (init; fig. 14, step 502 for setting a scan testing mode in fig. 18) and send the TMS signal to the scanner circuitry for initiating the DFT scanning (para. 51 :- scanning techniques (e.g., DFT) may be used in conjunction with the scanning test mode; fig. 11) of scanned system circuitry (229,239,249; figs. 11-14).
Baroughi teaches above claim limitations in different embodiments. However, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine different featured embodiments of Baroughi since such an implementation can increase the effectiveness of the testing of LED with suitable and combinable feature mix as suggested by “In an effort to provide a concise description of these embodiments …It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure” (para. 26 of Baroughi).
Claim(s) 1, 4-8, 10-16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Rearick et al. (US 6715105; hereinafter Rearick) in view of Quick et al. (US 20100102734).
Regarding claim 1, Rearick teaches in figure(s) 1-5 a package comprising:
at least one chip (clm. 1 – digital circuit; chip specific application logic 74a-74d/chip 10, 172a-172d; figs. 1,3);
an active electrical element (TAP 20, BIST 60-66, BIST controller 6, TAP controller 120 of 10 or 130) electrically connected to the at least one chip (circuit under test), the active electrical element configured to implement design for test (DFT) scanning (col. 4 lines 54-55, col. 5 ln. 37-38, 51-59 :- an integrated circuit includes a test access port (TAP) and DFT scan circuitry; figs. 2-3) of scanned system circuitry of the active electrical element (TAP 20, BIST 60-66, BIST controller 6, TAP controller 120 of 10 or 130); and
a data input port (TDI, SDI; col. 1 ln. 31-44) configured to receive commands (instruction 144; col. 8 ln. 50-65 :- a non-data command (e.g., a configuration or execution command) or a data manipulation command. Non-data commands include instructions that tell the TAP controller 130 how to set up the scan and/or data paths between the SDI port 122 and SDO port 128, or which instruct the controller 130 how to step 510h the CUT one or more clock cycles of execution. Data commands require the shifting in 510g of data into the scan path or register configured between the SDI port 122 and SDO port 128.) and data for controlling operation of the at least one chip, the data input port (col. 5 ln. 5-15) configured to receive a scan initiation command (col. 8 lines 20-25 - an instruction register scan, a LFSR register scan, a data scanpath register scan, a shift counter register scan, or a step counter register scan can be issued to transition the TAP through the appropriate states; figs. 4-5) to initiate DFT scanning within the active electrical element (clms. 1,11; figs. 2-3).
Rearick does not teach explicitly light-emitting diode (LED) package, LED chip.
However, Quick teaches in figure(s) 2-11 light-emitting diode (LED) package, LED chip (30/1; para. 5 - several LEDs of different colour mounted in the same physical package; fig. 2).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having light-emitting diode (LED) package, LED chip as taught by Quick in order to provide applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as evidenced by "method and apparatus for controlling a plurality of Light Emitting Diodes (LEDs) … LED driver receives a signal according to the protocol, and separates the first Command packet from the signal and controls an LED associated with the LED driver in accordance with instructions in the first Command packet… may be used in any number of electronic devices that have LEDs as part of their circuitry. This includes entertainment devices such as televisions, digital set-top boxes" (abstract, para. 105 of Quick).
Regarding claim 4, Rearick in view of Quick teaches the LED package of claim 1, wherein: the at least one LED chip comprises three LED chips (para. 5 - Multiple colours may be achieved by making use of several LEDs of different colour--these can even be mounted in the same physical package; fig. 5 of Quick); and the active electrical element comprises no more than eight total ports that include the data input port, a data output port, a ground port, a supply voltage port, and no more than four ports coupled to the three LED chips (as seen in figs. 1,3 of Rearick).
Regarding claim 5, Rearick in view of Quick teaches the LED package of claim 4,
Quick additionally teaches in figure(s) 2-11 wherein the active electrical element comprises no more than three ports coupled to the three LED chips (as seen in fig. 5).
Regarding claim 6, Rearick in view of Quick teaches the LED package of claim 1,
Quick additionally teaches in figure(s) 2-11 wherein the active electrical element comprises a serial interface coupled to the data input port (para. 64 - transmit the Command portion as a stream of asynchronous serial data bits and to transmit a "Break" symbol as the START code) configured to receive the commands and data for controlling operation of the at least one LED chip and the scan initiation command (para. 65 - Command contains control information for the first LED driver 20 to control the various elements of the LED 30 to which it is connected).
Regarding claim 7, Rearick teaches in figure(s) 1-5 the LED package of claim 6, further comprising scanner circuitry (130 fig. 3, circuit of fig. 2) coupled to the serial interface, the scanner circuitry configured to pass the commands and data for controlling operation of the at least one LED chip and the scan initiation command to other circuitry of the active electrical element (scanpath*).
Regarding claim 8, Rearick teaches in figure(s) 1-5 the LED package of claim 7, wherein the other circuitry forms scanned system circuitry of the active electrical element, and upon receipt of the scan initiation command, the scanned system circuitry generates a test mode select (TMS) signal that is sent to the scanner circuitry for initiating DFT scanning (TMS and DFT start in figs. 1,4,5; col. 2 lines 8-40, col. 8 lines 1-50).
Regarding claim 10, Rearick teaches in figure(s) 1-5 a method of testing for a device, the method comprising:
receiving commands and data at a data input port (TDI, SDI; col. 1 ln. 31-44; figs. 1,3), the commands and data configured for controlling operation of at least one chip (clm. 1 – digital circuit; chip specific application logic 74a-74d/chip 10, 172a-172d; figs. 1,3);
receiving a scan initiation command (col. 8 lines 20-25 - an instruction register scan, a LFSR register scan, a data scanpath register scan, a shift counter register scan, or a step counter register scan can be issued to transition the TAP through the appropriate states; figs. 4-5) for initiation of design for test (DFT) scanning (col. 4 lines 54-55, col. 5 ln. 37-38, 51-59 :- an integrated circuit includes a test access port (TAP) and DFT scan circuitry; figs. 2-3) at the data input port; and
generating a test mode select (TMS) signal (TMS; fig. 1) based on the scan initiation command (RUN_TEST command; fig. 4) for initiating DFT scanning of of scanned system circuitry of an active electrical element (TAP 20, BIST 60-66, BIST controller 6, TAP controller 120 of 10 or 130); and
halting operation of the at least one chip (col. 3 lines 20-30 :- BIST form is known as non-concurrent online testing that occurs when the system is in an idle state, such as execution of diagnostic routines. Yet another form of BIST is known as offline testing. Off-line BIST, which is the context of the invention, occurs when the system is placed in a special test mode) according to the commands and data during DFT scanning.
Rearick does not teach explicitly light-emitting diode (LED) device, LED chip.
However, Quick teaches in figure(s) 2-11 light-emitting diode (LED) device, LED chip (30/1; para. 5 - several LEDs of different colour mounted in the same physical package; fig. 2)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having light-emitting diode (LED) device, LED chip as taught by Quick in order to provide applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as evidenced by "method and apparatus for controlling a plurality of Light Emitting Diodes (LEDs) … LED driver receives a signal according to the protocol, and separates the first Command packet from the signal and controls an LED associated with the LED driver in accordance with instructions in the first Command packet… may be used in any number of electronic devices that have LEDs as part of their circuitry. This includes entertainment devices such as televisions, digital set-top boxes" (abstract, para. 105 of Quick).
Regarding claim 11, Rearick teaches in figure(s) 1-5 the method of claim 10, wherein the data input port is a terminal of an active electrical element of the LED device ((TDI, SDI in fig. 1).
Regarding claim 12, Rearick teaches in figure(s) 1-5 the method of claim 11, wherein generating the TMS signal (TMS; fig. 1) comprises receiving the scan initiation command (RUN_TEST; fig. 4) at scanned system circuitry of the active electrical element.
Regarding claim 13, Rearick teaches in figure(s) 1-5 the method of claim 12, further comprising sending the TMS signal to scanner circuitry of the active electrical element and implementing DFT scanning of the scanned system circuitry (col. 5 lines 35-59).
Regarding claim 14, Rearick teaches in figure(s) 1-5 An active electrical element for controlling operation of at least one chip, the active electrical element comprising:
a serial interface (TDI, SDI in figs. 1-3; col. 1 lines 30-35 - DFT technique is called scan testing…Input data is loaded serially ("shifted") into each of the scan registers via a Test Access Port (TAP)) configured to receive commands and data for controlling operation of the at least one chip and a scan initiation command to initiate design for test (DFT) scanning (instruction 144; col. 8 ln. 50-65 :- a non-data command (e.g., a configuration or execution command) or a data manipulation command. Non-data commands include instructions that tell the TAP controller 130 how to set up the scan and/or data paths between the SDI port 122 and SDO port 128, or which instruct the controller 130 how to step 510h the CUT one or more clock cycles of execution. Data commands require the shifting in 510g of data into the scan path or register configured between the SDI port 122 and SDO port 128.);
scanner circuitry (130 fig. 3, circuit of fig. 2) coupled to the serial interface; and
scanned system circuitry (tester 5; fig. 1) coupled to the scanner circuitry, the scanned system circuitry configured to generate a test mode select (TMS) signal (TMS; fig. 1) based on the scan initiation command and send the TMS signal to the scanner circuitry for initiating the DFT scanning (RUN_TEST command; fig. 4) of the scanned system circuitry.
Rearick does not teach explicitly LED chip.
However, Quick teaches in figure(s) 2-11 LED chip (30/1; para. 5 - several LEDs of different colour mounted in the same physical package; fig. 2)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having LED chip as taught by Quick in order to provide applying a known technique to a known device (method, or product) ready for improvement to yield predictable results as evidenced by "method and apparatus for controlling a plurality of Light Emitting Diodes (LEDs) … LED driver receives a signal according to the protocol, and separates the first Command packet from the signal and controls an LED associated with the LED driver in accordance with instructions in the first Command packet… may be used in any number of electronic devices that have LEDs as part of their circuitry. This includes entertainment devices such as televisions, digital set-top boxes" (abstract, para. 105 of Quick).
Regarding claim 15, Rearick teaches in figure(s) 1-5 the active electrical element of claim 14, wherein the scanner circuitry is configured to pass the commands and data for controlling operation of the at least one LED chip and the scan initiation command to the scanned system circuitry before the TMS signal is generated (col. 8 lines 15-20 - When test access is required, the TAP exits the Test-Logic-Reset state by applying a logical 0 at the test mode select (TMS) port. This puts the TAP into the Run-Test/Idle state).
Regarding claim 16, Rearick teaches in figure(s) 1-5 the active electrical element of claim 14, further comprising a data input port that is configured to receive both the scan initiation command and the commands and data for controlling operation of the at least one LED chip (col. 8 lines 53-67 :- Non-data commands include instructions that tell the TAP controller 130 how to set up the scan and/or data paths between the SDI port 122 and SDO port 128…Data commands require the shifting in 510g of data into the scan path or register configured between the SDI port 122 and SDO port 128).
Regarding claim 19, Rearick teaches in figure(s) 1-5 the active electrical element of claim 16, further comprising a data output port, a ground port, a supply voltage port, and ports for coupling to one or more LED chips (col. 5 line 50- col. 6 line 15; fig. 2).
Claim(s) 2-3, 9, 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Rearick in view of Quick, and further in view of Hildebrant et al. (US 20050193294).
Regarding claim 2, Rearick in view of Quick teaches the LED package of claim 1,
Rearick does not teach explicitly wherein the data input port is a first bidirectional communication port.
However, Hildebrant teaches in figure(s) 1-6 wherein the data input port is a first bidirectional communication port (270; fig. 5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having wherein the data input port is a first bidirectional communication port as taught by Hildebrant in order to provide "receives test data over a wireless connection" (para. 38).
Regarding claim 3, Rearick as modified by Quick and Hildebrant teaches the LED package of claim 2,
Hildebrant additionally teaches in figure(s) 1-6 wherein the active electrical element is configured to detect an input signal at the first bidirectional communication port, assign the first bidirectional communication port as the data input port, and assign a second bidirectional communication port as a data output port (para. 38 - wireless IP core 216 that receives test data over a wireless connection 270. The wireless IP core 216 performs all the functions of the data link layer, network layer, etc., and passes data frames to a test data parser 214; para. 43 - A results data packager 305 receives the test results from the TDO output register 304 in parallel, and formats them into frames to pass on to the wireless interface 216 for transmission to the test station 250).
Regarding claim 9, Rearick in view of Quick teaches the LED package of claim 1,
Rearick does not teach explicitly wherein the active electrical element comprises an application-specific integrated circuit (ASIC).
However, Hildebrant teaches in figure(s) 1-6 wherein the active electrical element comprises an application-specific integrated circuit (ASIC) (para. 48 - wireless enabled ASICs).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having wherein the active electrical element comprises an application-specific integrated circuit (ASIC) as taught by Hildebrant in order to provide "In combination with DFT and CCT techniques, the present invention can assist in bringing down the costs of integrated circuit testing" (para. 48).
Regarding claim 17, Rearick in view of Quick teaches the active electrical element of claim 16,
Rearick does not teach explicitly wherein the data input port is a first bidirectional communication port.
However, Hildebrant teaches in figure(s) 1-6 wherein the data input port is a first bidirectional communication port (270; fig. 5).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having wherein the data input port is a first bidirectional communication port as taught by Hildebrant in order to provide "receives test data over a wireless connection" (para. 38).
Regarding claim 18, Rearick as modified by Quick and Hildebrant teaches the active electrical element of claim 17,
Hildebrant additionally teaches in figure(s) 1-6 wherein the active electrical element is configured to detect an input signal at the first bidirectional communication port, assign the first bidirectional communication port as the data input port, and assign a second bidirectional communication port as a data output port (para. 38 - wireless IP core 216 that receives test data over a wireless connection 270. The wireless IP core 216 performs all the functions of the data link layer, network layer, etc., and passes data frames to a test data parser 214; para. 43 - A results data packager 305 receives the test results from the TDO output register 304 in parallel, and formats them into frames to pass on to the wireless interface 216 for transmission to the test station 250).
Regarding claim 20, Rearick in view of Quick teaches the active electrical element of claim 14,
Rearick does not teach explicitly wherein the serial interface, the scanner circuitry, and the scanned system circuitry are part of an ASIC.
However, Hildebrant teaches in figure(s) 1-6 wherein the serial interface, the scanner circuitry (para. 5 - JTAG protocol, data is loaded into the scan chains via a Test Data In (TDI) serial input pin, and data is output from the scan chains via a Test Data Out (TDO) serial output pin), and the scanned system circuitry (para. 5 - Scan testing, a scan storage cell is implemented for each input and output of interest of the block under test. The scan storage cells are connected together in a serial chain, which is connected at an input to the integrated circuit's scan-in port and connected at an output to the integrated circuits scan-out port) are part of an ASIC (para. 48 - wireless enabled ASICs.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Rearick by having wherein the serial interface, the scanner circuitry, and the scanned system circuitry are part of an application-specific integrated circuit (ASIC) as taught by Hildebrant in order to provide "In combination with DFT and CCT techniques, the present invention can assist in bringing down the costs of integrated circuit testing" (para. 48).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/Primary Examiner, Art Unit 2858