DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species II in the reply filed on 2/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 16 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/10/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 11, 15, 21, 23, and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YOSHIDA et al. (US PG Pub 2019/0122955, hereinafter Yoshida).
Regarding claim 1, figure 17 of Yoshida discloses a semiconductor device package, comprising:
a semiconductor die (11), comprising:
a wide bandgap semiconductor material (11a, ¶ 41); and
a metallization layer (11c) on a surface of the semiconductor die;
a submount (13); and
wherein the metallization layer (11c) of the semiconductor die is directly bonded to the submount (13) via an ultrasonic bond (¶ 39).
Regarding claim 2, figure 17 of Yoshida discloses the metallization layer (11c) and the submount (13) each comprise a malleable metal (¶ 42, 46) at an interface between the metallization layer and the submount.
Regarding claim 3, figure 17 of Yoshida discloses the metallization layer (11c) and the submount (13) comprise aluminum (¶ 42) at the interface between the metallization layer and the submount.
Regarding claim 8, figure 17 of Yoshida discloses the semiconductor device package does not include any die-attach material at an interface between the metallization layer (11c) and the submount (13).
Regarding claim 11, figure 17 of Yoshida discloses the submount (13) comprises a first metal layer (7), a second metal layer (5) , and an insulating material (6) between the first metal layer and the second metal layer.
Regarding claim 15, figure 17 of Yoshida discloses the metallization layer (11c) is on a substrate of the semiconductor die (11).
Regarding claim 21, figure 17 of Yoshida discloses the semiconductor die (11) comprises silicon carbide (¶ 41).
Regarding claim 23, figure 17 of Yoshida discloses the semiconductor die (11) comprises a silicon carbide-based MOSFET (¶ 81), a silicon carbide-based Schottky diode, or a Group III nitride-based high electron mobility transistor.
Regarding claim 40, figure 17 of Yoshida discloses a method of providing a semiconductor device package, the method comprising:
providing a metallization layer (11c) on a surface of a semiconductor die (11), the semiconductor die comprising a wide bandgap semiconductor (11a, ¶ 41); and
directly bonding the metallization layer to a submount using a direct bonding process including ultrasonic bonding (¶ 39).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida.
Regarding claim 7, Yoshida does not explicitly disclose the surface of the submount comprises a surface roughness measured as arithmetic average roughness Ra in a range of about 0.1 µm to about 100 µm.
However, it would have been obvious to form the device of Yoshida to have a surface roughness of the submount within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Masayuki et al. (US PG Pub 2002/0050585, hereinafter Masayuki.
Regarding claim 12, figure 17 of Yoshida discloses the submount (13) is mounted to a cooler (12, ¶ 37).
Yoshida does not explicitly disclose a lead frame.
In the same field of endeavor, Masayuki discloses coolers and lead frames can equivalently be used for heat dissipation (¶ 40).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to mounting the submount to a leadframe as taught by Masayuki for the purpose of substituting art recognized equivalents known to be used for the same purpose. see MPEP 2144.06.
Regarding claim 13, figure 17 of Yoshida discloses the metallization layer (11c) is associated with a contact for one or more semiconductor devices on the semiconductor die (11).
Claims 1, 10, 18, 19, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US PG Pub 2020/0357729, hereinafter Kim) in view of Yoshida and KAKIZAKI et al. (US PG Pub 2025/0210475, hereinafter Kakizaki).
Regarding claim 1, figure 1 of Kim discloses a semiconductor device package, comprising:
a semiconductor die (101); and
a metallization layer (128) on a surface of the semiconductor die;
a submount (104); and
wherein the metallization layer (128) of the semiconductor die is directly bonded to the submount (104).
Kim does not explicitly disclose the semiconductor die comprising a wide bandgap semiconductor material.
In the same field of endeavor, Yoshida discloses a semiconductor die (11), comprising:
a wide bandgap semiconductor material (11a, ¶ 41).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form the side to comprise a wide bandgap semiconductor material as taught by Yoshida for the purpose of increasing electric field strength against dielectric breakdown (¶ 41).
Kim discloses a solder bond (¶ 31) and does not explicitly disclose an ultrasonic bond.
In the same field of endeavor, Kakizaki discloses ultrasonic bonds and solder bonds are both suitable for bonding (¶ 131).
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an ultrasonic bond as taught by Kakizaki for the purpose of substituting art recognized equivalents known to be used for the same purpose. see MPEP 2144.06.
Regarding claim 10, figure 1 of Kim discloses the submount (104) is a lead frame or a clip structure (¶ 25).
Regarding claim 18, figure 1 of Kim discloses one or more wire bonds (127) to the semiconductor die (101).
Regarding claim 19, figure 1 of Kim discloses an encapsulating material (120) on the semiconductor die (101).
Regarding claim 24, figure 1 of Kim in view of Yoshida and Kakizaki discloses a semiconductor device package, comprising:
a semiconductor die (101), comprising:
a wide bandgap semiconductor material (Yoshida, ¶ 41); and
a metallization layer (128) on a surface of the semiconductor die; and
an aluminum lead frame (104, ¶ 26) directly bonded to the metallization layer.
The prior art does not explicitly disclose an aluminum metallization layer.
However, aluminum is well known in the art for metallization layers and it would have been obvious to use aluminum for the purpose of selecting a low resistance material.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Yoshida, as applied to claim 1, further in view of Kim et al. (US PG Pub 2012/0319259, hereinafter Kim 2).
Regarding claim 9, figure 1 of Kim discloses the submount (104) comprises aluminum (¶ 26).
Kim does not explicitly disclose a surface of the submount opposite the semiconductor die (101) is an anodized surface.
In the same field of endeavor, figure 2 of Kim 2 discloses a surface of a submount (111/121) opposite a semiconductor die (114) is an anodized surface (112/122).
In light of such teachings, it would have been obvious to one of ordinary skill in the art at the time the invention was made to form an anodized surface on a surface of the submount opposite the semiconductor die as taught by Kim 2 for the purpose of improving the heat radiation property (¶ 50).
Response to Arguments
Applicant's arguments filed 6/22/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 40, applicants argue that Yoshida doe not teach ultrasonic bonding.
However, paragraph 39 of Yoshida discloses the element 11 can be bonded to the conductive plate 5 using ultrasonic bonding without the die-bonding material 22.
Applicant’s arguments with respect to claim 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For at least the aforementioned reasons, the rejection is deemed proper and made final.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817
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