DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 1/31/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 30 and 32-34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (US PG Pub 2023/0031542, hereinafter Jung).
Regarding claim 30, figures 7-37 of Jung disclose a method for forming a semiconductor structure, comprising:
forming a first fin structure (F1) and a second fin structure (F3) over a substrate (100) along a first direction, wherein the first fin structure comprises first semiconductor material layers (11) and second semiconductor material layers (12) alternately stacked, and the second fin structure comprises first semiconductor material layers (11) and second semiconductor material layers (12) alternately stacked;
forming a dummy gate structure (DG) along a second direction over the first fin structure and the second fin structure;
removing a portion of the dummy gate structure to form a trench (T), wherein the trench has a top portion and a bottom portion, and a width (measured across the full diameter) of the bottom portion is greater than a width (measured across a narrower section that is not the full diameter) of the top portion, and the trench is along the first direction and the second direction;
filling a dielectric material (20) into the trench to form a dielectric wall structure; and
removing a portion of the first semiconductor material layers (11) to form a plurality of first nanostructures (NW).
Regarding claim 32, figure 37 of Jung discloses replacing the dummy gate structure with a gate structure (G2), wherein the first nanostructures (NW) are wrapped by the gate structure.
Regarding claim 33, figures 7-37 of Jung disclose wherein the first nanostructures (NW) comprise a first portion and a second portion, the first portion has a first width along the second direction, the second portion has a second width along the second direction, and the first width is greater than the second width.
Note: Arbitrary portions of the nanostructure can be interpreted to read on the claimed first and second portions such that the claimed relative widths are met.
Regarding claim 34, figures 7-37 of Jung disclose the dielectric wall structure (20) has a first portion and a second portion, the first portion of the dielectric wall structure has a third width along the second direction, the second portion of the dielectric wall structure has a fourth width along the second direction, and the third width is smaller than the fourth width.
Note: Arbitrary portions of the dielectric wall structure can be interpreted to read on the claimed first and second portions such that the claimed relative widths are met.
` Allowable Subject Matter
Claims 15-29 are allowed.
Regarding claim 15, the closest prior art of record, Jung et al. (US PG Pub 2023/0031542), either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a first fin structure and a second fin structure over a first region and a second region of a substrate, respectively, wherein the first fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked, and the second fin structure comprises first semiconductor material layers and second semiconductor material layers alternately stacked;
forming a dummy gate structure over the first fin structure and the second fin structure;
removing a top portion of the dummy gate structure to form an opening;
forming a protection layer in the opening; removing a bottom portion of the dummy gate structure to deepen a depth of the opening to form a recess;
removing a sidewall portion of the dummy gate structure to enlarge a width of the recess to form a trench; and
filling a dielectric material into the trench to form a dielectric wall structure between the first fin structure and the second fin structure, wherein the dielectric wall structure is formed in a remaining dummy gate structure”.
Regarding claim 25, the closest prior art of record, Jung et al. (US PG Pub 2023/0031542), either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a first fin structure and a second fin structure over a substrate;
forming a dummy gate structure over the first fin structure and the second fin structure, wherein the dummy gate structure comprises a dummy gate dielectric layer;
removing a top portion of the dummy gate structure to form an opening;
forming a protection layer in the opening;
removing a bottom portion of the dummy gate structure to deepen a depth of the opening to form a recess, wherein the dummy gate dielectric layer is exposed by the recess;
removing a sidewall portion of the dummy gate structure to enlarge a width of the recess to form a trench;
filling a dielectric material into the trench to form a dielectric wall structure; and
replacing the dummy gate structure with a gate structure, wherein the gate structure includes a first gate structure and a second gate structure, and the first gate structure is isolated from the second gate structure by the dielectric wall structure.”
Claim 31 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
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/YU-HSI D SUN/Primary Examiner, Art Unit 2817
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