DETAILED ACTION
This action is responsive to the amendments filed October 3, 2025. Prior to entry, claims 1-20 were pending. Claims 1-4, 8, 10, 15 and 18 are amended. Claims 6-7, 12, and 20 have been cancelled. Claims 21-24 are new. Upon entry, claims 1-5, 8-11, 13-19, and 21-24 are now pending. Claims 1, 10, and 18 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statements (IDS) filed on August 21, 2025. This IDS has been considered.
Claim Rejections - 35 USC § 112 – Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 22, the phrase “configured to generate a modified first clock signal” is unclear in it’s scope as the nature of the modification is not defined. Applicant’s specification does not indicate which electrical characteristics of the signal are different from the original nor the kind of alteration.
For purposes of compact prosecution, the term “modified” will be interpreted to mean “exhibits propagation delay” (see MPEP 2173.06).
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 10-11, 13-17, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sathe et al. (US 20140062565 – of Record; “Sathe”)
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Regarding independent claim 10, Sathe discloses a local clock driver in a memory circuit, the local clock driver comprising (Fig. 5: 511 clock driver):
a NAND gate (Fig. 5: 503 NAND gate);
a NOR gate (Fig. 5: 505 NOR gate);
a first transistor electrically connected to the NAND gate (Fig. 5: 509);
and a second transistor electrically connected to the NOR gate (Fig. 5: 507),
wherein the NAND gate and the NOR gate are configured to receive a first clock signal (Fig. 5 where it illustrates clk_dx (first clock signal) going to both NAND and NOR gates),
and the NAND gate is further configured to receive a second clock signal that is faster than the first clock signal (Fig. 5 where it illustrates clk (second clock signal) going to the NAND gate. It is noted that since clk_dx is derivative of clk and goes through a delay chain, clk is necessarily faster than clk_dx),
and the receipt of the second clock signal by the NAND gate reduces a delay in the rising edge of the first clock signal (Fig. 5. It is noted that the structure of Sathe's clock buffer is substantially similar to that of the local clock driver of instant application as appears in figure 4A in all electrically relevant means. Therefore, Sathe's buffer would be isomorphic to the instant application in their electrical properties including the rising edge transitions).
Regarding claim 11, Sathe discloses the limitations of claim 10.
As applied, Sathe further discloses the receipt of the second clock signal by the NAND gate causes the first transistor to turn on earlier than if the first transistor was instead configured to only receive the first clock signal (Fig. 5. It is noted that the first transistor being a P-FET in the instant application would be "turned on" when a ground (low) voltage is applied to it's gate. Since the output of the NAND gate, which drives the gate of the P-FET, is low any time either of it's inputs is low, the delay chain 501 between the two clock inputs will necessarily cause the first transistor to "turn on" prior to the rising edge of the first clock (clk_dx). Further, if only the delayed first clock were supplied to both inputs of the NAND gate, it would function effectively as an inverter with timing relative to the first clock which due to the delay chain 501 would delay its switching time.).
Regarding claim 13, Sathe discloses the limitations of claim 10.
As applied, Sathe further discloses wherein the NOR gate is further configured to receive the second clock signal (Fig. 5 where it illustrates the NOR gate 505 receiving the second clock signal clk).
Regarding claim 14, Sathe discloses the limitations of claim 13.
As applied, Sathe further discloses wherein the receipt of the second clock signal causes the second transistor to turn on earlier than if the second transistor was instead configured to only receive the first clock signal (Fig. 5. It is noted that the second transistor being an N-FET in the instant application would be "turned on" when a Vdd (high) voltage is applied to it's gate. Since the output of the NOR gate, which drives the gate of the N-FET, is high any time both of it's inputs are low. Since the structure of Sathe's clock driver is substantially similar to that of the local clock driver of instant application as appears in figure 4A the timing of its output would be understood by one of ordinary skill in the art to also be substantially similar. Further, if only the delayed first clock were supplied to both inputs of the NOR gate, it would function effectively as an inverter with timing relative to the first clock which due to the delay chain 501 would delay its switching time).
Regarding claim 15, Sathe discloses the limitations of claim 14.
As applied, Sathe further discloses wherein the receipt of the second clock signal by the NOR gate reduces a delay in the falling edge of the first clock signal (Fig. 5. It is noted that the structure of Sathe's clock buffer is substantially similar to that of the local clock driver of instant application as appears in figure 4A in all electrically relevant means. Therefore, Sathe's buffer would be isomorphic to the instant application in their electrical properties including the falling edge transitions).
Regarding claim 16, Sathe discloses the limitations of claim 10.
As applied, Sathe further discloses further comprising an inverter delay circuit (Fig. 5: 501 delay chain),
wherein the NAND gate and the NOR gate are configured to receive the first clock signal through the inverter delay circuit (Fig. 5 where it illustrates clk_dx (first clock signal) going to both NAND and NOR gates from 501 delay chain).
Regarding claim 17, Sathe discloses the limitations of claim 10.
As applied, Sathe further discloses wherein the loading of the second clock signal is smaller than the loading of the first clock signal (Fig. 5. It is noted that the structure of Sathe's clock driver is substantially similar to that of the local clock driver of instant application as appears in figure 4A. Therefore, the relative loading of both clock inputs would be considered substantially similar as well by those with ordinary skill in the art. However, it is noted that as both circuits use an input that appears to be configured to be electrically coupled to additional elements which are not depicted, the specific loading is not determinable).
Regarding claim 23, Sathe discloses the limitations of claim 10.
As applied, Sathe further discloses wherein the first transistor is a PMOS transistor, and the second transistor is a NMOS transistor (Fig. 5).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 2, 4-5, 9 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20190369906 – of Record) in view of Luk et al. (US 5790839 – of Record; “Luk”) as supported by Lau (US 20170126211).
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Regarding independent claim 1, Joo discloses a memory circuit comprising:
a clock generator configured to generate a first clock signal and a second clock signal, wherein the second clock signal is faster than the first clock signal (Fig. 1: 115 clock generator. See also para 41; "The clock generator 115 may generate the initial first clock signal ICLK1", "The clock generator 115 may generate the initial second clock signal ICLK2", "The initial second clock signal ICLK2 may toggle at a faster cycle than the initial first clock signal ICLK1");
and a first memory bank including:
a plurality of memory cells (Fig. 1: 112 second memory. See also para 26; "The first and second memories 111 and 112", "may store codes CODE therein. The codes CODE may include executable programs required for an operation of the semiconductor device 100". It is noted that to store programs, there would necessarily be a plurality of memory cells);
and a first local clock driver in electrical communication with the plurality of memory cells of the first memory bank (Fig. 1: 114 where it illustrates the device driving a local clock CLK1 to the memory);
the first local clock driver configured to receive both the first clock signal and the second clock signal (Fig. 1: 114 where it illustrates the device receiving both ICLK1 and ICLK2).
Joo is silent with respect to a specific clock buffer and a third clock signal.
However, Luk teaches and a clock buffer configured to receive the first clock signal and to generate a third clock signal (Fig. 4A where it illustrates a third clock signal generated from clock buffer 42A with receives the first clock signal) that is faster than the first clock signal (It is noted that the term “faster” appears to be defined in applicant’s Specification as “reduced slew” or "increased sharpness of the rising edge" (para. 24) . It is well understood in the art that one of the fundamental design purposes of any local clock buffer is to isolate loading and therefore improve transition times (i.e.: reduce slew or make it faster) as supported by Lau para. 17; “para. 17; "The output clock of the oscillator input buffer 114 is supplied to a buffer 116 (e.g., a CMOS buffer) that sharpens the edges of the output clock of the oscillator input buffer 114, i.e., reduces the rise time and fall time of the output clock")
Joo and Luk are from the same field of endeavor as applicant’s invention directed to clocking circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joo’s clocking structure with the teachings of Luk’s secondary clock buffers. Doing so would improve the clock skew of the circuit and increase its memory capacity.
Regarding claim 2, Joo and Luk as supported by Lau disclose the limitations of claim 1.
As applied, Joo further discloses further comprising:
a second memory bank including (Fig. 1: 111 first memory):
a plurality of memory cells (Fig. 1: 112 second memory. See also para 26; "The first and second memories 111 and 112", "may store codes CODE therein. The codes CODE may include executable programs required for an operation of the semiconductor device 100". It is noted that to store programs, there would necessarily be a plurality of memory cells);
and a second local clock driver in electrical communication with the plurality of memory cells of the second memory bank, the second local clock driver configured to receive the first clock signal (Fig. 1: where it illustrates component 113 receiving ICLK1 and driving a local clock signal CLK1).
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Regarding claim 4, Joo and Luk as supported by Lau disclose the limitations of claim 1.
Joo is silent with respect to a third and fourth memory bank.
However, Luk teaches further comprising:
a third memory bank including (Fig. 4A where it illustrates a top row of memory banks):
a plurality of memory cells (Fig. 4A: 42A clock buffer. It is noted that the clock buffer 42A is depicted supplying the local clock for 4 banks in this embodiment any of which could be considered the third bank);
and a third local clock driver in electrical communication with the plurality of memory cells of the third memory bank, the third local clock driver configured to receive the first clock signal (Fig. 4A: 42A clock buffer. It is noted that the clock buffer 42A is depicted supplying the local clock for 4 banks in this embodiment any of which could be considered the third bank);
and a fourth memory bank including (Fig. 4A where it illustrates a bottom row of memory banks):
a plurality of memory cells (Fig. 4A: 42B clock buffer. It is noted that the clock buffer 42B is depicted supplying the local clock for 4 banks in this embodiment any of which could be considered the fourth bank);
and a fourth local clock driver in electrical communication with the plurality of memory cells of the fourth bank, the fourth local clock driver configured to receive the first clock signal (Fig. 4A: 42B clock buffer. It is noted that the clock buffer 42B is depicted supplying the local clock for 4 banks in this embodiment any of which could be considered the fourth bank).
Regarding claim 5, Joo and Luk as supported by Lau disclose the limitations of claim 4.
As applied, Luk further discloses wherein the third memory bank and the fourth memory bank are not configured to receive the second clock signal (Fig. 4A where it illustrates only the first clock signal going to the third and fourth local clock drivers).
Regarding claim 9, Joo and Luk as supported by Lau disclose the limitations of claim 1.
As applied, Joo further discloses wherein the first clock signal and the second clock signal are simultaneously provided to the first local clock driver (Fig. 1 where it illustrates ICLK1 and ICLK2 directly connecting to component 114 with no intervening circuits to delay. It is noted that the term "simultaneously" is not explicitly defined in the instant application. It will be understood to persons having ordinary skill in the art to mean "substantially at the same time").
Regarding claim 22, notwithstanding the indefiniteness rejection above, Joo and Luk as supported by Lau disclose the limitations of claim 4.
As applied, Luk further discloses wherein the clock buffer is further configured to generate a modified first clock signal from the first clock signal (it is well understood in the art that all buffers have the property of propagation delay),
the modified first clock signal is configured to provide to the third and fourth local clock drivers (Fig. 4A where it illustrates a third clock signal generated from clock buffer 42A with receives the first clock signal,
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20190369906 – of Record) in view of Luk et al. (US 5790839 – of Record; “Luk”) as supported by Lau (US 20170126211) and further in view of Eto et al. (US 6150866 – of Record; “Eto”).
Regarding claim 3, Joo and Luk as supported by Lau disclose the limitations of claim 2.
Joo and Luk are silent with respect to the second local clock driver receiving the second clock signal.
However, Eto teaches the second local clock driver is configured to also receive the second clock signal (Fig. 1: 442 local clock driver 2. See also col. 2, ln 45-57; "a plurality of local clock drive circuits", "being supplied with a forward clock propagated by the first clock", "and being also supplied with the second clock").
Joo, Luk and Eto are from the same field of endeavor as applicant’s invention directed to clocking circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joo’s clock driver with Luk’s second level clock driver along with the teachings of Eto’s second clock signal to improve the rising and falling edges of the clock. Doing so would reduce the clock skew of the circuit and improve the overall speed of the memory system.
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Claims 8 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20190369906 – of Record) in view of Luk et al. (US 5790839 – of Record; “Luk”) as supported by Lau (US 20170126211) and further in view of Zhu (US 5849610; “Zhu”)
Regarding claim 8, Joo and Luk as supported by Lau disclose the limitations of claim 4.
Joo and Luk are silent with respect to a third and fourth local clock driver.
However, Zhu teaches the third local clock driver and the fourth local clock driver are both configured to receive the third clock signal (Fig. 7. See Examiner’s Markup above).
Joo, Luk and Zhu are from the same field of endeavor as applicant’s invention directed to clocking circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joo’s clocking structure with Luk’s second level clock driver along with the teachings of Zhu’s local clock buffers to reduce and isolate loading of clock endpoints in the clock tree. Doing so would reduce the clock skew of the circuit and improve the overall speed of the memory system.
Regarding claim 21, Joo and Luk as supported by Lau disclose the limitations of claim 4.
Joo and Luk are silent with respect to a third and fourth local clock driver.
However, Zhu teaches the third local clock driver and the fourth local clock driver are both configured to receive the third clock signal (Fig. 7. See Examiner’s Markup above).
Applicant is advised that should claim 8 be found allowable, claim 21 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claims 18-19 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Joo (US 20190369906 – of Record) in view of Sathe et al. (US 20140062565 – of Record; “Sathe”)
Regarding independent claim 18, Joo discloses a method for providing clock signals to a memory bank of a memory circuit, the method comprising:
generating a first clock signal and a second clock signal (Fig. 1: ICLK1 & ICLK2);
providing the first clock signal and the second clock signal to logic circuitry of a local clock driver within a memory bank (Fig. 1: where it illustrates ICLK1 & ICLK2 going to component 114 which drives a local clock to the memory 112),
Joo is silent with respect to the specific topology of the local driver circuit.
However, Sathe teaches the local clock driver having a NAND gate and a first transistor electrically connected to the NAND gate (Fig. 5),
wherein the second clock signal is configured to turn on the NAND gate and the first transistor faster than the first clock signal (Fig. 5. It is noted that the first transistor being a P-FET in the instant application would be "turned on" when a ground (low) voltage is applied to it's gate. Since the output of the NAND gate, which drives the gate of the P-FET, is low any time either of it's inputs is low, the delay chain 501 between the two clock inputs will necessarily cause the first transistor to "turn on" prior to the rising edge of the first clock (clk_dx)),
and the receipt of the second clock signal by the NAND gate reduces a delay in the rising edge of the first clock signal (Fig. 5. It is noted that the structure of Sathe's clock buffer is substantially similar to that of the local clock driver of instant application as appears in figure 4A in all electrically relevant means. Therefore, Sathe's buffer would be isomorphic to the instant application in their electrical properties including the rising edge transitions).
Joo and Sathe are from the same field of endeavor as applicant’s invention directed to clocking circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Joo’s clock generator with the teachings of Sathe’s local clock driver topology. Doing so would improve the rising and falling edge times of the clock, thereby reducing clock skew and improving memory speed.
Regarding claim 19, Joo and Sathe combined disclose the limitations of claim 18.
As applied, Sathe further discloses wherein the receipt of the second clock signal by the NAND gate causes the first transistor to turn on earlier than if the first transistor was instead configured to only receive the first clock signal (Fig. 5. It is noted that the first transistor being a P-FET in the instant application would be "turned on" when a ground (low) voltage is applied to it's gate. Since the output of the NAND gate, which drives the gate of the P-FET, is low any time either of it's inputs is low, the delay chain 501 between the two clock inputs will necessarily cause the first transistor to "turn on" prior to the rising edge of the first clock (clk_dx). Further, if only the delayed first clock were supplied to both inputs of the NAND gate, it would function effectively as an inverter with timing relative to the first clock which due to the delay chain 501 would delay its switching time).
Regarding claim 24, Joo and Sathe combined disclose the limitations of claim 18.
As applied, Sathe further discloses wherein the local clock driver further includes a NOR gate and a second transistor electrically connected to the NOR gate (Fig. 5),
and the NAND gate and the NOR gate are both configured to receive the second clock signal (Fig. 5).
Response to Arguments
Applicant's arguments filed October 3, 2025, with respect to independent claims 1, 10, and 18,
have been fully considered but because different facts and newly cited portions from the previously applied references in combination with the new references applied, are either unpersuasive or moot because of the new ground of rejection.
Applicant argues on pg. 12 of Remarks that the rejection of claim 1 is improper due to the amendment of the claim to incorporate the features of previously presented claim 7 which was objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Applicant was apprised of this issue during the examiner initiated interview of October 1, 2025, after receipt of the initial reply to non-final rejection filed September 30, 2025, which did not include intervening claim 6. As such, with the same issue in the supplemental response, and without the antecedent features of claim 6 included along with the features of claim 7, the scope of newly amended independent claim 1 is not the same as was previously indicated as potentially allowable. Therefore, the claim is considered only in light of the features and limitations currently presented and rejected on new grounds.
For at least these reasons the rejection of independent claim 1 as stated above is deemed proper.
Applicant argues on pg. 13 of Remarks that the obviousness rejection of independent claims 10 and 18 is improper because the cited references fail to disclose “reduces a delay in the rising edge of the first clock signal” as recited in the amendments. Applicant fails to provide any indication or suggestion of how the amended feature overcomes the prior art. As per CFR § 1.111(b), a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references does not comply with the requirements of a fully responsive reply. However, as per MPEP 714.03 discretion is exercised to accept the amendment as an adequate reply.
As stated in the rejection above, Sathe’s clock driver is substantially similar to the instant application and would therefore be isomorphic to the instant application in their electrical properties including the rising edge transitions.
For at least these reasons, the rejections for independent claims 10 and 18 are deemed proper.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/James S Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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