DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10, 18-20 and new claims 21-27 in the reply filed on 2/10/26 is acknowledged.
Applicant’s cancellation of non-elected claims 11-17 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-7, 9, 10, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambino et al., US Publication No. 2019/0363124 A1 (from the IDS) in view of Lv, CN 107093597 B (see attached English machine translation).
Gambino teaches:
1. A semiconductor device, comprising (see fig. 1):
a first chip (4) including a first wafer and a first dielectric layer (e.g. first dielectric layer surrounding 12) disposed thereon;
a second chip (6) including a second wafer and a second dielectric layer (e.g. second dielectric layer surrounding 14) disposed thereon, the second chip being bonded to the first chip to define a bond line (e.g. interface of 8/16) between the first dielectric layer and the second dielectric layer; and
a first die seal (12) in the first dielectric layer, a second die seal (14) in the second dielectric layer, and a hybrid bond (e.g. HBI at para. [0037]) connecting the first die seal and the second die seal through the bond line (e.g. interface of 8/16). See Gambino at para. [0001] – [0047], figs. 1-8.
Gambino does not expressly teach:
an electrostatic discharge path including a die seal layer on the second wafer, a die seal ground contact for the die seal layer,
In an analogous art, Lv teaches:
(see figs. 2A, 3A) an electrostatic discharge path (203, 202a) including a die seal layer (MTOP) on a wafer (1), a die seal ground contact (VIA TOP) for the die seal layer, a die seal (M1-M6, VIA1-VIA 5) in a dielectric layer (81-87). See Lv at English machine translation pages 6-9.
It would have been obvious to a person of ordinary skill in the art to modify Gambino with Lv to form “an electrostatic discharge path including a die seal layer on the second wafer, a die seal ground contact for the die seal layer, a first die seal in the first dielectric layer, a second die seal in the second dielectric layer, and a hybrid bond connecting the first die seal and the second die seal through the bond line” because “The invention can realize ESD protection function in the sealing ring so as to effectively use the area of the sealing ring to realize the ESD protection structure, it can save area and improve the integration degree.” (e.g. see Lv at Abstract) and “…electrostatic discharge (ESD) protection design is very important in improving the reliability and yield of the product.” (e.g. see Lv at page 1).
Gambino further teaches:
3. The semiconductor device of claim 1, further comprising: (see fig. 1 annotated below) a trench (e.g. see trench annotated) formed in the second wafer(6) of the second chip and extending in a direction of the second die seal (14)
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Regarding claim 5:
Gambino further teaches:
5. The semiconductor device of claim 3, (see fig. 1 annotated above) wherein the trench (e.g. see trench annotated) includes a conductive material in contact (e.g. through intervening layers) with the second die seal (14).
One of ordinary skill in the art modifying Gambino with Lv would form “the trench (e.g. see trench annotated in fig. 1 above of Gambino) includes a conductive material in contact (e.g. through intervening layers) with the die seal ground contact” because Lv teaches the die seal ground contact (VIA TOP in figs. 2A, 3A of Lv) is formed directly above the die seal (M1-M6, VIA1-VIA 5) in dielectric layer (81-87).
Regarding claim 6:
Gambino further teaches a plurality of saw streets (32) in fig. 2. Since fig. 1 is a cross-section of fig. 2, Gambino teaches:
a first saw street die seal (e.g. another of the plurality of 12) in the first dielectric layer (e.g. first dielectric layer surrounding 12), a second saw street die seal (e.g. another of the plurality of 14) in the second dielectric layer (e.g. second dielectric layer surrounding 14), and a saw street hybrid bond (e.g. another HBI, para. [0037]) connecting the first saw street die seal and the second saw street die seal through the bond line (e.g. interface of another 8/16)
Gambino does not expressly teach:
a saw street electrostatic discharge path formed in a saw street and including a saw street ground contact connected to the die seal layer,
Lv teaches this limitation as applied to claim 1 above.
Regarding claim 7:
Gambino is silent:
wherein the first die seal includes a first doped layer in the first wafer, and the second die seal includes a second doped layer in the second wafer.
Lv further teaches:
(see figs. 2-3) wherein the first die seal (201, 201a) includes a first doped layer (e.g. 4/1/5, npn in fig. 2; 5a/1/4ak, pnp in fig. 3) in the first wafer (1), and the second die seal includes a second doped layer in the second wafer. See Lv at English machine translation pages 6-9.
Gambino further teaches:
9. The semiconductor device of claim 1, wherein the hybrid bond includes a copper-copper hybrid bond, para. [0037].
10. The semiconductor device of claim 1, wherein the second chip (6) includes optical sensor circuitry and the first chip (4) includes circuit chip circuitry configured to operate or receive an output of the optical sensor circuitry, para. [0037].
Regarding claim 18:
Gambino and Lv teach the limitations as applied to claim 1 above.
Regarding claim 20:
Gambino and Lv teach the limitations as applied to claim 3 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Lv because (i) “The invention can realize ESD protection function in the sealing ring so as to effectively use the area of the sealing ring to realize the ESD protection structure, it can save area and improve the integration degree.” (e.g. see Lv at Abstract) and “…electrostatic discharge (ESD) protection design is very important in improving the reliability and yield of the product.” (e.g. see Lv at page 1); and (ii) “…under the condition of an ESD event, the PN between the collector region and the base region of the NPN triode reverse avalanche breakdown occurs. forming a substrate current, PN so that between the emitter region and the base region of the NPN triode of deviation, the NPN triode is opened discharging the ESD current.” (e.g. see Lv at page 9).
Claim(s) 2, 8 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambino in view of Lv, as applied to claims 1 and 18 above, and further in view of Yang et al., US Publication No. 2024/0006425 A1 and Feng et al., US Publication No. 2023/0177866 A1.
Regarding claim 2:
Gambino and Lv teach all the limitations of claim 1 above, and Gambino further teaches:
an opening (e.g. see trench annotated in fig. 1 above or opening 18) through a surface of the second chip (6) extending through the second wafer and at least into the second dielectric layer (e.g. second dielectric surrounding 14), fig. 1.
Gambino does not expressly teach:
a light shield;
a shield connection electrically connecting the light shield and the die seal layer to thereby include the light shield in the electrostatic discharge path.
In analogous art, Yang teaches (see fig. 6) a light shield (52) formed over a die seal (70, 75). See Yang at para. [0041] – [0042].
In an analogous art, Feng teaches (see figs. 7A-7B) a light shield (38) connected to ground, para. [0101].
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
Based on the teachings of Yang and Feng, it would have been obvious to one of ordinary skill in the art, who is also a person of ordinary creativity, to modify Gambino to form “a shield connection electrically connecting the light shield and the die seal layer to thereby include the light shield in the electrostatic discharge path” because:
Yang teaches or suggests a light shielding layer formed over a die seal to provide isolation for the pixel area (e.g. Yang at para. [0042]) and enables the formation of a BLC area (e.g. “The CMOS image sensor includes one or more black level calibration (BLC) area 50 which blocks incident light and provide a reference dark voltage current, para. [0021].); and
Feng teaches a light shield is grounded to eliminate static electricity on the surface by conduction (e.g. Feng at para. [0101])
Regarding claim 8:
Gambino does not expressly teach a color filter array (CFA) and microlens array and a light shield.
In an analogous art, Yang teaches:
(see fig. 2A) a color filter array (CFA) (140) and microlens array (130) disposed on a surface of a second wafer (10 in fig. 2A; SOC in fig. 6) opposite the second dielectric layer (e.g. dielectric layer of WLs in fig. 6).
(see fig. 6) a light shield (52) disposed on the second wafer; See Yang at para. [0020] – [0023], para. [0041] – [0042].
In an analogous art, Feng teaches (see figs. 7A-7B) a light shield (38) connected to ground, para. [0101].
Based on the teachings of Yang and Feng, it would have been obvious to one of ordinary skill in the art, who is also a person of ordinary creativity, to modify Gambino to form “a light shield ground contact in contact with the second wafer” because:
Yang teaches or suggests a light shielding layer formed over a die seal to provide isolation for the pixel area (e.g. Yang at para. [0042]) and enables the formation of a BLC area (e.g. “The CMOS image sensor includes one or more black level calibration (BLC) area 50 which blocks incident light and provide a reference dark voltage current, para. [0021].); and
Feng teaches a light shield is grounded to eliminate static electricity on the surface by conduction (e.g. Feng at para. [0101])
Regarding claim 19:
Gambino, Lv, Yang and Feng teach the limitations as applied to claim 2 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Yang because (i) “Some CMOS image sensors include a dark voltage (or current) calibration (or reference) circuit (black level calibration (BLC)) to provide a reference signal as a dark voltage current (DVC). The present disclosure generally relates to a CMOS image sensor including a BLC circuit, which can provide a more reliable and correct DVC for the black level calibration.” (e.g. Yang at para. [0019]); and (ii) “The color filters include three colors (e.g., RGB) arranged in a Bayer's pattern.” (e.g. Yang at para. [0026]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Feng because a light shield is grounded to eliminate static electricity on the surface by conduction. See Feng at para. [0101].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambino in view of Lv, as applied to claim 1 above, and further in view of Anderson et al., US Patent No. 6,867,460 B1.
Regarding claim 4:
Referring to fig. 1 annotated above, Gambino teaches the trench includes a conductive material.
Gambino does not expressly teach the trench includes a doped layer.
In an analogous art, Anderson teaches a contacts formed in a trench may comprise metal materials or doped polysilicon. See Anderson at col 5, ln 5–15.
It is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Anderson because one of ordinary skill in the art would be motivated to look for alternative conductive materials to fill the trench and Anderson teaches metal materials or doped polysilicon are known materials suitable to form a contact/connection.
Claim(s) 21-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gambino in view of Lv, Yang and Feng.
Regarding claim 21:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 1 and 2 above.
Regarding claim 22:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 2 above.
Regarding claim 23:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 3 above.
Regarding claim 24:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 4 above.
Regarding claim 25:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 5 above.
Regarding claim 26:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 6 above.
Regarding claim 27:
Gambino, Lv, Yang and Feng teach the limitations as applied to claims 1 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Lv because “The invention can realize ESD protection function in the sealing ring so as to effectively use the area of the sealing ring to realize the ESD protection structure, it can save area and improve the integration degree.” (e.g. see Lv at Abstract) and “…electrostatic discharge (ESD) protection design is very important in improving the reliability and yield of the product.” (e.g. see Lv at page 1).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Yang because (i) “Some CMOS image sensors include a dark voltage (or current) calibration (or reference) circuit (black level calibration (BLC)) to provide a reference signal as a dark voltage current (DVC). The present disclosure generally relates to a CMOS image sensor including a BLC circuit, which can provide a more reliable and correct DVC for the black level calibration.” (e.g. Yang at para. [0019]); and (ii) “The color filters include three colors (e.g., RGB) arranged in a Bayer's pattern.” (e.g. Yang at para. [0026]).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Gambino with the teachings of Feng because a light shield is grounded to eliminate static electricity on the surface by conduction. See Feng at para. [0101].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
14 May 2026
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