DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention Group I, Species I (FIG. 26), and Subspecies B (FIG. 25) in the reply filed on 3/27/2026 is acknowledged.
Applicant submit claims 1-4, 7-16 and 21-23 direct to the elections made.
However, upon closer examination, claim 7 reciting “the low-k dielectric layer is thicker than the high-k dielectric layer” pertains to a feature of non-elected Species II as shown in FIG. 27. More specifically, FIG. 26 of Species I describes the low-k dielectric layer 164 and the high-k dielectric layer 152b have the same thickness, FIG. 27 of Species II describes the low-k dielectric layer 164 being thicker than the high-k dielectric layer 152b, and FIG. 28 of Species III describes the low-k dielectric layer 164 being thinner than the high-k dielectric layer 152b.
Therefore, as best understood, claim 7 does not pertain to the elected Species I of FIG. 26 showing the low-k dielectric layer and the high-k dielectric layer having a same thickness.
Claims 5-7 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/27/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sung et al. US 2019/0088759 A1 (Sung).
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In re claim 11, Sung discloses (e.g. FIGs. 1-3 & 6) a method, comprising:
forming vertically stacked channel members 116 suspended above a substrate 110 (FIG. 6);
forming an epitaxial material 131 abutting opposing ends of the channel members 116 (FIG. 6);
depositing a gate dielectric layer 140 wrapping around the channel members 116;
depositing a first gate electrode 152 over the gate dielectric layer 140 (FIG. 3B);
recessing the first gate electrode 152 (FIG. 3C) and the gate dielectric layer 140 (FIGs. 1C & 2A);
forming a spacer layer 160 over the gate dielectric layer 140, wherein a dielectric constant of the spacer layer 160 is less than a dielectric constant of the gate dielectric layer 140 (¶ 22,30);
depositing a second gate electrode 154 over the first gate electrode 152 (FIG. 3D), wherein the spacer layer 160 is disposed on sidewalls of the second gate electrode 154 (see FIG. 3D); and
forming a contact 132 over the epitaxial material 131, wherein the spacer layer 160 is laterally stacked between the contact 132 and the second gate electrode 154.
In re claim 13, Sung discloses (e.g. FIG. 6) further comprising:
forming gate spacers 120 over the epitaxial material 131, wherein the gate spacers 120 are in physical contact with the spacer layer 160.
In re claim 14, Sung discloses (e.g. FIGs. 3D & 6) wherein the gate spacers 120 are in physical contact with the gate dielectric layer 140.
In re claim 15, Sung discloses (e.g. FIGs. 3D & 6) wherein a bottom surface of the second gate electrode 154 is below a bottom surface of the spacer layer 160.
In re claim 16, Sung discloses (e.g. FIGs. 3D & 6) wherein the dielectric constant of the spacer layer 160 is less than about 2.5 (e.g. less than 2.5 or 2.0, ¶ 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Sung as applied to claim 11 above, and further in view of Chanemougame et al. US 2018/0204927 A1 (Chanemougame).
In re claim 12, Sung discloses (e.g. FIG. 2-3) wherein the forming of the spacer layer 160 includes:
conformally depositing a dielectric layer 160 (FIG. 2B) over the gate dielectric layer 140 and removing horizontal portions of the dielectric layer 160 (FIG. 2C), wherein the vertical portion of the dielectric layer 160 remains as the spacer layer 160 (FIG. 2C & 3A).
Sung discloses forming the lower first gate metal after forming the low-k dielectric spacer layer 160 on the sidewall of the gate spacer 120.
Sung does not explicitly disclose forming the first gate electrode prior to depositing the dielectric layer to form the low-k spacer layer such that the dielectric layer is deposited over the first gate electrode and removing the horizontal portions of the dielectric layer exposes the first gate electrode.
However, Chanemougame teaches (e.g. FIGs. 1-22) a method of forming a replacement gate structure comprising depositing a gate dielectric layer 261 and a lower metal gate 262, recessing the lower gate electrode (¶ 35, FIGs. 8A-8B), forming a low-k dielectric layer 270 (low-k due to air gap 271, FIG. 12) over the gate dielectric layer 261 and the lower metal gate 262, removing horizontal portions of the dielectric layer 270 to expose the lower gate electrode 260 (FIG. 21, ¶ 49), wherein vertical portions of the dielectric layer 270 remains as spacer layer 276, and depositing upper gate metal 295 (¶ 50, FIG. 22) over the lower gate electrode 260 , wherein the spacer layer 276 is disposed on sidewalls of the upper gate metal 295 and is laterally between source/drain contact 248,294 and upper gate metal 295.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Sung’s low-k dielectric layer 160 after forming the first gate electrode 152, followed removing horizontal portions to expose the underlying first gate electrode with remaining vertical portions of the low-k dielectric layer 160 forming the spacer layer as taught by Chanemougame such that a subsequent low contact resistance second gate electrode 254 is provided above the first gate electrode and is spaced from the source/drain contact with the low-k spacer in between to reduce capacitive coupling.
Claims 1-4, 8-10, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. US 2019/0088759 A1 (Sung) in view of Liaw US 2021/0098627 A1.
In re claim 1, Sung discloses (e.g. FIGs. 1-3 & 6) a method of manufacturing a semiconductor device, comprising:
forming stacked nanowire channels 116 over a substrate 110;
patterning the nanowire channels 116 to form a fin structure (FIG. 6);
forming a dummy gate structure (not shown, ¶ 16) across the fin structure;
depositing gate spacers 120 over sidewalls of the dummy gate structure (¶ 18);
removing the dummy gate structure to form a recess 122, the recess 122 exposing sidewalls of the gate spacers 120 (FIG. 1A);
depositing an interfacial layer (silicon dioxide of 140, ¶ 22) around the nanowire channels 116;
depositing a high-k dielectric layer (high-k gate dielectric of 140, ¶ 22) over the interfacial layer and over the sidewalls of the gate spacers 120 (FIG. 1B);
depositing a first gate electrode 152 over the high-k dielectric layer 140 (FIG. 3B);
recessing the first gate electrode 152 (FIG. 3C);
recessing the high-k dielectric layer 140 to expose a top portion of the sidewalls of the gate spacers 120 (FIGs. 1C & 2A);
depositing a low-k dielectric layer 160 (¶ 30) over the recessed high-k dielectric layer 140 and over the exposed top portion of the sidewalls of the gate spacers 120 (FIGs. 2B & 3C); and
depositing a second gate electrode 154 over the first gate electrode 152 (FIG. 3D).
Sung does not explicitly disclose the stacked nanowire channels 116 are formed by alternately stacking first semiconductor layers and second semiconductor layers over a substrate; patterning the first and second semiconductor layers into a fin structure; laterally recessing end portions of the first semiconductor layers; forming inner spacers on end portions of the first semiconductor layers; removing the first semiconductor layers thereby forming gaps between the second semiconductor layers; depositing an interfacial layer wrapping around each of the second semiconductor layers.
Liaw discloses (e.g. FIGs. 1-27) a method of manufacturing a semiconductor device, comprising:
alternately stacking first semiconductor layers 220B and second semiconductor layers 220A over a substrate 200 (FIG. 2);
patterning the first and second semiconductor layers into a fin structure 130a,130b (FIG. 3);
forming a dummy gate structure 210 across the fin structure 130a,130b (FIG. 4);
depositing gate spacers 240 over sidewalls of the dummy gate structure 210 (FIG. 5);
laterally recessing end portions of the first semiconductor layers 220B (FIG. 7);
forming inner spacers 250 on end portions of the first semiconductor layers 220B (FIG. 9);
removing the dummy gate structure 210 to form a recess 153 (FIG. 12), the recess 153 exposing sidewalls of the gate spacers 240;
removing the first semiconductor layers 220B thereby forming gaps 157 between the second semiconductor layers 220A (FIG. 13);
depositing an interfacial layer (¶ 42) wrapping around each of the second semiconductor layers 220A;
depositing a high-k dielectric layer 228 (¶ 42) over the interfacial layer and over the sidewalls of the gate spacers 240;
depositing a first gate electrode 230,232 over the high-k dielectric layer 228.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Sung’s stacked nanowire channels according to the method steps taught by Liaw to form high density stack nanosheet device as is well-known in the art.
In re claim 2, Sung discloses (e.g. FIGs. 3D & 6) further comprising:
forming an epitaxial feature 131 abutting end portions of the second semiconductor layers 116 (nanowire channels, see FIG. 6); and
forming a contact 132 over and in electrical coupling with the epitaxial feature 131, wherein the low-k dielectric layer 160 is laterally stacked between the contact 132 and the second gate electrode 154.
In re claim 3, Sung discloses (e.g. FIGs. 3D & 6) wherein a topmost portion of the high-k dielectric layer 140 is above a top surface of the recessed first gate electrode 152.
In re claim 4, Sung discloses (e.g. FIG. 4) wherein the topmost portion of the high-k dielectric layer 140 is above the top surface of the recessed first gate electrode 152 for a vertical distance of H1-(T1+T2). Sung teaches recessing high-k dielectric 140 is controlled to avoid breaking the layer that would impact the proper function of the gate dielectric layer (¶ 34). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to etch back the high-k dielectric 140 by minimizing its height H1 without affecting gate dielectric function. As such, forming the high-k dielectric 140 to a height H1 that is less than about 2 nm above the top surface of first gate electrode 152 would be obvious to optimize. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 8, Sung discloses (e.g. FIG. 3D) the high-k dielectric layer 140 includes hafnium-containing material (¶ 22). No specific hafnium-containing impurities have been claimed that would distinguish over the hafnium-containing material present at an interface between the low-k dielectric layer 160 and the high-k dielectric layer 140.
In re claim 9, Sung discloses (e.g. FIG. 3D) the first gate electrode 152 includes titanium-containing or aluminum-containing material (¶ 25). No specific titanium-containing or aluminum-containing impurities have been claimed that would distinguish over the titanium-containing or aluminum-containing material present at an interface between the first gate electrode 152 and the second gate electrode 154.
In re claim 10, Sung discloses (e.g. FIG. 3D) wherein the low-k dielectric layer 160 (k of less than 2.0, ¶ 30) has a dielectric constant value less than the gate spacers 120 (e.g. silicon nitride, ¶ 18).
In re claim 21, Sung discloses (e.g. FIGs. 1-3 & 6) a method of manufacturing a semiconductor device, comprising:
forming stacked nanowire channels 116 over a substrate 110;
patterning the nanowire channels 116 to form a fin structure (FIG. 6);
forming a dummy gate structure (not shown, ¶ 16) across the fin structure;
depositing gate spacers 120 over sidewalls of the dummy gate structure (¶ 18);
forming first and second epitaxial features 131 sandwiching the nanowire channels 116;
depositing an interlayer dielectric layer 174 over the gate spacers 120 and over the first and second epitaxial structures 131 (FIG. 6)
removing the dummy gate structure to form a gate trench 122, the gate trench 122 exposing sidewalls of the gate spacers 120 (FIG. 1A);
depositing a first gate dielectric layer 140 around the nanowire channels 116 and over the sidewalls of the gate spacers 120 (FIG. 1B);
depositing a first gate electrode 152 over the first gate dielectric layer 140 (FIG. 3B);
recessing the first gate electrode 152 (FIG. 3C);
recessing the first gate dielectric layer 140 to expose a top portion of the sidewalls of the gate spacers 120 (FIGs. 1C & 2A);
depositing a second gate dielectric layer 160 over the recessed first gate dielectric layer 140 and over the exposed top portion of the sidewalls of the gate spacers 120 (FIGs. 2B & 3C), wherein a dielectric constant of the first gate dielectric layer 140 is greater than a dielectric constant of the second gate dielectric layer 160 (¶ 22,30); and
depositing a second gate electrode 154 over the first gate electrode 152 (FIG. 3D).
Sung does not explicitly disclose the stacked nanowire channels 116 are formed by alternately stacking first semiconductor layers and second semiconductor layers over a substrate; patterning the first and second semiconductor layers into a fin structure; removing the first semiconductor layers from the gate trench to form gaps between the second semiconductor layers.
Liaw discloses (e.g. FIGs. 1-27) a method of manufacturing a semiconductor device, comprising:
alternately stacking first semiconductor layers 220B and second semiconductor layers 220A over a substrate 200 (FIG. 2);
patterning the first and second semiconductor layers into a fin structure 130a,130b (FIG. 3);
forming a dummy gate structure 210 across the fin structure 130a,130b (FIG. 4);
depositing gate spacers 240 over sidewalls of the dummy gate structure 210 (FIG. 5);
forming first and second epitaxial features 208 (FIG. 10) sandwiching the first and second semiconductor layer 220A,220B;
depositing an interlayer dielectric layer 214 over the gate spacers 240 and over the first and second epitaxial features 208;
removing the dummy gate structure 210 to form a gate trench 153 (FIG. 12), the gate trench 153 exposing sidewalls of the gate spacers 240;
removing the first semiconductor layers 220B from the gate trench 153 to form gaps 157 between the second semiconductor layers 220A (FIG. 13);
depositing a first gate dielectric layer 228 (¶ 42) in the gaps 157 and over the sidewalls of the gate spacers 240;
depositing a first gate electrode 230,232 over the first gate dielectric layer 228.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Sung’s stacked nanowire channels according to the method steps taught by Liaw to form high density stack nanosheet device as is well-known in the art.
In re claim 22, Sung discloses (e.g. FIG. 3D) wherein the second gate electrode 154 interfaces with both the first gate dielectric layer 140 and the second gate dielectric layer 160.
In re claim 23, Sung discloses (e.g. FIG. 6) wherein a bottom surface of the second gate electrode 154 is below a top surface of a topmost one of the nanowire channels 116.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights