DETAILED ACTION
This office action is in response to amendment filed 9/3/2026.
Claims 1-17 and 21-23 are pending. Claims 18-20 have been canceled. Claims 5-6 and 17 have been withdrawn. Claims 1, 11, and 21 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7-16, and 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame et al. US 2018/0204927 A1 (Chanemougame) in view of Liaw US 2021/0098627 A1.
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In re claim 1, Chanemougame discloses (e.g. FIGs. 1-22) a method of manufacturing a semiconductor device, comprising:
patterning a semiconductor layer into a fin structure 210 (FIG. 2);
forming a dummy gate structure 231 (FIG. 3, ¶ 31) across the fin structure 210;
depositing gate spacers 240,241 over sidewalls of the dummy gate structure 231 (FIGs. 4-6);
removing the dummy gate structure 231 to form a recess 243 (FIGs. 7A-7B), the recess 243 exposing sidewalls of the gate spacers 240,241 (FIGs. 7A-7B);
depositing a high-k dielectric layer 261 (high-k dielectric, ¶ 35,56) over fin structure 201 and over the sidewalls of the gate spacers 240,241 (FIGs. 8A-8B);
depositing a first gate electrode 262 over the high-k dielectric layer 261 (FIGs. 8A-8B);
recessing the first gate electrode 262 (CMP of 262, ¶ 35);
after the recessing the first gate electrode 262 (after CMP, ¶ 35), recessing the high-k dielectric layer 261 (recessing of 260 including 261 after CMP, ¶ 35) to expose a top portion of the sidewalls of the gate spacers 240 (FIGs. 8A-8B);
depositing a low-k dielectric layer 270 (FIG. 12 & FIG. 21, low k silicon oxycarbide and due to air gap 271, ¶ 40) over the recessed high-k dielectric layer 261 and over the exposed top portion of the sidewalls of the gate spacers 241 (FIG. 12); and
depositing a second gate electrode 295 over the first gate electrode 262 (FIG. 22).
Chanemougame discloses the device is a FinFET and does not explicitly disclose stacked nanowire channels formed by alternately stacking first semiconductor layers and second semiconductor layers over a substrate; patterning the first and second semiconductor layers into a fin structure; laterally recessing end portions of the first semiconductor layers; forming inner spacers on end portions of the first semiconductor layers; removing the first semiconductor layers thereby forming gaps between the second semiconductor layers; depositing an interfacial layer wrapping around each of the second semiconductor layers.
However, owever, Liaw discloses (e.g. FIGs. 1-27) a method of manufacturing a semiconductor device, comprising:
alternately stacking first semiconductor layers 220B and second semiconductor layers 220A over a substrate 200 (FIG. 2);
patterning the first and second semiconductor layers into a fin structure 130a,130b (FIG. 3);
forming a dummy gate structure 210 across the fin structure 130a,130b (FIG. 4);
depositing gate spacers 240 over sidewalls of the dummy gate structure 210 (FIG. 5);
laterally recessing end portions of the first semiconductor layers 220B (FIG. 7);
forming inner spacers 250 on end portions of the first semiconductor layers 220B (FIG. 9);
removing the dummy gate structure 210 to form a recess 153 (FIG. 12), the recess 153 exposing sidewalls of the gate spacers 240;
removing the first semiconductor layers 220B thereby forming gaps 157 between the second semiconductor layers 220A (FIG. 13);
depositing an interfacial layer (¶ 42) wrapping around each of the second semiconductor layers 220A;
depositing a high-k dielectric layer 228 (¶ 42) over the interfacial layer and over the sidewalls of the gate spacers 240;
depositing a first gate electrode 230,232 over the high-k dielectric layer 228.
Liaw discloses gate-all-around devices GAA are well-known replacement for FinFETs in the art (¶ 14-15) with known advantages including better gate control, increased power efficiency and high scalability. Liaw further discloses providing an interfacial layer between the semiconductor channel and the high-k dielectric layers to improve adhesion (¶ 42).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame’s device as a stacked nanowire channels gate-all-around device according to the method steps taught by Liaw to form high density stack nanosheet device for its well-known advantages including better gate control, increased power efficiency and high scalability.
It is further obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide an interfacial dielectric layer in Chanemougame’s device to improve adhesion between the semiconductor channel and the gate dielectric as taught by Liaw.
In re claim 2, Chanemougame discloses (e.g. FIGs. 1-22) further comprising:
forming an epitaxial material 212,213 abutting opposing ends of the channel 211 (FIGs. 4-5);
forming a contact 294 over and in electrical coupling with the epitaxial material 212,213, wherein the low-k dielectric layer 270 is laterally stacked between the contact 294 and the second gate electrode 295.
Liaw discloses (e.g. FIG. 10B) forming an epitaxial material 208 abutting opposing ends of the second semiconductor layers 220A.
In re claim 7, Chanemougame discloses (e.g. FIG. 12) wherein the low-k dielectric layer 270 is thicker than the high-k dielectric layer 261.
In re claim 8, Chanemougame (e.g. FIG. 8) the high-k dielectric layer 261 includes art recognized high-k dielectric material (¶ 56).
Liaw discloses (e.g. FIG. 14) the high-k gate dielectric layer 228 may include hafnium oxide (¶ 42).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame’s high-k gate dielectric 261 with hafnium oxide as a suitable high-k gate dielectric material as taught by Liaw.
As such, the hafnium-containing material present at an interface between Chanemougame’s the low-k dielectric 270 and the high-k dielectric layer 261 teaches the claimed hafnium-containing impurities.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 9, Chanemougame discloses (e.g. FIG. 22) the second gate electrode 295 includes aluminum-containing material (¶ 50). No specific titanium-containing or aluminum-containing impurities have been claimed that would distinguish over the aluminum-containing material present at an interface between the first gate electrode 262 and the second gate electrode 295.
Furthermore, Liaw discloses (FIG. 15) the first gate electrode includes titanium-containing or aluminum-containing material (¶ 43).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame’s first gate electrode 262 with titanium-containing or aluminum-containing material as a gate metal as taught by Liaw to achieve desired work function as taught by Chanemougame (¶ 56).
As such, titanium-containing or aluminum-containing material present at an interface between Chanemougame’s the first gate electrode 262 and the second gate electrode 295teaches the claimed titanium-containing or aluminum-containing impurities.
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
In re claim 10, Chanemougame discloses (e.g. FIG. 4-12) wherein the low-k dielectric layer 270 (low k silicon oxycarbide and due to air gap 271, ¶ 40) has a dielectric constant value less than the gate spacers 240,241 (e.g. silicon nitride, ¶ 35,59).
In re claim 11, Chanemougame discloses (e.g. FIGs. 1-22) a method, comprising:
forming channel members 211 above a substrate 110 (FIG. 6);
forming an epitaxial material 212,213 abutting opposing ends of the channel members 211 (FIGs. 4-5);
depositing a gate dielectric layer 261 wrapping around the channel members 211 (FIG. 8A);
depositing a first gate electrode 262 over the gate dielectric layer 261 (FIG. 8A);
recessing the first gate electrode 262 and the gate dielectric layer 261 (CMP and recessing of 260, ¶ 35, see FIG. 8A);
after the recessing of the first gate electrode 262 and the gate dielectric layer 261, forming a spacer layer 270 (FIG. 12 & FIG. 21) over the gate dielectric layer 261, wherein a dielectric constant of the spacer layer 270 (low k silicon oxycarbide and due to air gap 271, ¶ 40) is less than a dielectric constant of the gate dielectric layer 261 (high-k dielectric, ¶ 35,56);
depositing a second gate electrode 295 (FIG. 22) over the first gate electrode 262 (FIG. 22), wherein the spacer layer 270 is disposed on sidewalls of the second gate electrode 295 (see FIG. 22); and
forming a contact 294 over the epitaxial material 212,213, wherein the spacer layer 270 is laterally stacked between the contact 294 and the second gate electrode 295.
Chanemougame discloses the device is a FinFET and does not explicitly disclose the channel members are formed by vertically stacked channel members suspended above the substrate.
However, Liaw discloses (e.g. FIGs. 1-27) a method of manufacturing a stacked nanosheet device comprising forming vertically stacked channel members 220A suspended above a substrate 200 (FIG. 2), and forming an epitaxial material 208 abutting opposing ends of the channel members 220A (FIG. 10B). Liaw discloses gate-all-around devices GAA are well-known replacement for FinFETs in the art (¶ 14-15) with known advantages including better gate control, increased power efficiency and high scalability.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame’s device as a stacked nanowire channels gate-all-around device according to the method steps taught by Liaw to form high density stack nanosheet device for its well-known advantages including better gate control, increased power efficiency and high scalability.
In re claim 12, Chanemougame discloses (e.g. FIGs. 1-22) the forming of the spacer layer 270 (FIG. 21) includes:
conformally depositing a dielectric layer 270 (FIG. 12) over the gate dielectric layer 261 and the first gate electrode 262; and
removing horizontal portions of the dielectric layer 270 to expose the first gate electrode 260 (FIG. 21, ¶ 49), wherein vertical portions of the dielectric layer 270 remains as spacer layer.
In re claim 13, Chanemougame discloses further comprising:
forming gate spacers 240,241 over the epitaxial material 212,213 (e.g. FIG. 4-5), wherein the gate spacers 240,241 are in physical contact with the spacer layer 270 (FIG. 22).
In re claim 14, Chanemougame discloses (e.g. FIG. 22) wherein the gate spacers 240,241 are in physical contact with the gate dielectric layer 261.
In re claim 15, in an alternative interpretation, dielectric 249 taught by Chanemougame (e.g. FIG. 22, ¶ 36) teaches the “spacer layer” that is formed over the gate dielectric layer 261, and is disposed on sidewalls of the second gate electrode 295, and is between the contact 294 and the second gate electrode 295, wherein spacer layer 249 (e.g. silicon oxide, ¶ 36) has a lower dielectric constant than the high-k gate dielectric layer 261. As such, Chanemougame teaches (e.g. FIG. 22) wherein a bottom surface of the second gate electrode 295 is below a bottom surface of the spacer layer (bottom of 249).
In re claim 16, Chanemougame discloses (e.g. FIG. 22) wherein the dielectric constant of the spacer layer 270 is less than about 2.5 (containing air gap 271 with dielectric constant of about 1).
In re claim 21, Chanemougame discloses (e.g. FIGs. 1-22) a method of manufacturing a semiconductor device, comprising:
patterning a semiconductor layer to form a fin structure 210 (FIG. 2);
forming a dummy gate structure 231 (FIG. 3, ¶ 31) across the fin structure 210;
depositing gate spacers 240,241 over sidewalls of the dummy gate structure 231 (FIGs. 4-6);
forming first and second epitaxial features 212,213 sandwiching the fin channel 211 (FIGs. 4-5);
depositing an interlayer dielectric layer 250 (FIG. 6, ¶ 33) over the gate spacers 240,241 and over the first and second epitaxial features 212,213;
removing the dummy gate structure 231 to form a gate trench 243 (FIGs. 7A-7B), the gate trench 243 exposing sidewalls of the gate spacers 240,241 (FIGs. 7A-7B);
depositing a first gate dielectric layer 261 (high-k dielectric, ¶ 35,56) over fin structure 201 and over the sidewalls of the gate spacers 240,241 (FIGs. 8A-8B);
depositing a first gate electrode 262 over the first gate dielectric layer 261 (FIGs. 8A-8B);
recessing the first gate electrode 262 (CMP of 262, ¶ 35);
after the recessing the first gate electrode 262 (after CMP, ¶ 35), recessing the first gate dielectric layer 261 (recessing of 260 including 261 after CMP, ¶ 35) to expose a top portion of the sidewalls of the gate spacers 240 (FIGs. 8A-8B);
depositing a second gate dielectric layer 270 (FIG. 12, ¶ 40) over the recessed first gate dielectric layer 261 and over the exposed top portion of the sidewalls of the gate spacers 241 (FIG. 12), wherein a dielectric constant of the first gate dielectric layer 261 (high-k dielectric, ¶ 35,56) is greater than a dielectric constant of the second gate dielectric layer 270 (low k silicon oxycarbide and due to air gap 271, ¶ 40); and
depositing a second gate electrode 295 over the first gate electrode 262 (FIG. 22).
Chanemougame discloses the device is a FinFET and does not explicitly disclose stacked nanowire channels formed by alternately stacking first semiconductor layers and second semiconductor layers over a substrate; patterning the first and second semiconductor layers into a fin structure; forming first and second epitaxial features sandwiching the first and second semiconductor layers; removing the first semiconductor layers from the gate trench to form gaps between the second semiconductor layers; depositing the first gate dielectric layer in the gaps.
However, Liaw discloses (e.g. FIGs. 1-27) a method of manufacturing a semiconductor device, comprising:
alternately stacking first semiconductor layers 220B and second semiconductor layers 220A over a substrate 200 (FIG. 2);
patterning the first and second semiconductor layers into a fin structure 130a,130b (FIG. 3);
forming a dummy gate structure 210 across the fin structure 130a,130b (FIG. 4);
depositing gate spacers 240 over sidewalls of the dummy gate structure 210 (FIG. 5);
forming first and second epitaxial features 208 (e.g. FIG. 10B) sandwiching the first and second semiconductor layers 220A,220B;
depositing an interlayer dielectric layer 214 over the gate spacers 240 and over the first and second epitaxial features 208 (e.g. FIG. 11);
removing the dummy gate structure 210 to form a gate trench 153 (FIG. 12), the gate trench 153 exposing sidewalls of the gate spacers 240;
removing the first semiconductor layers 220B from the gate trench 153 to form gaps 157 between the second semiconductor layers 220A (FIG. 13);
depositing a first gate dielectric layer 228 (¶ 42) in the gaps 157 and over the sidewalls of the gate spacers 240;
depositing a first gate electrode 230,232 over the first gate dielectric layer 228.
Liaw discloses gate-all-around devices GAA are well-known replacement for FinFETs in the art (¶ 14-15) with known advantages including better gate control, increased power efficiency and high scalability.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame’s device as a stacked nanowire channels gate-all-around device according to the method steps taught by Liaw to form high density stack nanosheet device for its well-known advantages including better gate control, increased power efficiency and high scalability.
In re claim 22, Chanemougame discloses (e.g. FIG. 22) wherein the second gate electrode 295 interfaces with both the first gate dielectric layer 261 and the second gate dielectric layer 270.
Claims 3-4 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chanemougame and Liaw as applied to claim 1 and 21 above, and further in view of Sung et al. US 2019/0088759 A1 (Sung).
In re claim 3, Chanemougame a high-k dielectric layer 261 surrounding a recessed first gate electrode 262 (FIG. 8). Chanemougame does not explicitly disclose a topmost portion of the high-k dielectric layer 261 is above a top surface of the recessed first gate electrode 262.
However, Sung discloses (e.g. FIGs. 3D & 6) a replacement gate structure formed around stacked nanowire channels 116, including a high-k first gate dielectric layer 140, a low-k second gate dielectric layer 160, a first gate electrode 152 and a second gate electrode 154. Sung teaches the provision of low resistance second gate metal 154 over the first gate metal 152 to decrease the electrical resistance (¶ 32) while the first gate metal is present close to the channel for better control of carriers (¶ 26). Sung further disclose the height H2 at a topmost portion of the high-k gate dielectric layer 140 is above a top surface of the recessed first gate electrode 152 to avoid breaking the layer that would impact the proper function of the gate dielectric layer (¶ 34)
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Chanemougame replacement gate structure 260 to include a recessed first gate metal and a high-k gate dielectric layer 140 with a topmost portion above a top surface of the recessed first gate metal as taught by Sung to achieve the desired gate control property while ensuring proper gate dielectric function as detailed by Sung.
In re claim 4, Sung discloses (e.g. FIG. 4) wherein the topmost portion of the high-k dielectric layer 140 is above the top surface of the recessed first gate electrode 152 for a vertical distance of H1-(T1+T2). Sung teaches recessing high-k dielectric 140 is controlled to avoid breaking the layer that would impact the proper function of the gate dielectric layer (¶ 34). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to etch back the high-k dielectric 140 by minimizing its height H1 without affecting gate dielectric function. As such, forming the high-k dielectric 140 to a height H1 that is less than about 2 nm above the top surface of first gate electrode 152 would be obvious to optimize. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 23, Chanemougame a recessed replacement gate structure 260 (FIG. 8). Liaw teaches stacked nanowire channels formed of second semiconductor layers 220A for a gate-all-around devices. Chanemougame and Liaw do not explicitly disclose the gate structure include a second gate electrode with a bottom surface that is below a top surface of a topmost one of the second semiconductor layers.
However, Sung discloses (e.g. FIGs. 3D & 6) a replacement gate structure formed around stacked nanowire channels 116, including a first gate electrode 152 and a second gate electrode 154, wherein (e.g. FIG. 6) wherein a bottom surface of the second gate electrode 154 is below a top surface of a topmost one of the nanowire channels 116.
Sung teaches the provision of low resistance second gate metal 154 over the first gate metal 152 to decrease the electrical resistance (¶ 32) while the first gate metal is present close to the channel for better control of carriers (¶ 26).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form a replacement gate structure around stacked nanowires, including a recessed first gate electrode and a second low resistance gate electrode such that a bottom surface of the second gate electrode is below a top surface of a topmost one of the nanowire channels as taught by Sung to achieve the desired gate control property with low electrical contact resistance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 7-16, and 21-23 have been considered but are moot because the new ground of rejection does not rely on the application of the reference in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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