Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1) in view of Yeom et al. (US-20040013014-A1 referred as Yeom) and Zhou (CN-107623034-B).
Regarding claim 1. Kim discloses a method of forming a semiconductor structure, comprising: forming a trench in a substrate ([0097], figure 4A, a trench #15 is formed in the substrate #11); forming a dielectric layer to cover an inner surface of the trench ([0099], figure 4B, the dielectric layer #17 is formed in the inner surface of the trench #15);
depositing a bottom conductive layer on the dielectric layer and in the trench ([0116], figure 4F, deposit the bottom conductive layer #21a on the dielectric layer #17 and in the trench #15);
removing a portion of the bottom conductive layer to form a recess on the bottom conductive layer and in the trench ([0118], figure 4G, the removal of a portion of the bottom conductive layer #21a forms a recess within the trench); and
forming a top conductive layer in the recess ([0138], figure 4N, forming a top conductive layer #25).
Kim lacks depositing a bottom conductive layer at a first temperature of 350 °C to 450 °C; and performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C wherein an annealing time is between 30 minutes to 100 minutes, and the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere.
Yeom discloses depositing a bottom conductive layer at a first temperature of 350 °C to 450 °C ([0047], the deposition of titanium nitride layer (which is a conductive layer) at about 350 °C to 450 °C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include depositing a conductive layer at 350 °C to 450 °C as taught by Yeom in order to increase deposition control in uniform film thickness, quality, and oxidation.
Kim as modified by Yeom still lacks performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C wherein an annealing time is between 30 minutes to 100 minutes, and the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere.
Zhou discloses performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C wherein an annealing time is between 30 minutes to 100 minutes, and the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere ([bottom 3 paragraphs of pg 12 from Machine Translation], after the conductive layer (bottom conductive layer) is formed, it is then annealed at a temperature of 470-500 C with the annealing time of 30-60 minutes inside of a nitrogen gas atmosphere, as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified by Yeom to include annealing the conductive layer within a temperature range of 470-500 °C and annealing time of 30-60 minutes while inside a nitrogen gas atmosphere as taught by Zhou in order to enhance the elements hardness, reduce residual stress, and to improve overall performance.
Regarding claim 2. Kim as modified discloses wherein the bottom conductive layer comprises titanium nitride ([0045], figure 4N, the bottom conductive layer #21 which is part of #LB may consist of titanium nitride).
Regarding claim 3. Kim as modified discloses wherein the top conductive layer comprises polysilicon ([0050], figure 4N, the top conductive layer #25 which is part of #UB may consists of polysilicon).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Zhou (CN-107623034-B) in further view of Tsai (US-20230197832-A1 referred as Tsai #1).
Regarding claim 8. Kim as modified lacks wherein the trench has a width of 12 nm to 30 nm.
Tsai #1 discloses wherein the trench has a width of 12 nm to 30 nm ([0030], trenches #30 have a width from 20-30nm as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the trench has a width of 12 nm to 30 nm as taught by Tsai #1 in order to enhance device performance, reduce unwanted electrical signal, and to improve reliability.
Claim 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Zhou (CN-107623034-B) in further view of Li (US-20230024465-A1).
Regarding claim 9. Kim as modified lacks wherein depositing the bottom conductive layer is performed by chemical vapor deposition or physical vapor deposition.
Li discloses wherein depositing the bottom conductive layer is performed by chemical vapor deposition or physical vapor deposition ([0033], figure 12, the bottom conductive layer #116 is formed by a physical vapor deposition as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the bottom conductive layer is performed by a physical vapor deposition as taught by Li in order to enhance purity in the element, increase durability and to allow corrosion resistance.
Regarding claim 10. Kim as modified lacks further comprising: before forming the trench in the substrate, forming a doped region in the substrate, wherein after forming the trench in the substrate, the trench penetrates through the doped region.
Li discloses further comprising: before forming the trench in the substrate, forming a doped region in the substrate, wherein after forming the trench in the substrate, the trench penetrates through the doped region ([0027], figure 4-5, the doped region #102 is formed to the substrate #100 and then formed with a trench #104 afterwards penetrating both the doped region #102 and substrate #100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include forming a doped region on a substrate and then forming a trench through both elements as taught by Li in order to enhance device performance, support for high density integration, and prevention of interference.
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Zhou (CN-107623034-B) in further view of Tsai (US-20220059666-A1 referred as Tsai #2).
Regarding claim 21. Kim as modified lacks further comprising:
before forming the trench in the substrate, forming a hard mask layer on the substrate;
when forming the trench in the substrate, forming the trench to penetrate the hard mask layer; and
when forming the dielectric layer to cover the inner surface of the trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer.
Tsai #2 discloses further comprising:
before forming the trench in the substrate, forming a hard mask layer on the substrate ([0051], fig 2, before the trench is formed, a hard mask layer #105 is formed on the substrate #101);
when forming the trench in the substrate, forming the trench to penetrate the hard mask layer ([0069], figure 4, the trench in the substrate #101 is formed which also includes penetrating the hard mask layer #105); and
when forming the dielectric layer to cover the inner surface of the trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer ([0102-0104], figure 16, in another embodiment after steps figures 2-4 is seen forming the dielectric layer #201 to cover the inner surface of the trench and the upper surface of the hard mask layer #105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include forming the dielectric layer on the inner trench and the upper surface of the hard mask as taught by Tsai #2 in order improve electrical protection, increase the devices lifetime, and to reduce device failures.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), Zhou (CN-107623034-B) and Tsai (US-20220059666-A1 referred as Tsai #2) in further view of Lu et al. (US-7309632-B1 referred as Lu).
Regarding claim 22. Kim as modified lacks wherein after removing the portion of the bottom conductive layer to form the recess on the bottom conductive layer and in the trench, the dielectric layer on the upper surface of the hard mask layer is exposed.
Lu discloses wherein after removing the portion of the bottom conductive layer to form the recess on the bottom conductive layer and in the trench, the dielectric layer on the upper surface of the hard mask layer is exposed ([col 2 line 59 – col 3 line 15], figure 3-4, after removing the portion of the bottom conductive layer #68 to form the recess on the bottom conductive layer #68 and in the trench. The dielectric layer #62 on the upper surface of the hard mask layer #58 is exposed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include wherein after removing the portion of the bottom conductive layer, the dielectric layer on the upper surface of the hard mask layer is exposed as taught by Lu in order improve electrical protection, increase the devices lifetime, and to reduce device failures.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Zhou (CN-107623034-B) in further view of Nakagawa et al. (KR-20120069779-A referred as Nakagawa).
Regarding claims 23. Kim as modified lacks wherein the second temperature is 470 C to 520 C.
Nakagawa discloses wherein the second temperature is 470 C to 520 C ([pg 8, paragraph 3 of Machine Translation], figure 7, the titanium alloy #12 is deposited on substrate #11 and annealed at a temperature of 500 C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include wherein the second temperature is 470 C to 500 C as taught by Nakagawa in order to reduce manufacturing costs, reduce energy consumed in manufacturing, and to provide an even surface from annealing.
Response to Arguments
Applicant's arguments filed 06/11/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding claim 1 on pages 10-11 of the arguments with respect to Nakagawa et al.. The examiner is no longer using Nakagawa et al. in the rejection above, therefore the argument is moot. Upon further search and consideration, a new rejection using a different interpretation of Kim et al. in combination with newly cited reference to Zhou has been presented with regard to claim 1.
Regarding the first deficiency on pages 10-11 of the arguments, the applicant states that the conductive layer 21a of Kim et al. can not be used as a bottom conductive layer since is used as a gate electrode. The examiner responds that the claim language asks for a bottom conductive layer, and the conductive layer 21a of Kim is made of tungsten which is a known conductive material. Therefore the conductive layer 21a of Kim could map as a bottom conductive layer from the claim language.
Regarding the second and third deficiency on pages 11-12 of the arguments, the applicant states how Kim et al. can not be combined with teaching in annealing parameters of temperature, time and atmosphere which is seen in the new prior art of Zhou. Although it is agreed that both arts are not the exact same invention, the claim language reads for annealing parameters which is what is being combined and is taught by the new reference to Zhou, not the entire invention, therefore the combination is proper.
Regarding claim 7 on pages 12-13 of the arguments with respect to Hori et al.. The examiner is no longer using Hori et al. in the rejection above, therefore the argument is moot. As seen in the new rejection above the combination of the amendment/change to the annealing time and the specified atmosphere was taught by the new reference to Zhou.
Allowable Subject Matter
Claims 11-12, 16-20, 22, and 24-26 allowed.
Regarding claim 11, the prior art does not teach or render obvious depositing a titanium nitride layer on the dielectric layer and in the first trench and the second trench at a first temperature of 350°C to 450°C; and performing an annealing process on the titanium nitride layer at a second temperature of 470 *C to 540 °C, wherein an annealing time is between 30 minutes to 100 minutes, and the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere and in the combination as claimed.
Claims 12, 16-20, 22, and 24-26 further limit allowable claim 11, therefore, are also allowable.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272 - 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. For questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACOB RAUL MARIN/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights