Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/25/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11, 23, and 25-56 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1) in view of Yeom et al. (US-20040013014-A1 referred as Yeom) and Nakagawa et al. (KR-20120069779-A referred as Nakagawa).
Regarding claim 1. Kim discloses a method of forming a semiconductor structure, comprising: forming a trench in a substrate ([0097], figure 4A, a trench #15 is formed in the substrate #11); forming a dielectric layer to cover an inner surface of the trench ([0099], figure 4B, the dielectric layer #17 is formed in the inner surface of the trench #15);
depositing a bottom conductive layer on the dielectric layer and in the trench ([0116], figure 4F, deposit the bottom conductive layer #21a on the dielectric layer #17 and in the trench #15);
removing a portion of the bottom conductive layer to form a recess on the bottom conductive layer and in the trench ([0118], figure 4G, the removal of a portion of the bottom conductive layer #21a forms a recess within the trench); and
forming a top conductive layer in the recess ([0138], figure 4N, forming a top conductive layer #25).
Kim lacks depositing a bottom conductive layer at a first temperature of 350 °C to 450 °C; and performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C wherein an annealing time is between 5 minutes to 100 minutes.
Yeom discloses depositing a bottom conductive layer at a first temperature of 350 °C to 450 °C ([0047], the deposition of titanium nitride layer (which is a conductive layer) at about 350 °C to 450 °C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include depositing a conductive layer at 350 °C to 450 °C as taught by Yeom in order to increase deposition control in uniform film thickness, quality, and oxidation.
Kim as modified by Yeom still lacks performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C, wherein an annealing time is between 5 minutes to 100 minutes.
Nakagawa discloses performing an annealing process on the bottom conductive layer at a second temperature of 470 °C to 540 °C, wherein an annealing time is between 5 minutes to 100 minutes ([pg 8, paragraph 3 of Machine Translation], figure 7, the titanium alloy (bottom conductive layer) #12 is deposited on substrate #11 and annealed at a temperature of 500 C with the annealing time of 10 minutes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified by Yeom to include annealing the conductive layer at a temperature of 500 °C (reading on the range of 470-540 °C) and annealing time of 10 minutes as taught by Nakagawa in order to enhance the elements hardness, reduce residual stress, and to improve overall performance.
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Regarding claim 11. Kim discloses a method of forming a semiconductor structure, comprising:
forming a first trench and a second trench in a substrate ([0099], figure 4B annotated above, the first trench #15a and the second trench #15b are formed in the substrate #11);
forming a dielectric layer to cover a first inner surface of the first trench and a second inner surface of the second trench ([0099], figure 4B annotated above, the dielectric layer #17 covers the first inner surface #17a in the first trench #15a and the second inner surface #17b in the second trench #15b);
depositing a titanium nitride layer on the dielectric layer and in the first trench and the second trench ([0118] [0045], figure 4G, the conductive layer #21 (part of #LB which may be titanium nitride) is seen on the dielectric layer #17 and in the first trench #15a and second trench #15b); and
Kim lacks depositing a titanium nitride layer at a first temperature of 350 °C to 450 °C; performing an annealing process on the titanium nitride layer at a second temperature of 470 C to 540 C, wherein an annealing time is between 5 minutes to 100 minutes.
Yeom discloses depositing a titanium nitride layer at a first temperature of 350 °C to 450 °C ([0047], the deposition of titanium nitride layer at about 350 °C to 450 °C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim to include depositing a titanium nitride layer at 350 °C to 450 °C as taught by Yeom in order to increase deposition control in uniform film thickness, quality, and oxidation.
Kim as modified by Yeom still lacks performing an annealing process on the titanium nitride layer at a second temperature of 470 C to 540 C, wherein an annealing time is between 5 minutes to 100 minutes.
Nakagawa discloses performing an annealing process on the titanium nitride layer at a second temperature of 470 C to 540 C, wherein an annealing time is between 5 minutes to 100 minutes ([pg 8, paragraph 3 of Machine Translation], figure 7, the titanium alloy #12 is deposited on substrate #11 and annealed at a temperature of 500 C with the annealing time of 10 minutes).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified by Yeom to include performing an annealing process on the titanium nitride layer at a second temperature of 500 C, wherein an annealing time of 10 minutes as taught by Nakagawa in order to increase deposition control in uniform film thickness, quality, and oxidation.
Regarding claim 2. Kim as modified discloses wherein the bottom conductive layer comprises titanium nitride ([0045], figure 4N, the bottom conductive layer #21 which is part of #LB may consist of titanium nitride).
Regarding claim 3. Kim as modified discloses wherein the top conductive layer comprises polysilicon ([0050], figure 4N, the top conductive layer #25 which is part of #UB may consists of polysilicon).
Regarding claims 23, 25, and 26. Kim as modified lacks
[claim 23 and claim 25] wherein the second temperature is 470 C to 520 C.
[claim 26] wherein the second temperature is 470 C to 500 C.
Nakagawa discloses
[claim 23 and claim 25] wherein the second temperature is 470 C to 520 C ([pg 8, paragraph 3 of Machine Translation], figure 7, the titanium alloy #12 is deposited on substrate #11 and annealed at a temperature of 500 C).
[claim 26] wherein the second temperature is 470 C to 500 C ([pg 8, paragraph 3 of Machine Translation], figure 7, the titanium alloy #12 is deposited on substrate #11 and annealed at a temperature of 500 C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include wherein the second temperature is 470 C to 500 C as taught by Nakagawa in order to reduce manufacturing costs, reduce energy consumed in manufacturing, and to provide a even surface from annealing.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa) in further view of Hori et al (US-20220059658-A1 referred as Hori).
Regarding claim 7. Kim as modified lacks wherein the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere.
Hori discloses wherein the annealing process is performed under an inert gas atmosphere or a nitrogen gas atmosphere ([0106], the annealing process is performed under an inert gas atmosphere).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the annealing time under an inert gas atmosphere by Hori in order to enhance ductility of materials, reduce hardness and to improve workability.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa) in further view of Tsai (US-20230197832-A1).
Regarding claim 8. Kim as modified lacks wherein the trench has a width of 12 nm to 30 nm.
Tsai discloses wherein the trench has a width of 12 nm to 30 nm ([0030], trenches #30 have a width from 20-30nm as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the trench has a width of 12 nm to 30 nm as taught by Tsai in order to enhance device performance, reduce unwanted electrical signal, and to improve reliability.
Claim 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa), in further view of Li (US-20230024465-A1).
Regarding claim 9. Kim as modified lacks wherein depositing the bottom conductive layer is performed by chemical vapor deposition or physical vapor deposition.
Li discloses wherein depositing the bottom conductive layer is performed by chemical vapor deposition or physical vapor deposition ([0033], figure 12, the bottom conductive layer #116 is formed by a physical vapor deposition as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the bottom conductive layer is performed by a physical vapor deposition as taught by Li in order to enhance purity in the element, increase durability and to allow corrosion resistance.
Regarding claim 10. Kim as modified lacks further comprising: before forming the trench in the substrate, forming a doped region in the substrate, wherein after forming the trench in the substrate, the trench penetrates through the doped region.
Li discloses further comprising: before forming the trench in the substrate, forming a doped region in the substrate, wherein after forming the trench in the substrate, the trench penetrates through the doped region ([0027], figure 4-5, the doped region #102 is formed to the substrate #100 and then formed with a trench #104 afterwards penetrating both the doped region #102 and substrate #100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include forming a doped region on a substrate and then forming a trench through both elements as taught by Li in order to enhance device performance, support for high density integration, and prevention of interference.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa), in further view of Varghese et al. (US-20200126926-A1 referred as Varghese).
Regarding claim 12. Kim as modified lacks wherein the first trench has a first top edge, the second trench has a second top edge adjacent to the first top edge, and a distance between the first top edge and the second top edge is 12 nm to 30 nm.
Varghese discloses wherein the first trench has a first top edge, the second trench has a second top edge adjacent to the first top edge, and a distance between the first top edge and the second top edge is 12 nm to 30 nm ([0042], figure 3, the first and second trenches #330 are spaced apart about 12-30nm in between the first top edge and second top edge).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the trenches being spaced apart by 12 nm to 30 nm as taught by Varghese in order to enhance device performance, reduce unwanted electrical signal, and to improve reliability.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa), in further view of Patlolla et al. (US-9859218-B1 referred as Patlolla).
Regarding claims 16. Kim as modified discloses further comprising:
forming a polysilicon layer on the titanium nitride layer and in the first trench and the second trench ([0137], figure 4L, forming a conductive layer #25a ([0050], which is part of #UB that consists of polysilicon) on the titanium nitride layer #21 in the first trench #15a and the second trench #15b); and
removing a portion of the polysilicon layer to expose the sidewall and the top surface of the dielectric layer ([0138], figure 4M, removing a portion of the polysilicon layer #25 to expose the sidewall and the top surface of the dielectric layer #17).
Kim as modified lacks after performing the annealing process on the titanium nitride layer, removing a portion of the titanium nitride layer to expose a sidewall and a top surface of the dielectric layer.
Patlolla discloses after performing the annealing process on the titanium nitride layer, removing a portion of the titanium nitride layer to expose a sidewall and a top surface of the dielectric layer ([(32)], figure 7, after performing the annealing process to the entire substrate device #10 (which includes the titanium nitride layer #24), the portion of the titanium nitride layer #24 is removed to expose a sidewall and top surface of the dielectric layer #12);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include removing a portion of the titanium nitride layer after the annealing process as taught by Patlolla in order to minimize pattern collapse, and reduce the aspect ratio for an enhanced device performance.
Regarding claim 17. Kim as modified discloses further comprising: after removing the portion of the polysilicon layer, forming an insulating capping layer to fill the first trench and the second trench ([0146], figure 4L-4M and figure 4O, after removing a portion of the polysilicon layer #25 ([0050], #UB includes #25), an insulating capping layer #26 is seen filling in the first trench #15a and the second trench #15b as marked by figure 4B annotated above).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa) in further view of Chen (US-20230131599-A1).
Regarding claim 18. Kim as modified lacks further comprising: before forming the first trench and the second trench in the substrate, forming a doped region in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench and the second trench penetrate through the doped region.
Chen discloses further comprising: before forming the first trench and the second trench in the substrate, forming a doped region in the substrate ([0016], figure 3, the doped region #204 is formed in the substrate #201), wherein after forming the first trench and the second trench in the substrate, the first trench and the second trench penetrate through the doped region ([0044], figure 12, the first and second trenches #240 are formed penetrating through the doped region #204).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include two trenches going through a doped region in a substrate as taught by Chen in order to distribute the device weight, increase manufacturing speed, and to increase device versatility.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), and Nakagawa et al. (KR-20120069779-A referred as Nakagawa) in further view of Takana et al. (US-20230112433-A1 referred as Takana).
Regarding claim 19. Kim as modified lacks wherein a first depth of the first trench is greater than a second depth of the second trench.
Takana discloses wherein a first depth of the first trench is greater than a second depth of the second trench ([0019], figure 4, the first depth of the first trench #122 is greater than the second depth of the second trench #121).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the first trench being deeper than the second trench as taught by Takana in order increase device performance, reduce leakage, and promote thermal performance.
Regarding claim 20. Kim as modified lacks further comprising: before forming the first trench and the second trench in the substrate, forming an isolation structure in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench penetrates into the isolation structure.
Takana discloses further comprising: before forming the first trench and the second trench in the substrate, forming an isolation structure in the substrate, wherein after forming the first trench and the second trench in the substrate, the first trench penetrates into the isolation structure ([0019], figure 2 and 4, the isolation feature #110 is first formed in the substrate #100 and then penetrated by the first trench #122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include the first trench being deeper than the second trench as taught by Takana in order improve device reliability, enhance electrical performance, and to reduce electrical interference.
Claims 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom) and Nakagawa et al. (KR-20120069779-A referred as Nakagawa) in further view of Tsai (US-20220059666-A1).
Regarding claim 21 and claim 24. Kim as modified lacks
[Claim 21] further comprising:
before forming the trench in the substrate, forming a hard mask layer on the substrate;
when forming the trench in the substrate, forming the trench to penetrate the hard mask layer; and
when forming the dielectric layer to cover the inner surface of the trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer.
[Claim 24] further comprising:
before forming the first trench and the second trench in the substrate,
forming a hard mask layer on the substrate;
when forming the first trench and the second trench in the substrate, forming the first trench and the second trench to penetrate the hard mask layer; and
when forming the dielectric layer to cover the first inner surface of the first trench and the second inner surface of the second trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer.
Tsai discloses
[Claim 21] further comprising:
before forming the trench in the substrate, forming a hard mask layer on the substrate ([0051], fig 2, before the trench is formed, a hard mask layer #105 is formed on the substrate #101);
when forming the trench in the substrate, forming the trench to penetrate the hard mask layer ([0069], figure 4, the trench in the substrate #101 is formed which also includes penetrating the hard mask layer #105); and
when forming the dielectric layer to cover the inner surface of the trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer ([0102-0104], figure 16, in another embodiment after steps figures 2-4 is seen forming the dielectric layer #201 to cover the inner surface of the trench and the upper surface of the hard mask layer #105).
[Claim 24] further comprising:
before forming the first trench and the second trench in the substrate, forming a hard mask layer on the substrate ([0051], fig 2, before the first and second trench is formed, a hard mask layer #105 is formed on the substrate #101);
when forming the first trench and the second trench in the substrate, forming the first trench and the second trench to penetrate the hard mask layer ([0069], figure 4, the first and second trench in the substrate #101 is formed which also includes penetrating the hard mask layer #105); and
when forming the dielectric layer to cover the first inner surface of the first trench and the second inner surface of the second trench, forming the dielectric layer to cover sidewalls and an upper surface of the hard mask layer ([0102-0104], figure 16, in another embodiment after steps figures 2-4 is seen forming the dielectric layer #201 to cover the inner surface of the first and second trench and the upper surface of the hard mask layer #105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include forming the dielectric layer on the inner trench and the upper surface of the hard mask as taught by Tsai in order improve electrical protection, increase the devices lifetime, and to reduce device failures.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US-20200395461-A1), Yeom et al. (US-20040013014-A1 referred as Yeom), Nakagawa et al. (KR-20120069779-A referred as Nakagawa), and Tsai (US-20220059666-A1) in further view of Lu et al. (US-7309632-B1 referred as Lu).
Regarding claim 22. Kim as modified lacks wherein after removing the portion of the bottom conductive layer to form the recess on the bottom conductive layer and in the trench, the dielectric layer on the upper surface of the hard mask layer is exposed.
Lu discloses wherein after removing the portion of the bottom conductive layer to form the recess on the bottom conductive layer and in the trench, the dielectric layer on the upper surface of the hard mask layer is exposed ([col 2 line 59 – col 3 line 15], figure 3-4, after removing the portion of the bottom conductive layer #68 to form the recess on the bottom conductive layer #68 and in the trench. The dielectric layer #62 on the upper surface of the hard mask layer #58 is exposed).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Kim as modified to include wherein after removing the portion of the bottom conductive layer, the dielectric layer on the upper surface of the hard mask layer is exposed as taught by Tsai in order improve electrical protection, increase the devices lifetime, and to reduce device failures.
Response to Arguments
Applicant's arguments filed 03/25/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
Regarding claims 1 and 11 on pages 9-12 of the arguments, Applicants amendments and arguments are persuasive. Upon further search and consideration, a new rejection using a different interpretation of Kim et al. in combination with newly cited reference to Tsai et al. has been presented with regard to claim 1 and 11.
Conclusion
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/JACOB RAUL MARIN/ Examiner, Art Unit 2818
/JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
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