Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2023 and 01/22/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Banerjee et al, US 20220415378 A1.
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Pertaining to claim1, Banerjee teaches ( see figs 2 and 4 above) An electronic fuse device, comprising: a first bit cell [290] comprising a first plurality of active regions [310-326 or 312-340] extending along a first direction;
and a second bit cell [292] comprising a second plurality of active regions [338-366 or 352-368] extending along the first direction, wherein each of the first plurality of active regions is aligned with one of the second plurality of active regions along the first direction, wherein the first bit cell [290] and the second bit cell [292] are spaced apart along the first direction by a space, wherein the space is free of a well tap cell ( see space in fig.2 between the two-bit cell).
Pertaining to claim 2, Banerjee teaches ( see figs 2 and 4 above)The electronic fuse device of claim 1, wherein the first plurality of active regions [310-326 or 312-340] are discontinuous with the second plurality of active regions [338-366 or 352-368].
Pertaining to claim 3, Banerjee teaches ( see figs 2 and 4 above)The electronic fuse device of claim 1, further comprising: at least one isolation gate structure [378,fig3 ] disposed between the first bit cell[290] and the second bit cell[292].
Pertaining to claim 4, Banerjee teaches ( see figs 2 and 4 above)The electronic fuse device of claim 3, wherein the at least one isolation gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, wherein the gate electrode comprises metal ( see para 0034 using metal gate on a gate insulating layer).
Pertaining to claim 5, Banerjee teaches ( see figs 2 and 4 above) the electronic fuse device of claim 1, further comprising: at least one grounded gate structure ( dummy gates) disposed between the first bit cell[290] and the second bit cell[290], wherein the at least one grounded gate structure is electrically coupled to a circuit ground (see para 0036 about these dummy gates such as 378 are connected to the ground reference VSS to disable the resulting transistor).
Allowable Subject Matter
Claims 9-16 allowed.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Banerjee et al, (US 20220415378 A1) teaches the limitation of “An electronic fuse device, comprising: a first bit cell comprising a first n-type transistor and a first p-type transistor; and a second bit cell comprising a second n-type transistor and a second p-type transistor”, but it does not teach or suggest, singularly or in combination, at least the limitations of the independent claim 9 including “wherein the first n-type transistor is disposed over a first p-type well, wherein the first p-type transistor is disposed over a first n-type well , wherein the first p-type well is insulated from the first n-type well, wherein the second n-type transistor is disposed over a second p-type well, wherein the second p-type transistor is disposed over a second n-type well, wherein the second p-type well is insulated from the second n-type well. ”
it does not also teach or suggest, singularly or in combination, at least the limitations of the independent claim 17 including “a first bit cell comprising a first complementary metal oxide semiconductor (CMOS) device; and a second bit cell comprising a second CMOS device, wherein the first CMOS device comprises: a first n-type transistor over a first p-type well, a first p-type transistor over a first n-type well, wherein the first p-type well is insulated from the first n-type well by an isolation structure, wherein the first bit cell and the second bit cell are spaced apart by a space, wherein the space is free of a well tap cell. “
Claims 6-8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for allowance: The closest prior art of record of Banerjee et al, (US 20220415378 A1) teaches the limitation of claim1, but it does not teach or suggest, singularly or in combination, at least the limitations of the dependent claim 6 including “further comprising: a backside interconnect structure below the first bit cell and the second bit cell; and a frontside interconnect structure over the first bit cell and the second bit cell” in combination with the remaining limitations of the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
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/MAMADOU L DIALLO/Primary Examiner, Art Unit 2897