Prosecution Insights
Last updated: October 02, 2026
Application No. 18/488,910

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103
Filed
Oct 17, 2023
Priority
Oct 25, 2022 — RE 10-2022-0138608
Examiner
CAMPBELL, SHAUN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
770 granted / 1058 resolved
+4.8% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
31 currently pending
Career history
1089
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
25.2%
-14.8% vs TC avg
§112
12.9%
-27.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1058 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Amendment, received 8/4/2026, has been entered. Claims 1-11 are elected for examination and claims 12-20 are withdrawn from consideration. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. No. 2022/0131045 A1), hereafter referred to as Lee, in view of Sakariya et al. (US Pub. No. 2014/0159064 A1), hereafter referred to as Sakariya. As to claim 1, Lee discloses a display device (figs 7-9; [0043]), comprising: a first electrode (fig 9, EL1) above a surface of a substrate (SUB); light-emitting elements (LD1, LD2, LD3) comprising: a first end portion (bottom portion of 16) above, contacting, and electrically connected to, the first electrode (EL1); a second end portion (top end portion) opposite to the first end portion (bottom portion of 16) with respect to a direction that is perpendicular to the surface of the substrate (SUB); a bonding electrode (16); a second layer (15); an active layer (13; [0059]); a first layer (12); and a third layer (11) having conductivity by doping an impurity into an intrinsic semiconductor layer ([0061]; n-type semiconductor layer 11 includes n-type impurities); an intermediate layer (INS1) over the light-emitting elements (LD), and exposing the second end portion (top end portion); and a second electrode (EL2) above the intermediate layer (INS1), and contacting and electrically connected to the second end portion (top end portion of LD). Lee does not disclose wherein the second layer, the active layer, the first layer, and the third layer have a same diameter, which is greater than a diameter of the bonding electrode. Nonetheless, Sakariya discloses a similar display structure including a micro-LED with straight sidewalls or tapered sidewalls ([0144]) and including a diameter which is greater than a diameter of a bonding electrode (fig 5A, diameter of micro-LED 450 is greater than diameter of bonding electrode 420; [0145]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the micro-LED of Lee with any one of outwardly tapered sidewalls, inwardly tapered sidewalls or straight sidewalls with a diameter greater than that of a bonding electrode as taught by Sakariya as a matter of design choice that one of ordinary skill in the art would choose based on the manufacturing elements of the diode. As to claim 2, Lee in view of Sakariya disclose the display device of claim 1 (paragraphs above). Lee further discloses wherein the bonding electrode (16) is at the first end portion (bottom end portion), and electrically connected to the first electrode (EL1), and wherein the third layer (11) is at the second end portion (top end portion), and electrically connected to the second electrode (EL2). As to claim 3, Lee in view of Sakariya disclose the display device of claim 2 (paragraphs above). Lee further discloses wherein the first layer comprises an n-type semiconductor layer, and the second layer comprises a p-type semiconductor layer ([0065]-[0066]). As to claim 4, Lee in view of Sakariya disclose the display device of claim 3 (paragraphs above). Lee further discloses wherein the intermediate layer comprises an organic layer ([0169]). As to claim 5, Lee in view of Sakariya disclose the display device of claim 4 (paragraphs above). Lee further discloses a first bank (BNK) defining an opening (EMA) above the first electrode (EL1) to expose an area of the first electrode (EL1); and a cover layer (CTL) above the second electrode (EL2). As to claim 6, Lee in view of Sakariya disclose the display device of claim 5 (paragraphs above). Lee further discloses wherein the intermediate layer (INS1) is between the first bank (BNK) and the light-emitting elements (LD) in the opening of the first bank in plan view, thereby fixing the light-emitting elements (LD), and has a flat surface (flat surface of INS1). As to claim 7, Lee in view of Sakariya disclose the display device of claim 5 (paragraphs above). Lee further discloses a color conversion layer (LCP) comprising a color conversion pattern (CCL1) above the cover layer (CTL) and corresponding to the light-emitting elements (LD), and a second bank (LBP1) adjacent to the color conversion pattern (CCL1), above the cover layer (CTL), and corresponding to the first bank (BNK); and a color filter layer (CF1) above the color conversion layer (CCL1), and configured to selectively transmit light emitted from the color conversion layer ([0189]). As to claim 8, Lee in view of Sakariya disclose the display device of claim 1 (paragraphs above). Lee does not disclose a conductive pattern between the first electrode and the first end portion of the light-emitting elements. Nonetheless, Sakariya discloses a conductive pattern (fig 3W, 132) between a first electrode (116) and a first end portion (bottom portion) of light-emitting elements (400). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the conductive pattern of Sakariya in the display device of Lee since this will improve the light emission efficiency of the pixels by improving reflection of the pixel emission region. As to claim 9, Lee discloses a display device (figs 7-9; [0043]) comprising: a substrate (SUB) comprising an emission area (EMA) and a non-emission area (NEMA); a passivation layer (PSV) above a surface of the substrate (SUB); a (1-1)th electrode, a (1-2)th electrode, and a (1-3)th electrode (electrodes EL1 corresponding to PXL1-3) above the passivation layer (PSV), and spaced apart (spaced apart pixel electrodes EL1 for PXL1-3); a first bank (BNK) above the (1-1)th electrode, the (1-2)th electrode, the (1-3)th electrode (EL1), and the passivation layer (PSV), and defining an opening exposing respective areas of the (1-1)th electrode, the (1-2)th electrode, and the (1-3)th electrode (openings in BNK); first light-emitting elements (LD1) comprising a first end portion (16) above, contacting, and electrically connected to the (1-1)th electrode (EL1), and a second end portion (top portion) opposite to the first end portion in a direction perpendicular to the surface of the substrate (SUB); second light-emitting elements (LD2) comprising a first end portion (16) above, contacting, and electrically connected to the (1-2)th electrode (EL1), and a second end portion (top) opposite to the first end portion in the direction perpendicular to the surface of the substrate (SUB); third light-emitting elements (LD3) each comprising a first end portion (16) above, contacting, and electrically connected to the (1-3)th electrode (EL1), and a second end portion (top portion) opposite to the first end portion in the direction perpendicular to the surface of the substrate (SUB); an intermediate layer (INS1) over the first light-emitting elements (LD), the second light-emitting elements (LD), the third light-emitting elements (LD), and the first bank (BNK), and exposing the second end portions (top portion) of the first light-emitting elements, the second light-emitting elements, and the third light-emitting elements (LDs); and a second electrode (EL2) above the intermediate layer (INS1), contacting the second end portions of the first light-emitting elements (LD1), the second light-emitting elements (LD2), and the third light-emitting elements (LD3), and electrically connected to the first light-emitting elements, the second light-emitting elements, and the third light-emitting elements ([0116]), wherein the first light-emitting elements (LD1), the second light-emitting elements (LD2), and the third light-emitting elements (LD3) comprise a bonding electrode (16), a second layer (15), an active layer (13), a first layer (12), and a third layer (11), which has conductivity by doping an impurity into an intrinsic semiconductor layer ([0061]; n-type semiconductor layer 11 includes n-type impurities), that are sequentially arranged toward the second electrode (EL2). Lee does not disclose wherein the second layer, the active layer, the first layer, and the third layer have a same diameter, which is greater than a diameter of the bonding electrode. Nonetheless, Sakariya discloses a similar display structure including a micro-LED with straight sidewalls or tapered sidewalls ([0144]) and including a diameter which is greater than a diameter of a bonding electrode (fig 5A, diameter of micro-LED 450 is greater than diameter of bonding electrode 420; [0145]). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the micro-LED of Lee with any one of outwardly tapered sidewalls, inwardly tapered sidewalls or straight sidewalls with a diameter greater than that of a bonding electrode as taught by Sakariya as a matter of design choice that one of ordinary skill in the art would choose based on the manufacturing elements of the diode. As to claim 10, Lee in view of Sakariya disclose the display device of claim 9 (paragraphs above). Lee further discloses wherein the bonding electrode (16) is at the first end portion (bottom portion), and is electrically connected to a respective one of the (1-1)th electrode, the (1-2)th electrode, and the (1-3)th electrode (EL1), and wherein the third layer (11) is at the second end portion (top portion), and is electrically connected to the second electrode (EL2). As to claim 11, Lee in view of Sakariya disclose the display device of claim 9 (paragraphs above). Lee further discloses wherein the first layer comprises an n-type semiconductor layer, and the second layer comprises a p-type semiconductor layer ([0065]-[0066]). Response to Arguments Applicant's arguments filed 8/4/2026 have been fully considered but they are not persuasive. Applicant argued that Lee does not anticipate the amended claim limitations. Examiner agrees, however, the claims are obvious based on Lee in view of Sakariya. Applicant argued that Sakariya does not appear to cure the deficiencies of Lee to teach or suggest the abovementioned features of claim 1 and 9. Examiner disagrees because Sakariya teaches in figure 5A and paragraphs [0144]-[0145] that a micro-LED for a display device may include sidewalls that are either inwardly tapered, outwardly tapered or straight while having a bonding electrode that has a diameter such that the amended claim limitations are obvious with respect to Lee in view of Sakariya, as presented in the office action above. Pertinent Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 8,987,765 B2. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 8/26/2026
Read full office action

Prosecution Timeline

Oct 17, 2023
Application Filed
May 13, 2026
Non-Final Rejection mailed — §103
Aug 04, 2026
Response Filed
Aug 31, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
81%
With Interview (+8.6%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1058 resolved cases by this examiner. Grant probability derived from career allowance rate.

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