Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-16 and claims 21-24, in the reply filed on 05/11/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) in view of Godinho et al. (US-5124774-A referred as Godinho).
Regarding claim 1. Lin discloses a memory cell, comprising:
first and second active regions, wherein each of the first and second active regions extends lengthwise in a first direction ([0039], figure 3a, first active region #322 and second active region #324 extend in a first direction (vertical));
first and second gate structures, wherein each of the first and second gate structures extends lengthwise in a second direction that is perpendicular to the first direction ([0039], figure 3a, first gate structure #332 and second gate structure #334 extend in a second direction (horizontal)), the first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull- up transistor, respectively ([0040], figure 3a, the first gate structure #332 engages first active region #322 and second active region #324 in forming a first pulldown transistor #114a and a first pullup transistor #114b, respectively), and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively ([0040], figure 3a, the second gate structure #334 engages first active region #322 and second active region #324 in forming a second pulldown transistor #124a and a second pullup transistor #124b, respectively);
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a first frontside source/drain contact disposed above and electrically coupled to a first common source/drain region of the first and second pull-down transistors, wherein the first common source/drain region is disposed on the first active region (figure 3a/3b annotated above, as described in [0041], the first common source region #328a of the first and second pulldown transistors #114a/124a is illustrated. Figure 3b, and as described in [0043], illustrates a usable first frontside source contact #357a disposed above the first active region #322 which could be electrically coupled to the first common source region #328a).
Lin lacks a first backside via disposed under and electrically coupled to the first common source/drain region; and
a first backside metal line disposed under and electrically coupled to the first backside via.
Godinho discloses a first backside via disposed under and electrically coupled to the first common source/drain region ([col 5 lines 24-34], figure 5, a first backside via #37 disposed under and electrically coupled to the first common source region #36 of the pulldown transistors #30a/30b); and
a first backside metal line disposed under and electrically coupled to the first backside via ([col 5 lines 51-56], figure 6a shows a further illustration of a first backside metal line #43a disposed under and coupled to the first backside via #37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to have a first backside via and a first backside metal line as taught by Godinho in order to enhance device versatility, increase the devices integrity, and to extend the devices lifetime.
Regarding claim 2. Lin as modified lacks wherein the first backside via electrically couples to an electrical ground of the memory cell.
Godinho discloses wherein the first backside via electrically couples to an electrical ground of the memory cell ([col 5 lines 24-34], figure 5, the first backside via #37 is coupled to an electrical ground, as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to have wherein the first backside via electrically couples to an electrical ground of as taught by Godinho in order to enhance device versatility, increase the devices integrity, and to extend the devices lifetime.
Regarding claim 3. Lin as modified lacks wherein a width of the first backside via measured in the second direction equals a width of the first active region measured in the second direction.
MPEP 2144.04 IV A - describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Lin as modified to include wherein a width of the first backside via measured in the second direction equals a width of the first active region measured in the second direction in order to distribute the overall weight of the device, improve device reliability, and potentially reduce stress concentrations.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) and Godinho et al. (US-5124774-A referred as Godinho) in further view of Sinha et al. (US-20240107738-A1 referred as Sinha).
Regarding claim 4. Lin as modified lacks wherein an edge of the first backside metal line aligns with an edge of the first active region.
Sinha discloses wherein an edge of the first backside metal line aligns with an edge of the first active region ([0095], figure 10, the edge of the first backside metal line #120b aligns with an edge of the first active region #114).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein an edge of the first backside metal line aligns with an edge of the first active region as taught by Sinha in order to enhance device versatility, increase the devices integrity, and to extend the devices lifetime.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) and Godinho et al. (US-5124774-A referred as Godinho) in further view of Xian et al. (US-20220375920-A1 referred as Xian).
Regarding claim 5. Lin as modified lacks wherein the first backside metal line partially overlaps with the first active region in a top view of the memory cell.
Xian discloses wherein the first backside metal line partially overlaps with the first active region in a top view of the memory cell ([0053-0054], figure 3B, the first backside metal line #348 partially overlaps with the first active region #332).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside metal line partially overlaps with the first active region in a top view as taught by Xian in order to simplify the device design, increase the devices integrity, and to extend the devices lifetime.
Claim 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) and Godinho et al. (US-5124774-A referred as Godinho) in further view of Hsu et al. (US-20160322366-A1 referred as Hsu).
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Regarding claim 6. Lin as modified discloses a second frontside source/drain contact disposed above and electrically coupled to a second common source/drain region of the first and second pull-up transistors, wherein the second common source/drain region is disposed on the second active region (figure 3a/3b annotated above, as described in [0041], the second common source region #328b of the first and second pullup transistors #114b/124b is illustrated. Figure 3b, and as described in [0043], illustrates a usable second frontside source contact #357b disposed above the second active region #324 which could be electrically coupled to the second common source region #328b).
Lin as modified lacks a second backside via disposed under and electrically coupled to the second common source/drain region; and a second backside metal line disposed under and electrically coupled to the second backside via.
Hsu discloses a second backside via disposed under and electrically coupled to the second common source/drain region ([0021-0022], figure 1 flipped horizontally, shows first pull up transistors #12 (part of gate structure #56) and second pull up transistor #14 (part of gate structure #58) which have a second common source region #78 as shown and illustrated in figure 2. A second backside via #62 is disposed under and coupled to the second common source region #78); and a second backside metal line disposed under and electrically coupled to the second backside via ([0094], figure 5, a second backside metal line #66 is disposed under and coupled to the second backside via #62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include a second backside metal line and a second backside via as taught by Hsu in order to enhance the devices versatility, distribute circuitry across the device, and to extend the devices lifetime.
Regarding claim 7. Lin as modified lacks wherein the first backside metal line electrically couples to an electrical ground of the memory cell, and the second backside metal line electrically couples to a power voltage of the memory cell.
Godinho discloses wherein the first backside metal line electrically couples to an electrical ground of the memory cell ([col 5 lines 24-34], figure 5, the first backside metal line #43a is coupled to an electrical ground from #37, as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to have wherein the first backside metal line electrically couples to an electrical ground of the memory cell as taught by Godinho in order to enhance device versatility, increase the devices integrity, and to extend the devices lifetime
Lin as modified by Godinho still lacks wherein the second backside metal line electrically couples to a power voltage of the memory cell.
Hsu discloses wherein the second backside metal line electrically couples to a power voltage of the memory cell ([0022], figure 2 and figure 4, the first backside via #62 is electrically coupled to the voltage source #32 as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to include wherein the second backside metal line electrically couples to a power voltage of the memory cell as taught by Hsu in order to enhance the devices versatility, distribute circuitry across the device, and to extend the devices lifetime.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin), Godinho et al. (US-5124774-A referred as Godinho), and Hsu et al. (US-20160322366-A1 referred as Hsu) in further view of Xiong et al. (US-20170338361-A1 referred as Xiong).
Regarding claim 8. Lin as modified lacks wherein the first backside metal line and the second backside metal line have different widths.
Xiong discloses wherein the first backside metal line and the second backside metal line have different widths ([0040], figure 13, the first backside metal line #006 and the second backside metal line #007 have different widths as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside metal line and the second backside metal line have different widths as taught by Xiong in order to distribute weight across the device, reduce manufacturing materials, and to allow for versatile designs.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) in view of Hsu et al. (US-20160322366-A1 referred as Hsu).
Regarding claim 9. Lin discloses a memory cell, comprising:
first and second active regions, wherein each of the first and second active regions extends lengthwise in a first direction ([0039], figure 3a, first active region #322 and second active region #324 which extend in a first (vertical) direction);
first and second gate structures, wherein each of the first and second gate structures extends lengthwise in a second direction that is perpendicular to the first direction ([0039], figure 3a, first gate structure #332 and second gate structure #334 extend in a second (horizontal) direction), the first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull- up transistor, respectively ([0040], figure 3a, the first gate structure #332 engages in the first active region #322 and second active region #324 in forming a first pulldown transistor #114a and a first pullup transistor #114b, respectively), and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively ([0040], figure 3a, the second gate structure #334 engages in the first active region #322 and second active region #324 in forming a second pulldown transistor #124a and a second pullup transistor #124b, respectively);
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a first frontside source/drain contact disposed above and electrically coupled to a first common source/drain region of the first and second pull-up transistors, wherein the first common source/drain region is disposed on the second active region ([0041], figure 3a/3b annotated above, the first common source region #328b is seen on the second active region #324 as illustrated due to the inner portion #328 having source terminals from the first and second pullup transistor #114b/124b. and a first frontside source contact #357b is disposed above and coupled to the first common source region #328b).
Lin lacks a first backside via disposed under and electrically coupled to the first common source/drain region; and a first backside metal line disposed under and electrically coupled to the first backside via.
Hsu discloses a first backside via disposed under and electrically coupled to the first common source/drain region; and a first backside metal line disposed under and electrically coupled to the first backside via ([0021-0022], figure 1 flipped horizontally, shows first pull up transistors #12 (part of gate structure #56) and second pull up transistor #14 (part of gate structure #58) which have a first common source region #78 as shown and illustrated in figure 2. A first backside via #62 is disposed under and coupled to the first common source region #78. And a first backside metal line #66 is disposed under and coupled to the first backside via #66).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to have wherein the first backside via first backside metal line connected to the first common region as taught by Hsu in order to increase circuit versatility, enhance the integrity of the device, and also allow for consistent connectivity.
Regarding claim 10. Lin as modified lacks wherein the first backside via electrically couples to a power voltage of the memory cell.
Hsu discloses wherein the first backside via electrically couples to a power voltage of the memory cell ([0022], figure 2 and figure 4, the first backside via #62 is electrically coupled to the voltage source #32 as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside via electrically couples to a power voltage of the memory cell as taught by Hsu in order to increase circuit versatility, allow for a consistent power source, and to reduce device failure.
Regarding claim 11. Lin as modified lacks wherein a width of the first backside via measured in the second direction equals a width of the second active region measured in the second direction.
MPEP 2144.04 IV A - describes changes in size/proportion - In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" were held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.). In Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
It would have been obvious to one of ordinary skill in the art at the time of filing to have further modified for Lin as modified to include wherein a width of the first backside via measured in the second direction equals a width of the first active region measured in the second direction in order to distribute the overall weight of the device, improve device reliability, and potentially reduce stress concentrations.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) and Hsu et al. (US-20160322366-A1 referred as Hsu) in further view of Sinha et al. (US-20240107738-A1 referred as Sinha).
Regarding claim 12 and claim 13. Lin as modified lacks
[claim 12] wherein an edge of the first backside metal line aligns with an edge of the second active region.
[claim 13] wherein the first backside metal line partially overlaps with the second active region in a top view of the memory cell.
Sinha discloses
[claim 12] wherein an edge of the first backside metal line aligns with an edge of the second active region ([0071], figure 1, the edge of the first backside metal line #112c aligns with an edge of the second active region #104).
[claim 13] wherein the first backside metal line partially overlaps with the second active region in a top view of the memory cell ([0071], figure 1, the first backside metal line #112c partially overlaps the second active region #104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to further modify the position of the first backside metal line in reference to the second active region as taught by Sinha in order to have a compact device, reduce total weight of device, and to simplify the designing process.
Claims 14-15 rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) and Hsu et al. (US-20160322366-A1 referred as Hsu) in further view of Godinho et al. (US-5124774-A referred as Godinho).
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Regarding claim 14. Lin as modified discloses a second frontside source/drain contact disposed above and electrically coupled to a second common source/drain region of the first and second pull-down transistors, wherein the second common source/drain region is disposed on the first active region ([0041], figure 3a/3b annotated above, the second common source region #328a is seen on the first active region #322 as illustrated due to the inner portion #328 having source terminals from the first and second pulldown transistor #114a/124a. and a second frontside source contact #357a is disposed above and coupled to the second common source region #328b).
Lin as modified lacks a second backside via disposed under and electrically coupled to the second common source/drain region; and a second backside metal line disposed under and electrically coupled to the second backside via.
Godinho discloses a second backside via disposed under and electrically coupled to the second common source/drain region ([col 5 lines 24-34], figure 5, a second backside via #37 is disposed under and electrically coupled to the second common source region #36 of the pulldown transistors #30a/30b); and a second backside metal line disposed under and electrically coupled to the second backside via ([col 6 lines 42-56], figure 6a, the second backside metal line #43a is disposed under and coupled to the second backside via #37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to further include a second backside via and a second backside metal line as taught by Godinho in order to have a compact device, reduce total weight of device, and to allow additional control of the circuit.
Regarding claim 15. Lin as modified lacks wherein the first backside metal line electrically couples to a power voltage of the memory cell, and the second backside metal line electrically couples to an electrical ground of the memory cell.
Hsu discloses wherein the first backside metal line electrically couples to a power voltage of the memory cell ([0022], figure 2 and figure 4, the first backside metal line #66 is electrically coupled to the voltage source #32 as described through the first backside via #62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside metal line electrically couples to a power voltage of the memory cell as taught by Hsu in order to increase circuit versatility, allow for a consistent power source, and to reduce device failure.
Lin as modified by Hsu still lacks the second backside metal line electrically couples to an electrical ground of the memory cell.
Godinho discloses the second backside metal line electrically couples to an electrical ground of the memory cell ([col 6 lines 42-56], figure 6a, the second backside metal line #43a is electrically connected to the second backside via #37 which is connected to the ground).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified by Hsu to have wherein the first backside metal line electrically couples to a power voltage of the memory cell as taught by Godinho in order to increase circuit versatility, allow for a consistent power source, and to reduce device failure.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin), Hsu et al. (US-20160322366-A1 referred as Hsu), and Godinho et al. (US-5124774-A referred as Godinho) as applied to claim 14 in further view of Figueroa et al. (US-6346743-B1 referred as Figueroa).
Regarding claim 16. Lin as modified lacks a first frontside source/drain contact via disposed above and electrically coupled to the first frontside source/drain contact, wherein the first frontside source/drain contact via and the first backside via have no overlapping portions in a top view of the memory cell.
Figueroa discloses a first frontside source/drain contact via disposed above and electrically coupled to the first frontside source/drain contact, wherein the first frontside source/drain contact via and the first backside via have no overlapping portions in a top view of the memory cell ([col 6, lines 57-65], figure 2b, a first frontside source contact via #231 is electrically coupled to the first backside via #254 have no overlapping portions in a topview of the memory cell).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein a first frontside source/drain contact via disposed above and electrically coupled to the first frontside source/drain contact as taught by Figueroa in order to reduce future circuit failure, enhance the devices integrity, and to distribute weight across the device.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin) in view of Godinho et al. (US-5124774-A referred as Godinho) and Hsu et al. (US-20160322366-A1 referred as Hsu).
Regarding claim 21. Lin discloses memory cell, comprising:
first and second active regions, wherein each of the first and second active regions extends lengthwise in a first direction ([0039], figure 3a, first active region #322 and second active region #324 which extend in a first (vertical) direction);
first and second gate structures, wherein each of the first and second gate structures extends lengthwise in a second direction that is different from the first direction ([0039], figure 3a, first gate structure #332 and second gate structure #334 extend in a second (horizontal) direction), the first gate structure engages the first and second active regions in forming a first pull-down transistor and a first pull- up transistor, respectively ([0040], figure 3a, the first gate structure #332 engages in the first active region #322 and second active region #324 in forming a first pulldown transistor #114a and a first pullup transistor #114b, respectively), and the second gate structure engages the first and second active regions in forming a second pull-down transistor and a second pull-up transistor, respectively ([0040], figure 3a, the second gate structure #334 engages in the first active region #322 and second active region #324 in forming a second pulldown transistor #124a and a second pullup transistor #124b, respectively).
Lin lacks a first backside via disposed under and electrically coupled to a first common source/drain region of the first and second pull-down transistors, wherein the first common source/drain region is disposed on the first active region;
a first backside metal line disposed under and electrically coupled to the first backside via;
a second backside via disposed under and electrically coupled to a second common source/drain region of the first and second pull-up transistors, wherein the first common source/drain region is disposed on the second active region; and
a second backside metal line disposed under and electrically coupled to the second backside via.
Godinho discloses a first backside via disposed under and electrically coupled to a first common source/drain region of the first and second pull-down transistors, wherein the first common source/drain region is disposed on the first active region ([col 5 lines 24-34], figure 5, a first backside via #37 disposed under and electrically coupled to the first common source region #36 that’s within the first active region of the pulldown transistors #30a/30b);
a first backside metal line disposed under and electrically coupled to the first backside via ([col 5 lines 51-56], figure 6a shows a further illustration of a first backside metal line #43a disposed under and coupled to the first backside via #37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin to have a first backside via and a first backside metal line as taught by Godinho in order to enhance device versatility, increase the devices integrity, and to extend the devices lifetime.
Lin as modified by Godinho still lacks a second backside via disposed under and electrically coupled to a second common source/drain region of the first and second pull-up transistors, wherein the first common source/drain region is disposed on the second active region; and
a second backside metal line disposed under and electrically coupled to the second backside via.
Hsu discloses a second backside via disposed under and electrically coupled to a second common source/drain region of the first and second pull-up transistors, wherein the first common source/drain region is disposed on the second active region; and
a second backside metal line disposed under and electrically coupled to the second backside via ([0021-0022], figure 1 flipped horizontally, shows first pull up transistors #12 (part of gate structure #56) and second pull up transistor #14 (part of gate structure #58) which have a second common source region #78 as shown and illustrated in figure 2. Please note the second common source region #78 is disposed within the active region #54. A second backside via #62 is disposed under and coupled to the second common source region #78. And a second backside metal line #66 is disposed under and coupled to the second backside via #62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified by Godinho to have wherein the second backside via first backside metal line connected to the second common region as taught by Hsu in order to increase circuit versatility, enhance the integrity of the device, and also allow for consistent connectivity.
Claim 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin), Godinho et al. (US-5124774-A referred as Godinho), and Hsu et al. (US-20160322366-A1 referred as Hsu) as applied to claim 21 in further view of Kim et al. (US-20230039507-A1 referred as Kim).
Regarding claim 22. Lin as modified lacks a first frontside source/drain contact disposed above and electrically coupled to the first common source/drain region; and a second frontside source/drain contact disposed above and electrically coupled to the second common source/drain region.
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Kim discloses a first frontside source/drain contact disposed above and electrically coupled to the first common source/drain region ([0110], figure 9b annotated above, a first source contact #Cn1 is disposed and electrically coupled to the first common source region #CACT1); and a second frontside source/drain contact disposed above and electrically coupled to the second common source/drain region ([0110], figure 9b annotated above, a second source contact #Cn2 is disposed and electrically coupled to the second common source region #CACT2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first and second frontside contact is connected to the first and second common source region, respectively, as taught by Kim in order to increase circuit versatility, extend the devices lifetime, and to reduce short circuits.
Regarding claim 23. Lin as modified lacks wherein the first backside metal line and the second backside metal line have a same width measured in the second direction.
Kim discloses wherein the first backside metal line and the second backside metal line have a same width measured in the second direction ([0110], figure 9b annotated above, the first backside metal line #wire1 andt ehe second backside metal line #wire2 have the same width when measured in the second direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside metal line and the second backside metal line have a same width measured in the second direction as taught by Kim in order to enhance the devices integrity, simplify the device design, and to reduce manufacturing material.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US-20130242644-A1 referred as Lin), Godinho et al. (US-5124774-A referred as Godinho), and Hsu et al. (US-20160322366-A1 referred as Hsu) as applied to claim 21 in further view of Chung et al. (US-20240251541-A1 referred as Chung).
Regarding claim 24. Lin as modified lacks wherein the first backside metal line and the second backside metal line have different widths measured in the second direction.
Chung discloses wherein the first backside metal line and the second backside metal line have different widths measured in the second direction ([0073], figure 3e, the first backside metal line #MD1 and the second backside metal line #MD4 have different widths when viewed in the second direction #Z).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Lin as modified to have wherein the first backside metal line and the second backside metal line have a same width measured in the second direction as taught by Chung in order to enhance the devices integrity, simplify the device design, and to reduce manufacturing material.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Liaw (US-20250048610-A1) and Wang et al. (US-20240306359-A1) for teaching the pull up transistors, pull down transitors, and active regions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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