DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group (II) and Species (B and C), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10 February 2026.
Applicant’s election without traverse of Group (I) and Species (A) in the reply filed on 10 February 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 18 October 2023 and 6 April 2025 have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Srinivas Pulugurtha et al. (US 2015/0243748 A1; hereinafter “Pulugurtha”).
Regarding Claim 1, Pulugurtha teaches a semiconductor device, comprising:
a bit line (102a, Fig. 1I, para [0022] describes wherein a lower region 102a of a semiconductor base 102 may serve as a buried digit line);
a source on the bit line (102a, Fig. 1I, para [0022] describes wherein a lower region 102a of a semiconductor base 102 may serve as both a source region and a buried digit line wherein the source region would be on the bit line in the same lower region 102);
a body on the source (102b, Fig. 1I, para [0022] describes a p-type region 102b above the lower body region 102a comprising the source wherein the upper p-type region 102b is on the source region 102a);
a channel on the body (146, Fig. 1I, para [0051] describes wherein a channel region 146 overlies the lower body region 102b);
a drain on the channel (144, Fig. 1I, para [0051] describes wherein a drain region vertically overlies the channel region 146);
a word line surrounding and spaced apart from the channel (118, Fig. 1I, para [0030] describes gate electrodes 118 surrounding and spaced apart from the channel 146 by gate dielectric material 116 and para [0030] further describes wherein gate electrodes 118 may serve as word lines); and
a first body contact on the body, wherein the first body contact and the source are separated by the body (FBC and 154, annotated Fig 1I, para [0059] describes body contacts 154 on the body region 102b wherein first body contact FBC is on the body 102b and is separated from source region 102a by the body region 102b).
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Regarding Claim 2, Pulugurtha teaches the semiconductor device of claim 1, wherein the first body contact is adjacent to a first side of the channel (FBC and C, annotated Fig. 1I depicts wherein first body contact FBC is adjacent to a first side of the channel facing the gate dielectric layer 116).
Regarding Claim 3, Pulugurtha teaches the semiconductor device of claim 2, further comprising a second body contact adjacent to a second side of the channel (SBC and C, annotated Fig. 1I, depicts wherein a second body contact SBC is adjacent to a second side of the channel facing the second body contact SBC), wherein the second side is opposite to the first side (annotated Fig. 1I depicts wherein the first side, to the left of the channel when looking at annotated Fig. 1I is on an opposite side of the channel C than the second side which is to the right of the channel when looking at annotated Fig. 1I).
Regarding Claim 5, Pulugurtha teaches the semiconductor device of claim 1, further comprising a dielectric layer extending from a sidewall of the drain (116, Fig 1I, para [0028] describes a gate dielectric layer 116 which extends from a sidewall of the drains 144), passing through a sidewall of the channel (116, Fig. 1I, para [0028] describes wherein the dielectric layer 116 passes through a sidewall of the semiconductor pillars comprising channels 146) and a top surface of the body, to the first body contact (116 and 102b, annotated Fig. 1I, para [0028] describes wherein dielectric layer passes through a top surface of the base region 102b and extends to a height of the lower surface of the first body contact 154).
Regarding Claim 6, Pulugurtha teaches the semiconductor device of claim 5, further comprising an isolation structure surrounding the first body contact and in contact with the dielectric layer (124’, annotated Fig. 1I, para [0048] describes isolation structures 124’ wherein isolation structures 124’ surround both sides of first body contact FBC and are in contact with the dielectric layer 116).
Regarding Claim 8, Pulugurtha teaches the semiconductor device of claim 1, wherein a bottom surface of the first body contact is level with a bottom surface of the channel (FBC and C, annotated Fig. 1I depicts wherein a bottom surface of the first body contact FBC is level with a bottom surface of the channel C wherein both bottom surfaces are level with an upper surface of the body region 102b).
Regarding Claim 10, Pulugurtha teaches the semiconductor device of claim 1, further comprising a terminal on the first body contact (154 and FBC, annotated Fig. 1I, para [0059] describes wherein body contacts 154 comprising first body contact FBC may be connected to a power supply voltage wherein a power supply voltage would require a terminal to be on and in contact with first body contact FBC in order to provide the power supply voltage to the first body contact FBC).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivas Pulugurtha et al. (US 2015/0243748 A1; hereinafter “Pulugurtha”) in view of the following arguments:
Regarding Claim 4, Pulugurtha discloses all the limitations of claim 1.
Pulugurtha fails to explicitly disclose the limitations of claim 1, wherein a top surface of the first body contact is level with a top surface of the drain.
However, Pulugurtha discloses in para [0059] wherein body contacts may be connected to a power supply voltage in order to eliminate floating body effects which would cause undesirable parasitic leakage in the semiconductor device. Pulugurtha further discloses in para [0061] wherein the body contacts may be formed to any desired height within isolation trenches.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first body contacts 154 wherein a height of a first body contact 154 may extend an entire length of an isolation trench 138 so as to enable a power supply voltage terminal to be disposed above an upper surface of a drain 144 wherein a resulting upper surface of a first body contact 154 would be level with a top surface of the drain 144 in order to provide the advantage of eliminating possible current leakage between device components when a power supply terminal supplies a power supply voltage to a first body contact (Pulugurtha, para [0059] – para [0061]).
Regarding Claim 7, Pulugurtha discloses all the limitations of claim 6.
Pulugurtha fails to explicitly disclose the limitations of claim 6, wherein a top surface of the first body contact is level with a top surface of the isolation structure.
However, Pulugurtha discloses in para [0059] wherein body contacts may be connected to a power supply voltage in order to eliminate floating body effects which would cause undesirable parasitic leakage in the semiconductor device. Pulugurtha further discloses in para [0061] wherein the body contacts may be formed to any desired height within isolation trenches.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first body contacts 154 wherein a height of a first body contact 154 may extend an entire length of an isolation trench 138 so as to enable a power supply voltage terminal to be disposed above an upper surface of a drain 144 wherein a resulting upper surface of a first body contact 154 would be level with a top surface of the drain 144 which is level with a top surface of an isolation structure 124’ in order to provide the advantage of eliminating possible current leakage between device components when a power supply terminal supplies a power supply voltage to a first body contact (Pulugurtha, para [0059] – para [0061]).
Regarding Claim 11, Pulugurtha discloses all the limitations of claim 10.
Pulugurtha fails to explicitly disclose the limitations of claim 10, wherein the first body contact extends from the body to the terminal.
However, Pulugurtha discloses in para [0059] wherein body contacts may be connected to a power supply voltage in order to eliminate floating body effects which would cause undesirable parasitic leakage in the semiconductor device. Pulugurtha further discloses in para [0061] wherein the body contacts may be formed to any desired height within isolation trenches.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to try different size first body contacts 154 wherein a height of a first body contact 154 may extend to a desired length of an isolation trench 138 so as to enable a power supply voltage terminal to be disposed on an upper surface of the first body contact wherein a resulting structure would comprise the first body contact 154 extending from the body 102b to a power supply voltage terminal in order to provide the advantage of eliminating possible current leakage between device components when a power supply terminal supplies a power supply voltage to a first body contact (Pulugurtha, para [0059] – para [0061]) and to provide the well-known advantage of providing a reliable electrical connection between the body contact to the body and from the body contact to the power supply voltage terminal.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Srinivas Pulugurtha et al. (US 2015/0243748 A1; hereinafter “Pulugurtha”) in view of Mitsunari Sukekawa et al. (US 2021/0005611 A1; hereinafter “Sukekawa”).
Regarding Claim 9, Pulugurtha discloses all the limitations of claim 1.
Pulugurtha fails to explicitly disclose the semiconductor device of claim 1, further comprising a capacitor on the drain.
However, Sukekawa teaches a similar semiconductor device, comprising a capacitor on the drain (62 and 22, Fig. 14B, para [0034] describes a capacitor 62 being provided on and coupled to a drain region 22).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Pulugurtha with Sukekawa to further disclose a semiconductor device wherein a capacitor is disposed on a drain in order to provide the well-known advantage of providing a memory storage element with a DRAM cell to enable the cell to function as intended and store data in an element such as the capacitor (Sukekawa, para [0061]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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