Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election, with traverse, of Group I-A, claims 1-10, in the reply filed on December 15th, 2025 is acknowledged. The traversal is on the ground(s) that “the patterning/etching/deposition process to form a circuit justify a separate grouping”. This is not found persuasive. The restriction for examination purposes as indicated in the restriction /election requirement, mailed on 12/10/2025, is proper because all these inventions listed in this action are independent or distinct for the reasons given and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Accordingly, the requirement is still deemed proper and is therefore made FINAL.
Non-elected invention of Group II-B, claims 11-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I-A, claims 1-10 as follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 20, 2023 has been considered by the examiner.
Drawings
The drawings filed on 12/08/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-5, 8-9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Melde (US 2022/0223740, hereinafter as Meld ‘740) in view of Wang (US 2009/0207662, hereinafter as Wang ‘662).
Regarding Claim 1, Meld ‘740 teaches a non-volatile memory (NVM) structure, comprising:
a semiconductor substrate (Fig. 4, (106); [0021]);
first and second memory devices on the semiconductor substrate, each of the first and second memory devices including:
a floating gate (116, [0023]), a tunnelling insulator (114; [0022]) under the floating gate, an isolation layer (112; [0022]) over the floating gate (116), and a select gate (138; [0026]) and a control gate (130; [0024]) over the isolation layer (112), an erase gate (132; [0024]) shared by the first and second memory devices;
a source region (122; [0023]) under the erase gate (132); and
Thus, Meld ‘740 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a shallow trench isolation structure between the erase gate and the source region”.
Wang ‘662 teaches a shallow trench isolation structure (Fig. 2, (230); [0013]) between the erase gate (232; [0014]) and the source region (208; [0011]). It would obviously appear that the field oxide region (230) is a shallow trench isolation structure.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Meld ‘740 by having a shallow trench isolation structure between the erase gate and the source region for the purpose of providing a dielectric isolation structure (see para. [0013]) as suggested by Wang ‘662.
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Fig. 2 (Meld ‘740)
Regarding Claim 2, Meld ‘740 teaches the isolation layer (112; [0022]) is a continuous material layer that extends over the floating gates (116/216) of the first and second memory devices
Wang ‘662 teaches a shallow trench isolation structure (Fig. 2, (230); [0013]).
Further, it has been held to be within the general skill of a worker in the art to select the isolation layer is extends over a shallow trench isolation structure on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 7a of Richter (US 9583640)) as evidence.
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A person of ordinary skills in the art is motivated to have portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm in order to improve the performance of the semiconductor device.
Regarding Claim 3, Wang ‘662 teaches the first doped well (208; [0011]) extends along opposite sides of the shallow trench isolation structure (230) (see Fig. 2).
Regarding Claim 4, Meld ‘740 and Wang ‘662 are shown to teach all the features of the claim with the exception of explicitly the limitations: “portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm”.
However, it has been held to be within the general skill of a worker in the art to select a width of at least 10 nm on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to have portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm in order to improve the performance of the semiconductor device.
Regarding Claim 5, Wang ‘662 teaches the shallow trench isolation structure (230) extends into a trench in the substrate (202; [0010]) and is at least partially surrounded by the source region (208).
Regarding Claim 8, Wang ‘662 teaches the shallow trench isolation structure (230).
and the floating gate (FG).
Meld ‘740 and Wang ‘662 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices”.
However, it has been held to be within the general skill of a worker in the art to select an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to have an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices in order to improve the performance of the semiconductor device.
Regarding Claim 9, Wang ‘662 teaches an upper surface of the shallow trench isolation structure (230) is higher than the upper and lower surfaces of the tunnelling insulators of the first and second memory devices
Meld ‘740 and Wang ‘662 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an upper surface of the shallow trench isolation structure is between upper and lower surfaces of the tunnelling insulators of the first and second memory devices”.
However, it has been held to be within the general skill of a worker in the art to select an upper surface of the shallow trench isolation structure is between upper and lower surfaces of the tunnelling insulators of the first and second memory devices on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
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A person of ordinary skills in the art is motivated to have an upper surface of the shallow trench isolation structure is between upper and lower surfaces of the tunnelling insulators of the first and second memory devices in order to improve the performance of the semiconductor device.
Regarding Claim 10, Wang ‘662 teaches the shallow trench isolation structure (230) extends between sidewalls of the tunneling insulators of the first and second memory devices (see Fig. 2).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Meld ‘740 and Wang ‘662 as applied to claim 5 above, and further in view of Kang (US 2006/0076607, hereinafter as Kang ‘607).
Regarding Claim 5, Meld ‘740 teaches the source region comprises a first doped well (122; [0023]).
Meld ‘740 and Wang ‘662 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the source region comprises a deep doped well”.
Kang ‘607 teaches a deep doped well (Fig. 4e, (215_2); [0034]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Meld ‘740 and Wang ‘662 by having a deep doped well in order to prevent punch-through (see para. [0034]) as suggested by Kang ‘607.
Regarding Claim 7, Meld ‘740 teaches first (124; [0031]) and second (224; [0031]) drain regions respectively coupled to the first and second memory devices (see Fig. 4),
Kang ‘607 teaches a depth of the source region (215) is greater than a depth of the first and second drain regions (219; [0029]) (see Fig. 4f).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Shuai et al. (US 2022/0278238 A1)
Cai et al. (US 2021/0066324 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893