Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 1-10, in the reply filed on May 18th, 2026, are acknowledged. Claims 1, 3-4 and 10 have been amended. Claims 11-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of claims 1-10 as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-5, 8-9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Melde (US 2022/0223740, hereinafter as Meld ‘740) in view of Liu (US 2008/0217675, hereinafter as Liu ‘675).
Regarding Claim 1, Meld ‘740 teaches a non-volatile memory (NVM) structure, comprising:
a semiconductor substrate (Fig. 4, (106); [0021]);
first and second memory devices on the semiconductor substrate, each of the first and second memory devices including:
a floating gate (116, [0023]), a tunnelling insulator (114; [0022]) under the floating gate, an isolation layer (112; [0022]) over the floating gate (116), and a select gate (138; [0026]) and a control gate (130; [0024]) over the isolation layer (112), an erase gate (132; [0024]) shared by the first and second memory devices;
a source region (122; [0023]) under the erase gate (132); and
Thus, Meld ‘740 is shown to teach all the features of the claim with the exception of explicitly the limitations: “a shallow trench isolation structure between the erase gate and the source region; wherein at least a portion of the shallow trench isolation structure is located above an upper surface of the substrate and is located between the tunneling insulators of the first and second memory devices”.
Liu ‘675 teaches a shallow trench isolation structure (Fig. 9, (76); [0013]) between the erase gate (78; [0026]) and the source region (74; [0024]); wherein at least a portion of the shallow trench isolation structure (76) is located above an upper surface of the substrate (38; [0018]) and is located between the tunneling insulators (72; [0025]) of the first and second memory devices (52/62; [0022]). Examiner considers the inter poly oxide (76; [0025]) formed by depositing a dielectric layer, is the shallow trench isolation structure.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Meld ‘740 by having a shallow trench isolation structure between the erase gate and the source region; wherein at least a portion of the shallow trench isolation structure is located above an upper surface of the substrate and is located between the tunneling insulators of the first and second memory devices for the purpose of improving erase performance of the resulting flash memory, and reduced likelihood of floating gate shorting (see para. [0011]) as suggested by Liu ‘675.
PNG
media_image1.png
368
503
media_image1.png
Greyscale
Fig. 2 (Meld ‘740)
Regarding Claim 2, Meld ‘740 teaches the isolation layer (112; [0022]) is a continuous material layer that extends over the floating gates (116/216) of the first and second memory devices
Liu ‘675 teaches a shallow trench isolation structure (Fig. 9, (76); [0025]).
Further, it has been held to be within the general skill of a worker in the art to select the isolation layer is extends over a shallow trench isolation structure on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. (see Fig. 7a of Richter (US 9583640)) as evidence.
PNG
media_image2.png
18
19
media_image2.png
Greyscale
A person of ordinary skills in the art is motivated to have portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm in order to improve the performance of the semiconductor device.
Regarding Claim 3, Liu ‘675 teaches the portion of the source region (74) extends along opposite sides of the shallow trench isolation structure (76) (see Fig. 9).
Regarding Claim 4, Meld ‘740 and Liu ‘675 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm”.
However, it has been held to be within the general skill of a worker in the art to select a width of at least 10 nm for the portions of the source region extends along opposite sides of the shallow trench isolation structure on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
PNG
media_image2.png
18
19
media_image2.png
Greyscale
A person of ordinary skills in the art is motivated to have portions of the source region that extend along the opposite sides of the shallow trench isolation structure have a width of at least 10 nm in order to improve the performance of the semiconductor device.
Regarding Claim 5, Liu ‘675 teaches the shallow trench isolation structure (76) extends into a trench in the substrate (38) and is at least partially surrounded by the source region (74).
Regarding Claim 8, Liu ‘675 teaches the shallow trench isolation structure (76).
and the floating gate (62).
Meld ‘740 and Liu ‘675 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices”.
However, it has been held to be within the general skill of a worker in the art to select an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
PNG
media_image2.png
18
19
media_image2.png
Greyscale
A person of ordinary skills in the art is motivated to have an upper surface of the shallow trench isolation structure is above an upper surface of the floating gates of the first and second memory devices in order to improve the performance of the semiconductor device.
Regarding Claim 9, Liu ‘675 teaches an upper surface of the shallow trench isolation structure (76) is higher than the lower surfaces of the tunnelling insulators (72) of the first and second memory devices (see Fig. 9).
Meld ‘740 and Liu ‘675 are shown to teach all the features of the claim with the exception of explicitly the limitations: “an upper surface of the shallow trench isolation structure is higher than the upper surfaces of the tunnelling insulators of the first and second memory devices”.
However, it has been held to be within the general skill of a worker in the art to select an upper surface of the shallow trench isolation structure is higher than the upper surfaces of the tunnelling insulators of the first and second memory devices on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
PNG
media_image2.png
18
19
media_image2.png
Greyscale
A person of ordinary skills in the art is motivated to have an upper surface of the shallow trench isolation structure is higher than the upper surfaces of the tunnelling insulators of the first and second memory devices in order to improve the performance of the semiconductor device.
Regarding Claim 10, Liu ‘675 teaches the shallow trench isolation structure (76) contacts sidewalls of the tunneling insulators (72) of the first and second memory devices (see Fig. 9).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Meld ‘740 and Liu ‘675 as applied to claim 5 above, and further in view of Kang (US 2006/0076607, hereinafter as Kang ‘607).
Regarding Claim 5, Meld ‘740 teaches the source region comprises a first doped well (122; [0023]).
Meld ‘740 and Liu ‘675 are shown to teach all the features of the claim with the exception of explicitly the limitations: “the source region comprises a deep doped well”.
Kang ‘607 teaches a deep doped well (Fig. 4e, (215_2); [0034]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Meld ‘740 and Liu ‘675 by having a deep doped well in order to prevent punch-through (see para. [0034]) as suggested by Kang ‘607.
Regarding Claim 7, Meld ‘740 teaches first (124; [0031]) and second (224; [0031]) drain regions respectively coupled to the first and second memory devices (see Fig. 4),
Kang ‘607 teaches a depth of the source region (215) is greater than a depth of the first and second drain regions (219; [0029]) (see Fig. 4f).
Response to Arguments
Applicant’s arguments with respect to claims 10-10, filed on May 18th, 2026, have been considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
Prosecution Insights