DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of “Invention I, Species A-2, and Species B-2 (Claims 1-10)” in the reply filed on February 03, 2026, is acknowledged. Claims 11-20 are canceled as requested by applicant in the reply filed on February 03, 2026.
Status of Claims
As of the amendment filed February 03, 2026, new claims 21-30 have been added all of which depend either directly or indirectly on independent claims 21 or 27. Claims 11-20 have now been canceled. Claims 6 and 7 have been amended. Therefore, claims 1-10 and 21-30 remain pending, with claims 1,21, and 27 being independent. All new matter was originally described in the specification, drawings, or claims as filed; therefore, no new matter has been added.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,21,27 and 29 are rejected under 35 U.S.C. 103 as being obvious over US 2018/0358298 A1; Zhai et al.; 12/2018; (“298”) in view of US 2024/0329339 A1; Ecton et al.; 10/2024; (“339”).
Regarding Claim 1. 298 teaches in Figs. 4,12A and 12C about a semiconductor package, comprising:
a chiplet (Fig. 12C, item 110) comprising a semiconductor substrate (Fig. 12C, substrate of item 110) and die connectors (Fig. 12C, items 112) disposed over the semiconductor substrate (Fig. 12C, items 112 are disposed over the substrate body of item 110);
a first underfill (Fig. 12A, item 195) surrounding the chiplet (Fig. 12A, item 195 at least partially surrounds item 110); and
a first encapsulant (Fig. 12C, item 140) laterally covering the first underfill (Fig. 12C, item 140 laterally covers item 195), the first encapsulant comprising a first surface (Fig. 12C, top surface of item 140) and a second surface (Fig. 12C, bottom surface of item 140) opposite to the first surface (Fig. 12C, bottom surface of item 140 is opposite to top surface of item 140), the first surface being substantially leveled with surfaces of the die connectors (Fig. 4, top surface of item 140 is substantially leveled with top surfaces of items 112).
298 does not teach about a semiconductor package, comprising:
a first underfill comprising first fillers, a portion of the first fillers comprising a substantially planar surface at a first surface of the first underfill;
the second surface being substantially leveled with the first surface of the first underfill.
339 teaches in Fig. 8 about a semiconductor package, comprising:
a package substrate comprising first fillers (“package substrate 2252 may be formed of an insulator … epoxy film having filler particles”, [0098], Ln. 1-3), a portion of the encapsulant fillers comprising a substantially planar surface at a first surface of the first underfill (fillers of encapsulant item 2268 are substantially planar at a bottom surface of the first underfill item 2266, see Examiner annotated Fig. 8);
the second surface (bottom surface of encapsulant item 2268) being substantially leveled with the first surface of the first underfill (bottom surface of encapsulant item 2268 is substantially leveled with bottom surface of underfill item 2266).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the insulator epoxy material having filler particles and the substantially planar fillers of the encapsulant of 339 to use as a manufacturing insulating material and technique for the insulating first underfill in 298 in order to provide insulation as taught by 339 in [0098], Ln. 1-3, and for planarization technique in Fig. 8.
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Fig. 8, annotated by Examiner from Ecton et al., “339”
Regarding Claim 21. 298 teaches in Fig. 12C about a semiconductor package, comprising:
a first semiconductor die (item 130) and a second semiconductor die (item 132);
a chiplet (item 110) comprising a first side facing the first semiconductor die and the second semiconductor die (the top side of item 110 faces items 130 and 132) and a second side opposite to the first side (the bottom side of item 110 is opposite to the top side of item 110), the chiplet overlapping the first semiconductor die and the second semiconductor die in a thickness direction of the chiplet (item 110 overlaps items 130 and 132 in a thickness direction, wherein thickness of item 110 is presented from left-to-right within Fig. 12C), and the first semiconductor die and the second semiconductor die being electrically interconnected through the chiplet (“interposer chiplet 110 interconnects the first and second components 130, 132”, [0029], Ln. 18-19);
an encapsulant covering the chiplet (encapsulant item 140 covers at least the sides of the chiplet item 110), the encapsulant comprising a third side (top side of item 140) facing the first semiconductor die and the second semiconductor die and (top side of item 140 faces items 130 and 132) a fourth side opposite to the third side (bottom side of item 140 is opposite to top side of item 140), wherein the fourth side of the encapsulant is substantially leveled with the second side of the chiplet (bottom side of item 140 is substantially leveled with second side item 110).
298 does not teach about a semiconductor package, comprising:
a first underfill surrounding corners of the chiplet; and
an encapsulant covering the first underfill, the fourth side of the encapsulant is substantially leveled with a surface of the first underfill.
339 teaches in Fig. 8 about a semiconductor package, comprising:
a first underfill (item 2266) surrounding corners of the chiplet (item 2266 surrounds the corners of item 2257); and
an encapsulant covering the first underfill (item 2268 covers item 2266), the fourth side of the encapsulant is substantially leveled with a surface of the first underfill (bottom side of item 2268 is substantially leveled with the bottom surface of item 2266).
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the first underfill and the encapsulant layout of 339 to use as an insulating material layout around the chiplet in 298 in order to surround the chiplet with a first underfill and an encapsulant as taught by 339 in [0102], Ln. 1-8, and in Fig. 8.
Regarding Claim 27. 298 teaches in Figs. 12A and 12C about a semiconductor package, comprising:
a chiplet (Fig. 12C, item 110) and a TIV (Fig. 12C, item 142);
an underfill (Fig. 12A, item 195) extending along a sidewall of the chiplet (Fig. 12C, item 195 extends at least partially along a sidewall of item 110) and extending between the chiplet and the TIV (Fig. 12C, item 195 extends between items 110 and 142); and
the encapsulant laterally surrounding the chiplet, the underfill, and the TIV (Fig. 12C, item 140 laterally surrounds items 110, 195, and 142).
298 does not teach about a semiconductor package, comprising:
the underfill comprising first fillers; and
an encapsulant comprising second fillers different from the first fillers, wherein first planar surfaces of the first fillers are substantially leveled with second planar surfaces of the second fillers.
339 teaches in Fig. 8 about a semiconductor package, comprising:
a package substrate comprising first fillers (“package substrate 2252 may be formed of an insulator … epoxy film having filler particles”, [0098], Ln. 1-3); and
an encapsulant comprising second fillers (fillers of encapsulant item 2268, see Examiner annotated Fig. 8), wherein bottom surface of the underfill (bottom of item 2266) is substantially leveled with planar surfaces of second fillers at the bottom of the encapsulant (see Examiner annotated Fig. 8)
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the
invention was made, to consider utilizing the insulator epoxy material having filler particles and the substantially planar fillers of the encapsulant of 339 to use as a manufacturing insulating material and technique for the insulating first underfill in 298 in order to provide insulation as taught by 339 in [0098], Ln. 1-3, and in Fig. 8.
Regarding Claim 29. 298 teaches in Figs. 12A and 12C about a semiconductor package, comprising:
wherein the chiplet comprises a die connector (Fig. 4, item 112) laterally separated from the encapsulant by the underfill (Fig. 12C, item 112 laterally separated from item 140 by item 195).
Allowable Subject Matter
Claims 2-10,22-26,28 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art does not teach or suggest the claimed limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORGE ANDRES LOPEZ whose telephone number is (571)272-5763. The examiner can normally be reached M-F (8:30am to 5:00pm).
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JORGE ANDRES LOPEZ/Examiner, Art Unit 2897
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