DETAILED ACTION
This office action is in response to the election filed 2/5/2026.
Currently, claims 1-2, 4-6, 8-16 and 21-26 are pending, of which claims 21-26 are newly added. Claims 3, 7 and 17-20 have been canceled.
Election/Restrictions
Applicant’s election of Group I, Species Ic in the reply filed on 2/5/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Drawings
The drawings are objected to because the reference character “332”, which is to be used to identify the doped epitaxial layer, points to the gate spacer, which is associated with reference character “322”. This occurs in at least FIG. 5-12.
Furthermore, the drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the width of each of the gate spacers being greater than a width of each of the first inner spacers (claim 13). must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR STRUCTURE WITH NANOSTRUCTURES AND BOTTOM DIELECTRIC LAYER.
Claim Objections
Claims 11 and 15 are objected to because of the following informalities:
Claim 11 recites the term “form” in the last line, whereas it should be “from”.
Claim 15 recites the term “separated” in line 13, whereas it should be “separates”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites the limitation “isolation structures, disposed on opposite sides of the first vertical stack in a Y-direction” in line 5. The Y-direction is the direction in which the first gate structure extends (line 6). The first vertical stack is described as comprising first nanostructures (line 3). The disclosure contains no support for the limitation “isolation structures, disposed on opposite sides of the first vertical stack in a Y-direction. On the contrary, the disclosure shows the isolation structures not being disposed on opposite sides of the first vertical stack in the Y-direction, and instead it is the gate that is disposed on opposite sides of the first vertical stack in the Y-direction.
The elected embodiment (FIG. 7A-C) does not show a cross-section depicting the opposite sides of the first vertical stack in the Y-direction (only FIG. 7C depicts a cross-section along the Y-direction, but that is located at the S/D region area. Thus, reference is made to FIG. 3 and 5C. As seen in these figures, isolation structures 216/316 are not located on opposite sides of the vertical stack comprising nanostructures 204/310A(/B). Rather, it is the gate structure 206/320A that is located on opposite sides of the vertical stack in the Y-direction. The isolation structures are located on opposite sides of the S/D features 214/332(/334) in the Y-direction, but the S/D features are distinct from the vertical stack (“first source/drain features, disposed on opposite sides of the first vertical stack in an X- direction”, lines 8-9). Thus, there is no support for the limitation “isolation structures, disposed on opposite sides of the first vertical stack in a Y-direction.
Claims 22-26 recite the same limitation via dependency.
Claims 21-26 are also rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 21 recites the limitations “isolation structures, disposed on opposite sides of the first vertical stack in a Y-direction” and “a first gate structure, extending in the Y-direction and wrapped around each of the first nanostructures” in lines 5 and 6-7, respectively. One of ordinary skill in the art would not be enabled to construct such a structure based on the disclosure, particularly because a gate structure that wraps around the nanostructures would preclude isolation structures being disposed on opposite sides of the vertical stack comprising the nanostructures.
Claims 22-26 recite the same limitation via dependency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitations “isolation structures, disposed on opposite sides of the first vertical stack in a Y-direction” and “a first gate structure, extending in the Y-direction and wrapped around each of the first nanostructures” in lines 5 and 6-7, respectively. These limitations are contradictory. A gate structure that wraps around the nanostructures and extends in the Y-direction would preclude isolation structures being disposed on opposite sides of the vertical stack comprising the nanostructures in the Y-direction.
Claims 22-26 recite the same limitation via dependency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 11,195,911).
Pertaining to claim 1, Xie shows, with reference to FIG. 12, a semiconductor structure, comprising:
a substrate (10);
first nanostructures (17), suspended over and vertically arranged over the substrate;
a first gate structure (42), wrapped around each of the first nanostructures;
gate spacers (22S), formed on opposite sides of the first gate structure and over a topmost one of the first nanostructures;
first source/drain features (28/30), attached to opposite sides of the first nanostructures; and
a first bottom dielectric layer (40), formed over the substrate and below the first nanostructures, wherein the first bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure.
Pertaining to claim 2, Xie shows inner spacers (26), formed on opposite sides of the first gate structure and separating the first nanostructures from each other, wherein the first bottom dielectric layer is below the inner spacers and sandwiched between a bottommost pair of the inner spacers and the substrate.
Pertaining to claim 11, Xie shows a semiconductor structure, comprising:
a substrate (10);
first nanostructures (17), suspended over and vertically arranged over the substrate in a Z-direction;
a first gate structure (42), extending in a Y-direction (see FIG. 1) and wrapped around each of the first nanostructures;
first source/drain features (28/30), attached to opposite sides of the first nanostructures in an X- direction;
first inner spacers (26), formed on opposite sides of the first gate structure in the X-direction and between the first nanostructure in the Z-direction; and
a first bottom dielectric layer (40), formed below the first gate structure in the Z-direction and connected to a bottommost pair of the first inner spacers, wherein the first bottom dielectric layer is in contact with the first gate structure and separates the first gate structure form the substrate in the Z-direction.
Pertaining to claim 14, Xie shows the first inner spacers and the first bottom dielectric layer are formed of the same material (both may be SiN – col. 12, lines 57-58; col. 9, lines 6-10; col. 7, lines 57-59).
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 12,439,608, hereinafter ‘608).
Pertaining to claim 1, ‘608 shows, with reference to FIG. 7A, a semiconductor structure, comprising:
a substrate (10/12/14);
first nanostructures (20), suspended over and vertically arranged over the substrate;
a first gate structure (40), wrapped around each of the first nanostructures;
gate spacers (26), formed on opposite sides of the first gate structure and over a topmost one of the first nanostructures;
first source/drain features (36), attached to opposite sides of the first nanostructures; and
a first bottom dielectric layer (16), formed over the substrate and below the first nanostructures, wherein the first bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure.
Pertaining to claim 4, ‘608 shows the bottom dielectric layer has a thickness in the range of 5 to 50 nm, which overlaps the claimed range.
Please note that ‘608 anticipates other claims, but is not currently being relied upon for those claims because other prior art references are used in this office action for such showing.
Claims 1-2, 8-9, 11 and 14-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kang et al. (US 2025/0107227).
Pertaining to claim 1, Kang shows, with reference to FIG. 4, a semiconductor structure, comprising:
a substrate (4, including portions 6A);
first nanostructures (12), suspended over and vertically arranged over the substrate;
a first gate structure (16), wrapped around each of the first nanostructures;
gate spacers (15), formed on opposite sides of the first gate structure and over a topmost one of the first nanostructures;
first source/drain features (7/8A), attached to opposite sides of the first nanostructures; and
a first bottom dielectric layer (11), formed over the substrate and below the first nanostructures, wherein the first bottom dielectric layer is vertically sandwiched between the substrate and the first gate structure.
Pertaining to claim 2, Kang shows inner spacers (13), formed on opposite sides of the first gate structure and separating the first nanostructures from each other, wherein the first bottom dielectric layer is below the inner spacers and sandwiched between a bottommost pair of the inner spacers and the substrate.
Pertaining to claim 8, Kang shows second nanostructures (associated with S/D features 7/8B – see para. [0039], lines 8-9), suspended over and vertically arranged over the substrate; a second gate structure (another one of gates 16 – see FIG. 1), wrapped around each of the second nanostructures; second source/drain features (7/8B), attached to opposite sides of the second nanostructures; and a second bottom dielectric layer (11), formed over the substrate and below the second gate structure, wherein the second bottom dielectric layer is sandwiched between the second gate structure and the substrate, and wherein the first source/drain features are in direct contact with the substrate (7 in contact with 6A).
Pertaining to claim 9, Kang shows the first source/drain features are p-type source/drain features, and the second source/drain features are n-type source/drain features (para. [0045]).
Pertaining to claim 11, Kang shows a semiconductor structure, comprising:
a substrate (4, including portions 6A);
first nanostructures (12), suspended over and vertically arranged over the substrate in a Z-direction;
a first gate structure (16), extending in a Y-direction (see FIG. 1) and wrapped around each of the first nanostructures;
first source/drain features (7/8A), attached to opposite sides of the first nanostructures in an X- direction;
first inner spacers (13), formed on opposite sides of the first gate structure in the X-direction and between the first nanostructure in the Z-direction; and
a first bottom dielectric layer (11), formed below the first gate structure in the Z-direction and connected to a bottommost pair of the first inner spacers, wherein the first bottom dielectric layer is in contact with the first gate structure and separates the first gate structure from the substrate in the Z-direction.
Pertaining to claim 14, Kang shows the first inner spacers and the first bottom dielectric layer are formed of the same material (para. [0038]).
Pertaining to claim 15, Kang shows that, in addition to the nanosheet GAA FETs associated with S/D features 7/8A, the same type of nanosheet GAA FETs are associated with S/D features 7/8B, and thereby shows second nanostructures, suspended over and vertically arranged over the substrate in the Z- direction; a second gate structure, extending in the Y-direction and wrapped around each of the second nanostructures; second source/drain features, attached to opposite sides of the second nanostructures in the X- direction; second inner spacers, formed on opposite sides of the second gate structure in the X-direction and between the second nanostructures in the Z-direction; and a second bottom dielectric layer, formed below the second gate structure in the Z-direction, and connected to a bottommost pair of the second inner spacers, wherein the second bottom dielectric layer separated the second gate structure from the substrate in the Z-direction, and wherein the first source/drain features are in direct contact with opposite sides of the first bottom dielectric layer in the X-direction (FIG. 1, 4).
Pertaining to claim 16, Kang shows the first source/drain features are p-type source/drain features, and the second source/drain features are n-type source/drain features (para. [0045]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Xie.
Pertaining to claims 5 and 12, Kang shows the structures of claims 1 and 11, respectively, wherein the first source/drain features comprises an epitaxial buffer layer (7) and a doped epitaxial layer (8A) over the epitaxial buffer layer in the Z-direction; and wherein the first bottom dielectric layer is in contact with and between the epitaxial buffer layers in the X-direction (FIG. 4).
Although Kang does not explicitly show the epitaxial buffer layer is undoped, Xie teaches in col. 10, lines 7-8 that the epitaxial buffer layer between a doped S/D region and the substrate is an intrinsic (i.e. undoped) semiconductor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to try an intrinsic semiconductor material, as taught by Xie, for the material of the epitaxial buffer layer of Kang, as the court has held that choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success is prima facie obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Pertaining to claim 6, Kang shows a top surface of the epitaxial buffer layer is higher than a top surface of the first bottom dielectric layer and lower than a bottom surface of a bottommost one of the first nanostructures (FIG. 4).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Noh et al. (US 2020/0411641).
Kang shows the structure of claim 11, further comprising gate spacers (15) formed on opposite sides of the first gate structure (16) in the X-direction and over a topmost one of the first nanostructures (12) in the Z-direction.
Although Kang fails to show a width of each of the gate spacers is greater than a width of each of the first inner spacers in the X-direction, Noh teaches in FIG. 11 that, for a similar structure, the gate spacers 108 have a greater width than the inner spacers 308.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Kang according to the teaching of Noh such that the gate spacers have a greater width than the inner spacers, with the motivation that the relative widths of the spacers results from formation of a S/D feature with a curved sidewall that is beneficial for increasing channel mobility (para. [0030]).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the first nanostructures, the first gate structure, the first source/drain features, and the first bottom dielectric layer are formed on an n-type well region, and the second nanostructures, the second gate structure, the second source/drain features, and the second bottom dielectric layer are formed on a p-type well region in combination with the limitations of claims 1 and 8, on which claim 10 depends.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang et al. (US 2024/0421003), Kang et al. (US 2025/0126829), and Mukesh et al. (US 2025/0098229) all teach structures including gates surrounding nanostructures and having a bottom dielectric layer therebelow.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL LUKE/Primary Examiner, Art Unit 2896