DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
2. The Amendments filed March 12th, 2026 are noted. Applicant’s amendments to the Specification to overcome the objections set forth in the Non-Final Office Action mailed 12/15/2025 are noted. Applicant’s amendment(s) to the Specification have overcome the objection(s) to the Title previously set forth in the Non-Final Office Action mailed 12/15/2025, so the objection(s) to the Title has been withdrawn.
Applicant’s amendment(s) to the Claims have overcome the objection(s) to minor grammatical informalities previously set forth in the Non-Final Office Action mailed 12/15/2025, so the objection(s) to minor grammatical informalities have been withdrawn.
Applicant’s amendments to the claims are noted.
3. Claims 17 and 23-31 are now canceled; Claims 1-16 and 18-22 remain pending in the application.
4. Claims 1-16 and 18-22 have been fully considered in examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 12-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizaki (JP Pub No JP2019212875A). *see attached translation for [] citations*
Regarding claim 1, Ishizaki teaches a light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096], comprising:
a substrate (comprising 120) fig. 10 [0032];
an active LED structure (comprising 103, 104, 105) fig. 10 [0002, 0034, 0036] on (supported by) the substrate (comprising 120), the active LED structure (103-105) comprising an n-type layer (103) [0034, 0036, 0096], a p-type layer (105) [0034, 0036, 0096], and an active layer (104) [0035] (vertically) between the n-type layer (103) and the p-type layer (105); and
an antireflective structure (comprising 111) fig. 10 [0038-0039] (vertically) between the active LED structure (103-105) and the substrate (120) configured to reduce internal reflection of light (reduces internal reflection of light off of dielectric film 132) [0038] from the active LED structure (103-105 of 108) [0038] for propagation of the light through [0040] the antireflective structure (111) [see also fig. 23, 0040].
Regarding claim 2, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches further comprising a bonding layer (comprising 112) fig. 10 [0042] (112 bonded to 122 [0042]) (vertically) between the active LED structure (comprising 103-105) fig. 10 [0002, 0032] and the substrate (comprising 120) fig. 10 [0032].
Regarding claim 3, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 2. Ishizaki also teaches wherein the bonding layer (comprising 112) fig. 10 [0042] (112 bonded to 122 [0042]) is (vertically) between the antireflective structure (comprising 111) fig. 10 [0038-0039] and the substrate (comprising 120) fig. 10 [0032].
Regarding claim 4, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 2. Ishizaki also teaches wherein the antireflective structure (comprising 111) fig. 10 [0038-0039] is (vertically) between the bonding layer (comprising 112) fig. 10 [0042] and the substrate (comprising 120 and further comprising 107 of 130/131) (107 and 120 are both described as portions of “bonding substrate 130/131” [see fig. 4, 0053, 0103]).
Regarding claim 5, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 2. Ishizaki also teaches wherein the antireflective structure (comprising 111) fig. 10 [0038-0039] is (at least) a single antireflective layer (111) (vertically) between the bonding layer (comprising 112) fig. 10 [0042] and the substrate (comprising 107 of ‘bonding substrate 130/131’ comprising 107 and 120 [0053, 0103]).
Regarding claim 6, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 5. Ishizaki also teaches wherein a composition of the single antireflective layer (comprising 111 layer unit) fig. 10 [0038-0039] is graded (may be at least two distinct sub-layers with different compositions) [0039] such that an index of refraction (inherent to selected material [0039]) of the single antireflective layer (represented by 111) is graded (directionally-dependent in stack of sublayers represented by 111 depending on local material composition [0039]) between (vertically between) the bonding layer (comprising 112) fig. 10 [0042] and the substrate (comprising 107 of ‘bonding substrate 130/131’ comprising 107 and 120 [0053, 0103]).
Regarding claim 7, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 2. Ishizaki also teaches wherein the antireflective structure (comprising 111) fig. 10 [0038-0039] comprises a plurality of antireflective layers (may be at least two distinct sub-layers with different compositions) [0039] with index of refraction values that progressively decrease [0039] (two sub-layers of distinct materials [0039] of differing index of refraction values [0039] could be arranged to either increase or decrease progressively in a given direction) in a direction from the substrate (comprising 107 of ‘bonding substrate 130/131’ comprising 107 and 120 [0053, 0103]) toward the bonding layer (comprising 112) fig. 10 [0042].
Regarding claim 8, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 2. Ishizaki also teaches wherein the antireflective structure (comprising 111) fig. 10 [0038-0039] is a first antireflective structure (comprising 111) fig. 10 [0038-0039], and the LED chip (1000) further comprises a second antireflective structure (122 of 132) [0042, 0044] (122 of 132 used in conjunction with 111 to promote antireflection and favorable control and suppression of internal light reflection [0038, 0040]), wherein the bonding layer (comprising 112) fig. 10 [0042] is (vertically) between the first (111) and second (122) antireflective structures.
Regarding claim 9 Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches wherein the antireflective structure (comprising 111) fig. 10 [0038-0039] (111 may be at least three [‘two or more’] [0039] distinct sub-layers with different compositions) [0039] comprises a first antireflective layer (lower portion of 111), a second antireflective layer (middle portion of 111), and a third antireflective layer (upper portion of 111), wherein the first (lower) and third (upper) antireflective layers have a first index of refraction (could both be composed of a material like AlN) [0039], and the second antireflective layer (middle layer of 111 composed of GaN [0042]) has a second index of refraction that is different (AlN and GaN distinct materials with inherently distinct indices of refraction [0039]) than the first index of refraction (111 could be formed of ‘two or more layers’ of materials like AlN and GaN, implying that 111 could represent an AlN/GaN/AlN stack [0039]).
Regarding claim 10, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches wherein the p-type layer (105) [0034, 0036, 0096] is (vertically) between the antireflective structure (comprising 111) fig. 10 [0038-0039] and the n-type layer (103) [0034, 0036, 0096].
Regarding claim 12, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches wherein the active LED structure (comprising 103, 104, 105) fig. 10 [0002, 0034, 0036] comprises aluminum indium gallium phosphide (AlGaInP) [0035] and the substrate (comprising 120) [0032] comprises sapphire [0032].
Regarding claim 13, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches further comprising a p-contact (186) fig. 10 [0037] (contact on p-type layer 105 [0096]) and an n-contact (185) fig. 10 [0040] (contact on n-type layer 103 [0096]) that are both on a (top) side of the active LED structure (comprising 103, 104, 105) fig. 10 [0002, 0034, 0036] that is opposite the substrate (comprising 120) fig. 10 [0032] (185, 186 opposite substrate 120 in collective LED structure 1000).
Regarding claim 15, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches wherein a layer (111) [0038-0039] of the antireflective structure (comprising 111) fig. 10 [0038-0039] forms a bonding layer (111 layer part of ‘bonded substrate’ structure 130/131 [see fig. 4, 0053, 0103]) (vertically) between the active LED structure (comprising 103, 104, 105) fig. 10 [0002, 0034, 0036] and the substrate (comprising 120) fig. 10 [0032]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ishizaki (JP Pub No JP2019212875A), as applied in claim 1 above, in view of Hurni (U.S. PG Pub No US2022/0231192A1).
Regarding claim 11, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. Ishizaki also teaches wherein the (lower) layer (105) fig. 10 [0034, 0096] is (vertically) between the antireflective structure (comprising 111) fig. 10 [0038-0039] and the (upper) layer (103) [0034, 0036, 0096].
However, Ishizaki does not explicitly disclose wherein the lower layer (105) is n-type and the upper layer (103) is p-type (opposite conductivity types taught instead [0096]).
Hurni teaches a light emitting diode (LED) chip (700) fig. 7A [0102] wherein the lower layer (720) fig. 7A [0103] is n-type (or p-type [0103]) and the upper layer (750) fig. 7A [0103] is p-type (or n-type [0103]).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductivity types of the layers of the LED [0103] to be the opposite conductivity types (n-type for p-type and vice-versa [0103]) such that the lower layer of the LED structure of Ishizaki is an n-type layer positioned vertically between the upper p-type layer of Ishizaki and the underlying antireflective structure as either conductivity types for the layers of the diode are recognized in the art as equally-suitable [0103] and interchangeable [0103] without hindering LED performance [0103], as evidenced by Hurni.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ishizaki (JP Pub No JP2019212875A), as applied in claim 1 above, in view of Breva (U.S. PG Pub No US2021/0050482A1) (of record).
Regarding claim 14, Ishizaki teaches the light-emitting diode (LED) chip (1000) fig. 10 [0002, 0031, 0096] of claim 1. However, Ishizaki does not explicitly disclose further comprising:
at least one n-contact interconnect that extends through the p-type layer (105) [0034, 0036, 0096] and the active layer (26) [0041] to contact a portion of the n-type layer (103) fig. 10 [0034, 0036, 0096];
a dielectric reflector layer (36) [0053] on the p-type layer;
a metal reflector layer on the dielectric reflector layer; and
a plurality of reflective layer interconnects that extend from the metal reflector layer and through the dielectric reflector layer.
Breva teaches a light-emitting diode (LED) chip (10) fig. 2A [0040-0041], comprising:
at least one n-contact interconnect (20) [0040, 0045] that extends through the p-type layer (22) [0041] and the active layer (26) [0041] to contact a portion of the n-type layer (24) [0041];
a dielectric reflector layer (36) [0053] on the p-type layer (22);
a metal reflector layer (34) [0044, 0053] on the dielectric reflector layer (36); and
a plurality of reflective layer interconnects (32’s) [0043] that extend from the metal reflector layer (34) and (partially) through the dielectric reflector layer (36).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the LED chip structure of Ishizaki to be further processed to comprise the additional interconnect and reflective structures of Breva [0040-0045] in order to selectively improve light reflection and extraction of the LED structure [0040-0045] to improve light emission efficiency [0004-0005], as taught by Breva.
Allowable Subject Matter
Claims 16 and 18-22 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 16 is allowed because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “wherein the dielectric reflector layer, the metal reflector layer, and the plurality of reflective layer interconnects are on an opposite side of the active LED structure from the bonding layer” in the context of claim 16. Claims 18-22 are also allowed by virtue of their dependency on claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form (of record) are considered relevant to the present disclosure because they all feature LED chips with light-guiding structures.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 06/05/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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