Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/14/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-7 without traverse in the reply filed on 4/10/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al JP2001144266 A in view of Feng et al US 20180294269 A1. Nakamura et al and Feng et al will be referenced to as Nakamura and Feng henceforth.
Regarding Claim 1,
Nakamura teaches:
“A method of forming a semiconductor device having a capacitor array (lower electrode 45, upper electrode 49, capacitive insulating film 50, [0023], [0064], [0072], [0078] FIG. 18), comprising:
forming a top electrode plate (upper electrode 49, [0072], FIG. 18) of the capacitor array in an active region and a periphery region (annotated FIG. 9 #1) of a substrate (substrate 1, [0049], FIG. 9); removing the top electrode plate in the periphery region ([0078], FIG. 10);”
Nakamura doesn’t substantially teach:
“depositing a first oxide layer above the top electrode plate in the active region and the periphery region; forming a nitride film on the first oxide layer in the active region and in the periphery region;
depositing a second oxide layer on the nitride film in the active region and the periphery region (Feng: dielectric layer 154, [0021], FIG. 1); and
polishing the second oxide layer to expose the nitride film in the active region (Feng: [0006], [0022], FIG. 2: 154 is planarized using 56 as an etch stop layer.).”
However, Feng teaches:
“depositing a first oxide layer (Feng: first dielectric layer 54, [0021], FIG. 1) above the top electrode plate in the active region and the periphery region (Feng: [0021]: 54 is conformally formed over the active and peripheral regions as 52 is.); forming a nitride film on the first oxide layer in the active region and in the periphery region (Feng: second dielectric layer 56, [0021], FIG. 1: 56 is preferably silicon nitride.);
depositing a second oxide layer on the nitride film in the active region and the periphery region (Feng: dielectric layer 154, [0021], FIG. 1); and
polishing the second oxide layer to expose the nitride film in the active region (Feng: [0006], [0022], FIG. 2: 154 is planarized using 56 as an etch stop layer.).”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Nakamura is modifiable in view of Feng by replacing the dielectric structure on the top electrode of Nakamura for the dielectric structures of Feng.
This is because Feng teaches that it is disadvantageous to have an excess amount of dielectric material above a peripheral circuit region as this decreases the accuracy of an etching process when forming contact plugs which in turn leads to the damage of the peripheral circuit region (Feng [0003]). Feng teaches a method of reducing this excess of dielectric material by the formation of an oxide, nitride, and second oxide stack which allows for a planarization process which reduces this excess (Feng: [0006]).
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Nakamura: annotated FIG. 9 #1
Regarding Claim 3,
Nakamura/Feng teaches:
“The method of forming the semiconductor device having the capacitor array of claim 1, wherein the first oxide layer comprises a first portion extending along a lateral direction (Feng: annotated FIG. 2 #1), a second portion extending along a longitudinal direction (Feng: annotated FIG. 2 #1), and a third portion along the lateral direction (Feng: annotated FIG. 2 #1), the first portion and the second portion are in the active region (Feng: annotated FIG. 2 #1), the third portion is in the periphery region (Feng: annotated FIG. 2 #1), and the method of forming the capacitor array further comprises:
before removing the top electrode plate in the periphery region, forming a hard mask covering the first portion and the second portion of the first oxide layer in the active region (photoresist film, [0078]: The photoresist film is not shown in the figures. However, one of ordinary skill in the art would be aware that the photoresist film covers the first and second portions. For if the photoresist film didn’t cover these portions, then these portions would be etched.).”
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Feng: Annotated FIG. 2 #1
Regarding Claim 5,
Nakamura/Feng teaches:
“The method of forming the semiconductor device having the capacitor array of claim 3, wherein forming the nitride film on the first oxide layer in the active region and in the periphery region further comprises:
forming the nitride film at least covering the first portion and the second portion of the first oxide layer in the active region (Feng: annotated FIG. 2 #1) and covering the substrate in the periphery region (Feng: [0020], annotated FIG. 2 #1: 56 covers substrate 10 in the periphery region.).”
Regarding Claim 6,
Nakamura/Feng teaches:
“The method of forming the semiconductor device having the capacitor array of claim 1, wherein depositing the second oxide layer on the nitride film in the active region and the periphery region further comprises: depositing the second oxide layer such that a top surface of the second oxide layer in the periphery region is higher than a top surface of the nitride film in the active region (Feng: FIG. 1: the topmost surface of 154 in the periphery region is higher than a topmost surface of 56 in the active region.).”
Regarding Claim 7,
Nakamura/Feng teaches:
“The method of forming the semiconductor device having the capacitor array of claim 1, wherein polishing the second oxide layer to expose the nitride film in the active region further comprises:
applying an endpoint detection (EPD) mode control such that a top surface of the nitride film in the active region is level with a top surface of a remained second oxide layer in the periphery region (Feng: [0024], FIG. 2: 56 acts as an etch stop layer. There must also be an endpoint detection mode control which detects that the CMP process is acting on 56 in the memory cell region. Otherwise the oxide in the peripheral region would continue to be etched and planarization would not be possible.).”
Allowable Subject Matter
Claims 2 and 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 2,
Nakamura/Feng fails to explicitly teach:
“forming a polymer layer on the titanium nitride layer in the active region and the periphery region” In view of the rest of the limitations of claim 2.
Nakamura/Feng fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because neither Nakamura nor Feng teach a polymer layer on a titanium nitride layer. In Nakamura, only a tungsten film is on a titanium nitride film.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Nakamura/Feng to reach all of the limitations of the claim.
Regarding Claim 4,
Nakamura/Feng fails to explicitly teach :
“forming a contact penetrating the first portion of the first oxide layer and the nitride film and contacting the top electrode plate” In view of the rest of the limitations of claim 4.
Nakamura/Feng fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because a contact is not shown to penetrate a first portion of the first oxide in Feng. In the combination Nakamura/Feng, a contact would penetrate a third portion of the first oxide and not a first portion as seen in FIG. 18 of Nakamura.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Nakamura/Feng to reach all of the limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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