DETAILED ACTION
This correspondence is in response to the communications received October 20, 2023. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 11 and the claims that depend therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim contains a limitation which is described as having a physical relationship orientation that is confusing, as the relationship of “11. The integrated device of claim 8, wherein the upper surfaces of the insertion layer comprise an uppermost surface directly over the gate and two additional upper surfaces contacting the outermost sidewalls of the insertion layer.” Since the “insertion layer” is continuous, it is unclear how the upper surfaces of 110 could have both “two additional upper surfaces” which then contact the insertion layer’s own “outermost sidewalls”. How does a top surface that is continuous contacts it’s own sidewall? Perhaps a claim amendment such as, “two additional upper surfaces meet/end/terminate at/extend to
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1, an integrated device, comprising:
a substrate (102);
a gate (104) overlying the substrate (over 102);
a channel layer (108) separated from the gate (104) by a dielectric (106) and overlying the gate (108 over 104);
source/drain regions (109) on the channel layer (regions in 108),
the gate (104) extending between the source/drain regions (104 between two 109);
an insertion layer (110) conforming to an upper surface of the channel layer (on 108) and comprising a first material (¶ 0022, “the insertion layer 110 is or comprises an insulative material such as silicon dioxide (SiO2)”); and
a passivation layer (112) conforming to an upper surface of the insertion layer (112 on 110) and comprising a second material different from the first material (¶ 0022, “the passivation layer 112 is or comprises a metal oxide such as aluminum oxide (Al2O3), hafnium oxide (Hf2O3)”);
wherein the passivation layer has a higher density than the insertion layer (discussed in ¶ 0022), whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer (discussed in ¶ 0017).
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Regarding claim 15, the Applicant discloses in Figs. 1, 2 and 12-14, an method of forming an integrated device, comprising:
forming a gate over an underlying layer (“underlying layer 702 may be either the substrate 102 or an interlayer dielectric of the plurality of interlayer dielectrics 202.”, ¶ 0042);
forming a dielectric (106) over sidewalls and an upper surface of the gate (on sidewalls and upper surface of 104) and across the underlying layer (106 on 102 as well);
forming a channel layer (108) over upper surfaces and sidewalls of the dielectric;
forming an insertion layer (110) over upper surfaces and sidewalls of the channel layer;
forming a passivation layer (112) covering the insertion layer, the channel layer, the gate, and the dielectric;
etching contact openings through the passivation layer and the insertion layer (step from Fig. 12 to 13, where opening 1306 is made in 112 and in 110),
the contact openings (1306) extending to the channel layer (extends to 108); and
forming source/drain contacts (114) within the contact openings on opposite sides of the gate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Park et al. (US 2023/0200131).
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Regarding claim 1, the prior art of Xun discloses in Fig. 2, an integrated device (pixel integrated with transistor in an display panel), comprising:
a substrate (“substrate 110”, col. 3, lines 1-4);
a gate (“gate electrodes 124”, col. 3, line 6-7) overlying the substrate (124 on 110);
a channel layer (region 154 of 151, col. 4, lines 40-45, hereinafter referred to as ‘CH’) separated from the gate by a dielectric (“gate insulating layer 140”, col. 3, lines 30) and overlying the gate (both CH and 140 formed over the gate 124);
source/drain regions (173 and 175, col. 3, line 55 to col. 4, line 2, hereinafter referred to as ‘SDR’) on the channel layer (SDR on CH),
the gate extending between the source/drain regions (124 between the two SDR);
an insertion layer (180a, where the aspect of “insertion” being interpreted as a layer which allows for the “insertion” of an electrical signal through itself into the underlying layer of the SDR which connects to CH) conforming to an upper surface of the channel layer (180a conforms at least in part to upper surface of CH) and comprising a first material (col. 5, lines 5-9, “The passivation layer 180 may include a lower passivation layer 180a and an upper passivation layer 180b. The lower passivation layer 180a may be formed of a silicon oxide and the upper passivation layer 180b may be formed of a silicon nitride.”); and
a passivation layer (180b) conforming to an upper surface of the insertion layer (180b conforms at least in part to upper surface of 180a) and comprising a second material different from the first material (col. 5, lines 5-9, “The passivation layer 180 may include a lower passivation layer 180a and an upper passivation layer 180b. The lower passivation layer 180a may be formed of a silicon oxide and the upper passivation layer 180b may be formed of a silicon nitride.”).
The prior art of Xun does not explicitly disclose,
“wherein the passivation layer has a higher density than the insertion layer,
whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and
wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer.”
The prior art of Xun discloses wherein the “passivation layer” is silicon nitride and the “insertion layer” is silicon oxide (see immediately above teachings). Then, the Park reference in ¶ 0069, “silicon nitride … has density higher than that of silicon oxide, so that it is effective in preventing hydrogen diffusion”. Therefore, the configuration of higher density material over lower density material is present in the teaching of Xun.
Applicant discloses in paragraph 0022, that when the upper dielectric layer is more dense than the lower dielectric layer, and if the layer immediately above the channel is silicon oxide, then the limitations of, “whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer”, would be satisfied.
Although Xun discloses the correct material layer configuration, Xun does not explicitly disclose the inherent density relationship between silicon nitride and silicon oxide. Even though this is a natural physical quantity that is characteristic of the relationship of the silicon nitride and silicon oxide materials, it is noted that this position is also substantiated by the teaching that is positively recited by the Park reference in ¶ 0069, “silicon nitride … has density higher than that of silicon oxide, so that it is effective in preventing hydrogen diffusion”. The inclusion of the Park reference then teaches the purpose of using the higher density material over the lower density material for the purpose of “preventing hydrogen diffusion” (¶ 0069). So then combination of teachings of Xun in view of Park would then collaboratively teach the limitation of, “whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer.”
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the Xun disclosed configuration wherein the “passivation layer” is silicon nitride and the “insertion layer” is silicon oxide, would inherently have the property of “whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer”, because Xun teaches the same materials as disclosed by Applicant. See MPEP 2112.01.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the passivation layer has a higher density than the insertion layer,
whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and
wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer.”, as disclosed by Park in the system of Xun, for the purpose of protecting the channel from external contaminants. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 3, the prior art of Xun et al. disclose the integrated device of claim 1, and Xun discloses in Fig. 2, wherein the channel layer (CH) conforms to outer sidewalls of the gate (CH shown to conform to outer sidewalls of 124), and the insertion layer (180a) conforms to outer sidewalls of the channel layer (180a conforms at least in part to the outer sidewalls of CH/151/154).
Regarding claim 5, the prior art of Xun et al. disclose the integrated device of claim 1, and Xun discloses in Fig. 2, wherein the insertion layer (180a) extends past outer sidewalls of the channel layer (180a extend past CH/151/154), and spaces outer sidewalls of the channel layer from the passivation layer (180a spaces CH/151/154 from 180b).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Park et al. (US 2023/0200131) in view of Sharma et al. (US 12,238,913).
Regarding claim 2, the prior art of Xun et al. disclose the integrated device of claim 1, and Xun discloses wherein the first material comprises silicon dioxide (col. 5, lines 5-9, “The lower passivation layer 180a may be formed of a silicon oxide”), and the Park reference discloses that the purpose of the use of arrangement of silicon nitride over silicon oxide is for the purpose of “preventing hydrogen diffusion” (¶ 0069), which then in combination discloses, “and the environmental materials comprise oxygen gas, hydrogen gas, and water vapor.”
Ultimately, Xun et al. do not disclose that, “the second material comprises aluminum”.
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Sharma discloses a similar layer to the claimed “passivation layer”, which is known in the art as a “inter level dielectric (ILD)”, of the material type claimed (aluminum oxide) and also that the ILD could alternatively be silicon nitride. Again, silicon nitride being the material Xun uses for the “passivation layer”. See Fig. 4A, and discussed in col. 12, lines 65-67 , “the insulating material 452 may be e.g., any of the ILD materials described herein, e.g., silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride.” Therefore, it is taught with the Sharma reference, that aluminum oxide is an obvious variant of the material of silicon nitride.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the passivation layer has a higher density than the insertion layer,
whereby the passivation layer mitigates diffusion of environmental materials towards the channel layer, and
wherein the insertion layer mitigates diffusion of the second material from the passivation layer into the channel layer.”, as disclosed by Sharma in the system of Xun et al., for the purpose of protecting the channel from external contaminants. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Park et al. (US 2023/0200131) in view of Yamazaki et al. (US 6,246,070).
Regarding claim 4, the prior art of Xun et al. disclose the integrated device of claim 1, however Xun does not disclose, “wherein outer sidewalls of the insertion layer are aligned with outer sidewalls of the channel layer.”
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Yamazaki discloses in Fig. 3, wherein outer sidewalls of the insertion layer (108 is the equivalent layer to the “insertion layer”) are aligned with outer sidewalls of the channel layer (the equivalent channel layer being 111/114/116, so then sidewalls of 108 and portion 116 are aligned).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein outer sidewalls of the insertion layer are aligned with outer sidewalls of the channel layer.”, as disclosed by Yamazaki in the system of Xun et al., for the purpose of protecting the channel and also to prevent unwanted charge build up between a stack of three insulators. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Park et al. (US 2023/0200131) in view of Yoon et al. (US 12,232,352).
Regarding claim 6, the prior art of Xun et al. disclose the integrated device of claim 1, however Xun does not explicitly disclose, “further comprising contacts extending to the source/drain regions of the channel layer, the contacts extending to an upper surface of the channel layer through the insertion layer and the passivation layer.”
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Yoon discloses in Fig. 6, further comprising contacts (SE, DE) extending to the source/drain regions (Act1 or Act3) of the channel layer (Act), the contacts extending to an upper surface of the channel layer (Act) through the insertion layer (equivalent layer of Yoon being 112) and the passivation layer (114). It should be noted that the manner which the contacts, insertion layer and passivation layer have already been disclosed by the Xun reference. This Yoon reference merely presented to show the source drain regions being formed within the channel layer and the contacts making direct contact with the top surface of the channel layer. This configuration is known to be an obvious variant to the semiconductor oxide with source drain electrode regions as intermediate to the source drain contacts of Xun.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“further comprising contacts extending to the source/drain regions of the channel layer, the contacts extending to an upper surface of the channel layer through the insertion layer and the passivation layer.”, as disclosed by Yoon in the system of Xun et al., for the purpose of making electrical connection to source and drain impurity regions of the semiconductor pattern of which the channel is formed between, so as to allow for the operation of the transistor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Park et al. (US 2023/0200131) in view of Sasaki (US 2016/0300954).
Regarding claim 7, the prior art of Xun et al. disclose the integrated device of claim 1, however Xun does not disclose, “wherein the channel layer has a first thickness, and the insertion layer has a second thickness that is greater than the first thickness.”
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Sasaki discloses in Fig. 3, wherein the channel layer has a first thickness (“The thickness of the oxide semiconductor layer 140 is, for example, 20 nm to 200 nm.”, ¶ 0067), and the insertion layer has a second thickness (equivalent layer being 160, “The thickness of the channel protective layer 160 is, for example, 50 nm to 500 nm.”, ¶ 0075) that is greater than the first thickness (160 thicknesses are comparatively larger than those of 140).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the channel layer has a first thickness, and the insertion layer has a second thickness that is greater than the first thickness.”, as disclosed by Sasaki in the system of Xun et al., for the purpose of improving the insertion layer’s ability to protect the channel. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 8, 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Yamazaki et al. (US 6,246,070).
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Regarding claim 8, the prior art of Xun discloses in Fig. 2, an integrated device (pixel integrated with transistor in an display panel), comprising:
a gate (“gate electrodes 124”, col. 3, line 6-7) overlying a substrate (124 over “substrate 110”, col. 3, lines 1-4);
a dielectric (“gate insulating layer 140”, col. 3, lines 30) surrounding an upper surface and outer sidewalls of the gate (140 surrounds upper surface and outer sidewalls of 124);
a channel layer (region 154 of 151, col. 4, lines 40-45, hereinafter referred to as ‘CH’) surrounding upper surfaces and outer sidewalls of the dielectric (CH/151/154 surround upper surfaces and outer sidewalls of 140);
an insertion layer (180a, where the aspect of “insertion” being interpreted as a layer which allows for the “insertion” of an electrical signal through itself into the underlying layer of the SDR which connects to CH) surrounding upper surfaces and outer sidewalls of the channel layer (180a surround upper surfaces and outer sidewalls of CH/151/154); and
a passivation layer (col. 5, lines 5-9, “The passivation layer 180 may include … an upper passivation layer 180b.”) surrounding upper surfaces and outer sidewalls of the insertion layer (180b surround upper surfaces and outer sidewalls of 180a),
wherein the insertion layer (180a) separates an uppermost surface of the channel layer (top surface of CH/151/154) from the passivation layer (180a separates CH/151/154 from 180b).
Xun does not disclose, “wherein the passivation layer and the dielectric extend past outermost sidewalls of the insertion layer”.
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Yamazaki discloses in Fig. 3, wherein the passivation layer (equivalent layer being 117) and the dielectric (equivalent layer being 103) extend past outermost sidewalls of the insertion layer (both 117, 103 extend past outermost sidewall of 108, where 108 is the equivalent layer to the “insertion layer”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the passivation layer and the dielectric extend past outermost sidewalls of the insertion layer”, as disclosed by Yamazaki in the system of Xun et al., for the purpose of protecting the channel and also to prevent unwanted charge build up between a stack of three insulators. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 11, the prior art of Xun et al. disclose the integrated device of claim 8, and Xun discloses in Fig. 2, wherein the upper surfaces of the insertion layer (180a) comprise an uppermost surface directly over the gate (highest points of 180a are over portions of 124) and two additional upper surfaces contacting the outermost sidewalls of the insertion layer (horizontal portions of 180a over 171/175/151/154/CH meet at sidewalls which are vertical extensions of 180a).
Regarding claim 12, the prior art of Xun et al. disclose the integrated device of claim 11, wherein the two additional upper surfaces are at a substantially equal depth beneath the uppermost surface (the above noted, “horizontal portions of 180a over 171/175/151/154/CH meet at sidewalls which are vertical extensions of 180a” are at the same depth beneath the highest points of 180a).
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Yamazaki et al. (US 6,246,070) in view of Park et al. (US 2023/0200131).
Regarding claim 9, the prior art of Xun et al. disclose the integrated device of claim 8, however Xun does not explicitly disclose, “wherein the insertion layer comprises a first material with a first density and the passivation layer comprises a second material with a second density, where the first density is less than the second density.”
The prior art of Xun discloses wherein the “passivation layer” is silicon nitride and the “insertion layer” is silicon oxide (col. 5, lines 5-9, “The passivation layer 180 may include a lower passivation layer 180a and an upper passivation layer 180b. The lower passivation layer 180a may be formed of a silicon oxide and the upper passivation layer 180b may be formed of a silicon nitride.”). Then, the Park reference in ¶ 0069, discloses, “silicon nitride … has density higher than that of silicon oxide, so that it is effective in preventing hydrogen diffusion”. Therefore, the configuration of higher density material over lower density material is present in the teaching of Xun.
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the Xun disclosed configuration wherein the “passivation layer” is silicon nitride and the “insertion layer” is silicon oxide, would inherently have the property of “where the first density is less than the second density”, because Xun teaches the same materials as disclosed by Applicant. See MPEP 2112.01.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the insertion layer comprises a first material with a first density and the passivation layer comprises a second material with a second density, where the first density is less than the second density.”, as disclosed by Park in the system of Xun, for the purpose of protecting the channel from external contaminants. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 10, the prior art of Xun et al. disclose the integrated device of claim 9, however Xun does not explicitly disclose, “wherein the second material diffuses into the insertion layer, wherein a third material of the channel layer diffuses into the insertion layer, and wherein the insertion layer mitigates diffusion of the second material into the channel layer and the third material into the passivation layer.”
It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the Xun disclosed configuration wherein the “passivation layer” is silicon nitride, the “insertion layer” is silicon oxide and the “channel layer” is a semiconductor material, would inherently have the property of “wherein the second material diffuses into the insertion layer, wherein a third material of the channel layer diffuses into the insertion layer, and wherein the insertion layer mitigates diffusion of the second material into the channel layer and the third material into the passivation layer.”, because Xun teaches the same materials as disclosed by Applicant. See MPEP 2112.01.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“wherein the second material diffuses into the insertion layer, wherein a third material of the channel layer diffuses into the insertion layer, and wherein the insertion layer mitigates diffusion of the second material into the channel layer and the third material into the passivation layer.”, as disclosed by Xun, for the purpose of protecting the channel from external contaminants. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Yamazaki et al. (US 6,246,070) in view of Yoon et al. (US 12,232,352).
Regarding claim 13, the prior art of Xun et al. disclose the integrated device of claim 12, and Xun does not explicitly disclose, “further comprising source/drain contacts extending through the two additional upper surfaces to contact the channel layer and couple to source/drain regions in the channel layer.”
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Yoon discloses in Fig. 6, further comprising source/drain contacts (SE and DE) extending through the two additional upper surfaces (regions of equivalent insertion layer 112 and passivation layer 113/114 allow passage of SE/DE) to contact the channel layer (to contact Act) and couple to source/drain regions (Act2/Act3) in the channel layer (Act). This Yoon reference merely presented to show the source drain regions being formed within the channel layer and the contacts making direct contact with the top surface of the channel layer. This configuration is known to be an obvious variant to the semiconductor oxide with source drain electrode regions as intermediate to the source drain contacts of Xun.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“further comprising source/drain contacts extending through the two additional upper surfaces to contact the channel layer and couple to source/drain regions in the channel layer.”, as disclosed by Yoon in the system of Xun et al., for the purpose of making electrical connection to source and drain impurity regions of the semiconductor pattern of which the channel is formed between, so as to allow for the operation of the transistor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claims 15-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Xun et al. (US 9,515,093) in view of Sasaki (US 2016/0300954) in view of Yoon et al. (US 12,232,352).
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Regarding claim 15, the prior art of Xun discloses in Fig. 2, a method of forming an integrated device (pixel integrated with transistor in an display panel), comprising:
forming a gate (“gate electrodes 124”, col. 3, line 6-7) over an underlying layer (124 over “substrate 110”, col. 3, lines 1-4);
forming a dielectric (“gate insulating layer 140”, col. 3, lines 30) over sidewalls and an upper surface of the gate (140 surrounds upper surface and outer sidewalls of 124) and across the underlying layer (140 stretches across 110;
forming a channel layer (region 154 of 151, col. 4, lines 40-45, hereinafter referred to as ‘CH’) over upper surfaces and sidewalls of the dielectric (CH/151/154 surround upper surfaces and outer sidewalls of 140);
forming an insertion layer (180a, where the aspect of “insertion” being interpreted as a layer which allows for the “insertion” of an electrical signal through itself into the underlying layer of the SDR which connects to CH) over upper surfaces and sidewalls of the channel layer (180a surround upper surfaces and outer sidewalls of CH/151/154);
forming a passivation layer (col. 5, lines 5-9, “The passivation layer 180 may include … an upper passivation layer 180b.”) covering the insertion layer, the channel layer, the gate, and the dielectric (180b covers 180a, CH/151/154, 124 and 140);
patterning contact openings through the passivation layer and the insertion layer (“The contact hole 185 exposing a part of the drain electrode 175 is formed by patterning the passivation layer 180”, col. 7, lines 30-35, where 180 includes both of 180a and 180b); and
forming a source/drain contact (via portion of 191) within the contact opening (185).
First, Xun does not disclose the method of, “etching contact openings through the passivation layer and the insertion layer” and “forming source/drain contacts within the contact openings on opposite sides of the gate”.
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Sasaki discloses in Fig. 4C, etching contact openings through the passivation layer and the insertion layer (as Xun only discloses patterning through 180a and 180b, Sasaki shows that patterning can be carried out by “etching” film 161 to patterned film 160, ¶ 0113) and forming source/drain contacts within the contact openings on opposite sides of the gate (source 170s and drain 170d contacts are formed in the openings created by the etch step).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“etching contact openings through the passivation layer and the insertion layer” and “forming source/drain contacts within the contact openings on opposite sides of the gate”, as disclosed by Sasaki in the system of Xun et al., for the purpose of providing a means to create electrical access to the source and drain nodes of the transistor to be able to operate the transistor. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Xun does not disclose the method of, “the contact openings extending to the channel layer”.
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Yoon discloses in Fig. 6, the contact openings extending to the channel layer (openings in the dielectric layers above the channel Act, are formed with openings to allow for contacts SE and DE to make contact directly with the channel pattern Act, to make contact with the source Act2 and drain Act3 regions of channel layer Act). This Yoon reference is merely presented to show the source drain regions being formed within the channel layer and the contacts making direct contact with the top surface of the channel layer. This configuration is known to be an obvious variant to the semiconductor oxide with source drain electrode regions as intermediate to the source drain contacts of Xun.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of, “the contact openings extending to the channel layer”, as disclosed by Yoon in the system of Xun et al., for the purpose of making electrical connection to source and drain impurity regions of the semiconductor pattern of which the channel is formed between, so as to allow for the operation of the transistor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 16, the prior art of Xun et al. disclose the method of claim 15, however Xun does not disclose limitations of claim 16. However Sasaki discloses in Figs. 4B to 4C,
further comprising:
etching the channel layer (“FIG. 4B, the patterned oxide semiconductor layer 140 is formed on the gate insulating layer 130. Specifically, the oxide semiconductor film 141 is wet-etched using the resist 180 and the silicon oxide layer 153 as a mask to form the oxide semiconductor layer 140.”, ¶ 0101) before forming the insertion layer (channel etch occurs in step in Fig. 4B(i) which is before the formation of film 161 in Fig. 4C), such that the insertion layer (161) covers outermost sidewalls of the channel layer and contacts the dielectric (161 covers outermost sidewalls of 140 and contacts equivalent dielectric 130).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitations of,
“further comprising:
etching the channel layer before forming the insertion layer, such that the insertion layer covers outermost sidewalls of the channel layer and contacts the dielectric”, as disclosed by Sasaki in the system of Xun et al., for the purpose of individuating the channel for a single transistor device and to isolate said device from neighboring devices. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 17, the prior art of Xun et al. disclose the method of claim 15, and Xun et al. disclose, further comprising:
etching the insertion layer (Xun’s equivalent insertion layer was etched in the combination rejection of claim 15) and the channel layer (Sasaki teaches, “FIG. 4B, the patterned oxide semiconductor layer 140 is formed on the gate insulating layer 130. Specifically, the oxide semiconductor film 141 is wet-etched using the resist 180 and the silicon oxide layer 153 as a mask to form the oxide semiconductor layer 140.”, ¶ 0101) before forming the passivation layer (Xun’s Fig. 2, 180b, formed after CH/151/154 and 180a), such that the passivation layer (180b) covers outermost sidewalls of the insertion layer and the channel layer (by modifying CH of Xun with Sasaki, the channel will now be finite in the horizontal directions, that will cause insertion layer 180a to drape over the sidewall of modified CH, that causes 180b to covering a “sidewall” of 180a and CH).
Regarding claim 18, the prior art of Xun et al. disclose the method of claim 15, wherein the channel layer has a first upper surface on a first side of the gate and a second upper surface on a second side of the gate, and wherein the source/drain contacts are coupled to the first upper surface and the second upper surface (Xun’s Fig. 2 has source drain 171/175 on either side of gate 124 and on upper surface of channel CH).
Regarding claim 20, the prior art of Xun et al. disclose the method of claim 15, and the Xun et al. combination rejection of claim 15, also appears to satisfy, wherein the dielectric (Xun Fig. 2, element 140) extends past outermost sidewalls of the channel layer (Xun’s channel CH is modified by Sasaki to have finite horizontal pattern shape, as combined in the rejection of claim 15, thereby the 140 of Xun would extend past the lateral extent of modified CH by Sasaki) and separates the channel layer from the gate (140 of Xun separates CH from 124).
Allowable Subject Matter
Claims 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“14. The integrated device of claim 13, wherein the channel layer comprises an active region extending between the source/drain contacts, wherein the active region has a first concentration of a material from the passivation layer and wherein an outer region of the channel layer at outermost sidewalls of the channel layer has a second concentration of the material from the passivation layer, where the second concentration is greater than the first concentration.”
“19. The method of claim 15, wherein the passivation layer is formed using a physical vapor deposition process, and wherein ion bombardment from the physical vapor deposition process leads to diffusion of a material of the passivation layer into the insertion layer.”
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893