DETAILED ACTION
This is in response to amendment to application no. 18/490,919 filed on June 5, 2026.
Claims 9-28 are presented for examination.
Claims 1-8 were previously cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al (US Pub 2009/0302374).
In re claim 9, Anderson et al discloses a semiconductor structure, comprising: a first isolation structure (i.e. 120) and a second isolation structure (i.e. 220) disposed in a substrate (i.e. 1001, 1002, 120, 220); a doped region (i.e. 110) interposed between the first isolation structure and the second isolation structure in the substrate (i.e. see at least paragraph 0039 disclosing 110 is at least n-type); a gate structure (i.e. 140, 240) disposed over the doped region; a first gate extension (i.e. 131) protruding from the gate structure into the first isolation structure, the first gate extension having a first depth measured from a top surface of the substrate (i.e. see at least Figure 3B); and a second gate extension (i.e. 242) protruding from the gate structure into the second isolation structure, the second gate extension having a second depth measured from the top surface of the substrate, the second depth being different from the first depth (i.e. see at least Figure 3B; paragraph 0037).
Response to Arguments
Applicant's arguments filed June 5, 2026 have been fully considered but they are not persuasive.
In response to applicants’ argument that Anderson does not teach or suggest “a first gate extension protruding from the gate structure…and a second gate extension protruding from the gate structure…” (emphasis added), Examiner asserts that Anderson does teach a gate structure (i.e. 140, 240) and a first gate extension (i.e. 131) protruding from the gate structure…and a second gate extension (i.e. 242) protruding from the gate structure (i.e. see at least Figure 3B).
Allowable Subject Matter
Claims 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-28 are allowed.
The following is an examiner’s statement of reasons for allowance: The closest prior art of Anderson et al (US Pub 2009/0302374) either singularly or in combination fails to anticipate or render obvious a semiconductor structure, comprising: a first active region and a second active region disposed in a substrate; an isolation structure interposed between the first active region and the second active region; a first gate structure disposed over the first active region; a first source/drain (S/D) structure engaged with the first gate structure to form a first transistor configured as a pull-up transistor; a first gate extension extending from the first gate structure into the isolation structure, the first gate extension having a first depth; a second gate structure disposed over the second active region; and a second gate extension extending from the second gate structure into the isolation structure, the second gate extension having a second depth that is greater than the first depth as recited in claim 16 and a quasi fin-FET device comprising: a substrate comprising a plurality of semiconductive channels bounded by a corresponding plurality of isolation trenches along a first lateral direction and by a corresponding plurality of gate structures disposed over the plurality of semiconductive channels and extending, in the first lateral direction, between the corresponding isolation trenches, wherein: a first junction between a first gate structure of the plurality of gate structures and a first conduction channel of the plurality of conduction channels includes a first feature of the first gate structure extending a first distance downward from an upper surface of the first conduction channel, contacting an outer sidewall of the first conduction channel and an inner sidewall of the corresponding isolation trench; and a second junction between a second gate structure of the plurality of gate structures and a second conduction channel of the plurality of conduction channels: includes a second feature of the second gate structure extending a second distance, different from the first distance, downward from an upper surface of the first second conduction channel, contacting the outer sidewall of the second conduction channel and the inner sidewall of the corresponding isolation trench; or does not extend below an upper surface of the second conduction channel; wherein the first conduction channel and the second conduction channel are conduction channels in a static random-access memory (SRAM) cell as recited in claim 21.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817
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