DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 9-20, in the reply filed on February 3, 2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on August 15, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 16, 17, and 21-23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Anderson et al (US Pub 2009/0302374).
In re claim 9, Anderson et al discloses a semiconductor structure, comprising: a first isolation structure (i.e. 120) and a second isolation structure (i.e. 220) disposed in a substrate (i.e. 1001, 1002, 120, 220); a doped region (i.e. 110) interposed between the first isolation structure and the second isolation structure in the substrate (i.e. see at least paragraph 0039 disclosing 110 is at least n-type); a gate structure (i.e. 140) disposed over the doped region; a first gate extension (i.e. 131) protruding from the gate structure into the first isolation structure, the first gate extension having a first depth measured from a top surface of the substrate (i.e. see at least Figure 3B); and a second gate extension (i.e. 242) protruding from the gate structure into the second isolation structure, the second gate extension having a second depth measured from the top surface of the substrate, the second depth being different from the first depth (i.e. see at least Figure 3B; paragraph 0037).
In re claim 16, Anderson et al discloses a semiconductor structure, comprising: a first active region (i.e. 110) and a second active region (i.e. 210) disposed in a substrate (i.e. 1001, 1002, 120, 220); an isolation structure (i.e. 220) interposed between the first active region and the second active region; a first gate structure (i.e. 140) disposed over the first active region; a first gate extension (i.e. 131) extending from the first gate structure into the isolation structure, the first gate extension having a first depth (i.e. see at least Figure 3B); a second gate structure (i.e. 240) disposed over the second active region; and a second gate extension (i.e. 242) extending from the second gate structure into the isolation structure, the second gate extension having a second depth that is greater than the first depth (i.e. see at least Figure 3B; paragraph 0037).
In re claim 17, Anderson et al discloses further comprising: first source/drain (S/D) structures (i.e. 119) engaged with the first gate structure to form a first transistor; and second S/D structures (i.e. 219) engaged with the second gate structure to form a second transistor (i.e. see at least paragraph 0058).
In re claim 21, Anderson et al discloses a quasi fin-FET device comprising: a substrate (i.e. 1001, 1002, 120, 220) comprising a plurality of semiconductive channels bounded by a corresponding plurality of isolation trenches (i.e. 120, 220) along a first lateral direction and by a corresponding plurality of gate structures (i.e. 140, 240) disposed over the plurality of semiconductive channels and extending, in the first lateral direction, between the corresponding isolation trenches, wherein: a first junction between a first gate structure of the plurality of gate structures and a first conduction channel of the plurality of conduction channels includes a first feature of the first gate structure (i.e. 131) extending a first distance downward from an upper surface of the first conduction channel, contacting an outer sidewall of the first conduction channel and an inner sidewall of the corresponding isolation trench; and a second junction between a second gate structure of the plurality of gate structures (i.e. 242) and a second conduction channel of the plurality of conduction channels: includes a second feature of the second gate structure extending a second distance, different from the first distance, downward from an upper surface of the first conduction channel, contacting the outer sidewall of the second conduction channel and the inner sidewall of the corresponding isolation trench (i.e. see at least Figure 3B; paragraph 0037).
In re claim 22, Anderson et al discloses wherein the first feature is a symmetric feature at first and second isolation trenches bounding the first conduction channel along the first lateral direction (i.e. see at least Figure 3B).
In re claim 23, Anderson et al discloses wherein the first feature directly contacts the outer sidewall of the first conduction channel and the inner sidewall of the corresponding isolation trench (i.e. see at least Figure 3B).
Allowable Subject Matter
Claims 10-15, 18-20, and 24-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Chen et al (US Pub 2006/0086987)
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/ANTHONY HO/Primary Examiner, Art Unit 2817