DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2020/0152242 A1), and further in view of Tanaka (US 11,450,381 B2).
Regarding claim 1, Chang teaches a memory device, comprising:
a first memory array (Fig. 5, array 120) comprising a plurality of first memory cells arranged along a corresponding one of a plurality of first columns and respectively across a plurality of first rows, wherein each of the plurality of first columns extends along a first lateral direction and each of the plurality of first rows extends along a second lateral direction (Fig. 5, word lines WL are extended on a second lateral direction in the row direction, and bit lines BL are extended on a first lateral direction in the column direction. The first memory array 120 comprises a plurality of memory cells arranged in rows and columns);
a first bit line segment extending along the first lateral direction and operatively coupled to each of the plurality of first memory cells, wherein the first bit line segment is disposed in a first one of a plurality of metallization layers above the plurality of first memory cells (BL1_1 is in a first lateral direction in a first metallization layer M1 which connects plurality of memory cells in array 120);
a second bit line segment extending also along the first lateral direction and continually flying cross the first memory array but operatively isolated from any of the plurality of first memory cells, wherein the second bit line segment is disposed in a second one of the plurality of metallization layers (BL2_1 is in a first lateral direction in a second metallization layer M2. BL2_1 cross the first memory array 120 and isolated from the first memory cells in the first memory array 120. BL2_1 continually flying across array 120); and
a third bit line segment extending also along the first lateral direction and continually flying cross the first memory array but operatively isolated from any of the plurality of first memory cells, wherein the third bit line segment is disposed in a third one of the plurality of metallization layers (BL3_1 extends is in a first lateral direction in a third metallization layer M3. BL3_1 cross the first memory array 120 and is isolated from any of the plurality of first memory cells in array 120. BL3_1 continually flying cross the first memory array);
wherein the first bit line segment has a first length along the first lateral direction, the second bit line segment has a second length along the first lateral direction, and the third bit line segment has a third length along the first lateral direction, and wherein the first length is less than the second length and the second length is less than the third length (segment for BL1_1 is less than segment BL2_1 and is less than the third segment BL3_1), and
wherein the first bit line segment is operatively coupled to a first bit line controller configured to access a first portion of the plurality of first memory cells, the second bit line segment is operatively coupled to a second bit line controller configured to access a plurality of second memory cells of a second memory array, and the third bit line segment is operatively coupled to a third bit line controller configured to access a plurality of third memory cells of a third memory array (Currently, the claims does not explicitly claim the first, second and third bit line controller are different. Fig. 5, teaches the bit lines connected to control circuit 160. In order to expedite the prosecution of the case, Tanaka is used to teach that different memory arrays can have a separate control circuits. Fig. 2, shows different control buffers for each array, buffer circuit 220L and 220R).
It would have been obvious to a person with the ordinary skill in the art before the effective filling date of the claimed invention to have separate control circuits for each array in order to process operations faster and increase the speed for the memory device.
Regarding claim 2, Chang further teaches the memory device of claim 1, further comprising:
a second memory array comprising (Fig. 5, array 122) a plurality of second memory cells arranged along a corresponding one of a plurality of second columns and respectively across a plurality of second rows, wherein each of the plurality of second columns extends along the first lateral direction and each of the plurality of second rows extends along the second lateral direction; and
a third memory array comprising (Fig. 5, array 524) a plurality of third memory cells arranged along a corresponding one of a plurality of third columns and respectively across a plurality of third rows, wherein each of the plurality of third columns extends along the first lateral direction and each of the plurality of third rows extends along the second lateral direction.
Regarding claim 3, Chang further teaches the memory device of claim 2, wherein the second bit line segment is operatively coupled to each of the plurality of second memory cells, and the third bit line segment is operatively coupled to each of the plurality of third memory cells (Fig. 5, second bit line segment BL3_1 can be coupled to the memory cells in the three arrays/sub-banks).
Regarding claim 4, Chang further teaches the memory device of claim 2, wherein the second memory array is interposed between the first memory array and the third memory array along the first lateral direction (Fig. 5, second memory array 122 is between 524 and 120).
Regarding claim 5, Chang further teaches the memory device of claim 2, further comprising: a fourth bit line segment extending also along the first lateral direction and disposed in the first metallization layer, wherein the fourth bit line segment couples the second bit line segment to each of the plurality of second memory cells (fourth bit line segment BL1_2); and
a fifth bit line segment extending also along the first lateral direction and disposed in the first metallization layer, wherein the fifth bit line segment couples the third bit line segment to each of the plurality of third memory cells (Fifth bit line segment BL1_3).
Regarding claim 6, Chang further teaches the memory device of claim 2, further comprising: a fourth memory array comprising a plurality of fourth memory cells arranged along a corresponding one of a plurality of fourth columns and respectively across a plurality of fourth rows, wherein each of the plurality of fourth columns extends along the first lateral direction and each of the plurality of fourth rows extends along the second lateral direction; and a fourth bit line segment extending also along the first lateral direction and operatively coupled to each of the plurality of fourth memory cells, but operatively isolated from any of the plurality of first, second, or third memory cells, wherein the fourth bit line segment is disposed in a fourth one of the plurality of metallization layers (Fig. 5 is an exemplary to show part of the structure for memory device. The memory device is not limited to only 3 sub-banks/arrays. The memory device will have a plurality of arrays/sub-banks more than what is shown in Fig. 5. Therefore, the memory device inherently have a fourth memory array to comprise the fourth memory cells in similar arrangement as the ones in Fig. 5).
Regarding claim 7, Chang further teaches the memory device of claim 1, wherein the third metallization layer is disposed above the second metallization layer, and the second metallization layer is disposed above the first metallization layer (¶0024).
Regarding claim 8, Chang further teaches the memory device of claim 1, wherein the third bit line segment is disposed directly above the second bit line segment, and the second bit line segment is disposed directly above the first bit line segment (Fig. 5 shows the third bit line segment is in M3 which is above the second bit line segment in M2 and is above the first bit line segment M1).
Regarding claim 9, Chang further teaches the memory device of claim 1, wherein the first column along which the plurality of first memory cells are disposed, the second column along which the plurality of second memory cells are disposed, and the third column along which the plurality of third memory cells are disposed are aligned with one another in the first lateral direction (Fig. 5).
Regarding claim 10, Chang further teaches the memory device of claim 1, wherein a first number of the plurality of first rows is twice a second number of the plurality of second rows, and twice a third number of the plurality of third rows (Fig. 5).
Regarding claims 11-20, the claims have similar limitations as claims 1-10 except the claims are written in a different format. Therefore, the claims are rejected under the same grounds of rejection for the same reason.
Regarding claim 21, Chang teaches the memory device of claim 2, wherein the third bit line segment extends across the first and second memory arrays but is operatively isolated from any of the first or second memory cells (Fig. 5, the third bit line segment BL3_1 extends across the first and second arrays 120 and 122 and isolated from the two arrays).
Regarding claim 22, Chang further teaches the memory device of claim 1, wherein the second bit line segment extending across the first memory array comprises extending above the first memory array, and wherein the third bit line segment extending across the first memory array comprises extending above the first memory array (Fig. 5, the second bit line and the third bit line segments extend above the first memory array 120).
Response to Arguments
Applicant's arguments filed 08/18/2025 have been fully considered but they are not persuasive.
Applicant’s representative argues in page 9 “For example, the specification provides by using the bit line segments as claimed, "the load of each BL can be further reduced, which advantageously allows the memory array to include an increased number of rows while having its BLs immune from high loads." (Spec. ¶[0024 ], showing an improvement reached by the second and third bit line segment continually flying across the first memory array). A search of the prior art has failed to disclose the combination of elements recited in claims 1. For example, Chang is directed…” The examiner agrees the prior art teaches strap cells 140 and 540 between the memory arrays which is different that then current case which does not use strap cells between the arrays. However, the current claims require the second and third bit line segment to extend along the first direction and continually flying across the first memory array. Chang teaches the second segment BL2_1 and third segment BL3_1 to extend along the first direct and continually flying across the first memory array 120 and the strap cells 140. Therefore, the current reference still teaches the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824