DETAILED ACTION
This action is responsive to the application No. 18/490,923 filed on October 20, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the third plurality of sidewall recesses, the chuck, and cleaning chamber must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-10 are objected to because of the following informalities:
In claim 1, line 14, “substrate,; and” should be changed to -- substrate; and --.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 13 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 13 recites implementing the first process parameters and the second process parameters based on a first quantity of the contaminants in the first plurality of sidewall recesses and on a second quantity of the contaminants in the second plurality of sidewall recesses. There is no written description support for implementing the first and second process parameters based on a first and second quantity of the contaminants. As best understood this claim describes some form of feedback control wherein a quantity of contaminants is measured and then process parameters are selected based on the quantity measured.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites implementing the first process parameters and the second process parameters based on a first quantity of the contaminants in the first plurality of sidewall recesses and on a second quantity of the contaminants in the second plurality of sidewall recesses. It is unclear how first and second process parameters are implemented based on a first and second quantity of contaminants. The claim implies some form of feedback control is used wherein the quantity of contaminants is determined, e.g. a thickness of the passivation/contamination, and then the process variables are selected or adjusted based on the quantity of contaminant (e.g. a measured thickness). It is unclear how one would implement, select, or adjust the first and second process parameters based on a quantity of contaminants nor is it clear how a quantity of contaminants is measured or determined. In a Bosch etch, each part of the cycle affects the other parts of the cycle, e.g. if the fluorocarbon polymer passivation step (the fluorocarbon polymer passivation is the claimed contamination) duration is increased, thereby depositing a thicker passivation/contamination film, then the subsequent etch step would need to be adjusted to ensure the passivation is completely removed from the bottom of the trench so the subsequent isotropic etch step can proceed. So in any Bosch etch, there is always a dependency between the etching and passivation steps, and having more or less passivation present would require adjustments to the etching steps in the cycle. For the purpose of examination, this will be treated as in any Bosch process, the amount of passivation present determines the amount of removal/etching required in the recipe, e.g. thicker passivation will require a longer or faster etching step, and anyone successfully performing Bosch etching will have already determined a suitable balance between the etching and passivation steps when developing the recipe.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Itou et al. (US 2018/0240678) in view of Zhang (US 2009/0239353) and Doub et al. (US 2015/0357241).
(Re Claim 1) Itou teaches a method of making a semiconductor die, comprising (see Figs. 1-5C and ¶¶19-89):
forming a first plurality of sidewall recesses in a sidewall of a substrate and extending along a first length of the sidewall from a first surface of the substrate, the first plurality of sidewall recesses each having less than a first depth, wherein the forming the first plurality of sidewall recesses results in first residual contaminants formed in at least a portion of the first plurality of sidewall recesses (see Figs. 3A and 4, first recesses S1, residual contaminants discussed below);
forming a second plurality of sidewall recesses in the sidewall of the substrate and extending along a second length of the sidewall between the first plurality of sidewall recesses and a second surface of the substrate, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth, wherein the forming the second plurality of sidewall recesses results in second residual contaminants formed in at least a portion of the second plurality of sidewall recesses (see Figs. 3B and 4, second recesses S2, residual contaminants discussed below);
the semiconductor die being singulated by the forming of the second plurality of sidewall recesses upon reaching the second surface of the substrate (Fig. 3B); and
removing the first residual contaminants and the second residual contaminants therefrom (the ashing step disclosed, ¶¶82-84 will remove residual contaminates from the etched sidewalls).
Itou lacks details regarding the residual contaminants from the Bosch DRIE processes, however these residual contaminants are well known in the art and occur when performing Bosch etching. Furthermore, there are numerous prior art teaching directed to cleaning these unwanted residues after a Bosch etch process. First, with respect to Itou’s disclosed ashing process, related art from Zhang (¶244) recognizes an oxygen plasma or a chemical cleaning can be used to remove residues generated during the etching from the exposed sidewalls. In view of Zhang, a PHOSITA would recognize Itou’s oxygen plasma ashing process will obviously remove residues from the die sidewalls. Related art from Doub also recognizes the etching results in unwanted sidewall residual contamination and discloses spraying solvents to clean the residues (¶¶4,16, 20, 32, 33, 37, 39-41, Fig. 5). In view of the prior art, a PHOSITA would recognize Itou’s etching process will deposit residual contamination on the exposed etched sidewalls. Residual contamination from Bosch DRIE is well known in the art, and it is also well known to perform cleaning, either in the form of a plasma clean, e.g. oxygen plasma (as taught by Itou and Zhang), or to use a wet chemical/solvent clean to remove the unwanted residues as taught by Doub. In view of Zhang and Doub, a PHOSITA would recognize the etching naturally forms residue on the etched sidewalls and find it obvious to perform a cleaning step following Itou’s etching to remove the undesirable residual contaminants. Also, while wet or dry cleaning can be used to remove the contaminants, one may want to avoid aggressive oxygen plasma ashing since this can also attack and damage the exposed dicing tape, therefore a PHOSITA would find the wet chemical cleaning options disclosed by Doub are better options. Doub offering a process clearly compatible with Itou’s existing process flow wherein the solvents can be sprayed directly on the dies while still mounted on a tape frame (Fig. 5).
(Re Claim 2) wherein forming the first plurality of sidewall recesses comprises performing a first processing cycle with first process parameters, and further wherein forming the second plurality of sidewall recesses comprises performing a second processing cycle with second process parameters (see first and second etching routines ¶¶57-81).
(Re Claim 3) wherein the first processing cycle and the second processing cycle include a deposition of a passivation layer, an anisotropic etch, and an isotropic etch, wherein at least a portion of the passivation layer is included in the first residual contaminants and/or the second residual contaminants (see first and second etching routines ¶¶57-81, residual contaminants discussed above).
(Re Claim 4) wherein the first process parameters include an isotropic etching time (¶64 8-15 sec) that is less than an isotropic etching time of the second process parameters (¶76 10-25 sec).
(Re Claim 6) wherein the first process parameters include an isotropic etching power level (¶64: etch includes max power of 2500 W) that is less than an isotropic etching power level of the second process parameters (¶76: etch includes max power up to 5000 W).
(Re Claim 7) further comprising: mounting the substrate on carrier tape (Fig. 1A: wafer 1, tape 3) prior to forming the first plurality of sidewall recesses and the second plurality of sidewall recesses; moving the semiconductor die, on the carrier tape, to a cleaning chamber (as modified above in view of Doub, in Fig. 5 the wafer on a tape frame is moved from the plasma etcher to the wet cleaning chamber).
Itou is silent regarding performing the removing of the semiconductor die while the semiconductor die is attached to the carrier tape. A PHOSITA would recognize that in both Itou and Doub, a wafer mounted on a tape is diced, and following dicing the dies are conventionally picked from the tape for further processing, e.g. testing, binning/sorting, and packaging, as this is standard process flow. Doub further teaches after the cleaning, the singulated dies are picked from the tape (Fig. 11). A PHOSITA would find it obvious to perform this conventional process step after Itou’s dicing and Doub’s cleaning steps are completed and the tape carrier is no longer necessary.
(Re Claim 8) wherein the removing comprises rinsing the semiconductor die using a solvent spray (see discussion above, Doub sprays solvents to clean the residues, Fig. 5, ¶¶4,16, 20, 32, 33, 37, 39-41).
(Re Claim 9) comprising: forming the first plurality of sidewall recesses each with less than a first width; and forming the second plurality of sidewall recesses each with at least a second width that is greater than the first width (Figs. 3A-4).
(Re Claim 11) Itou teaches a method of performing semiconductor die singulation, comprising (see Figs. 1-5C and ¶¶19-89):
mounting a substrate attached to carrier tape on a mounting chuck (Figs. 1-2: wafer 1, tape 3, mounting chuck 111);
defining a dicing channel in the substrate (Figs. 3A-3B);
forming a first plurality of sidewall recesses in sidewalls of the dicing channel and extending along a first length of the sidewalls from a first surface of the substrate, the first plurality of sidewall recesses each defining less than a first depth (see Figs. 3A and 4, first recesses S1);
forming a second plurality of sidewall recesses in the sidewalls of the dicing channel and extending along a second length of the sidewalls between the first plurality of sidewall recesses and a second surface of the substrate that is attached to the carrier tape, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth (see Figs. 3B and 4, second recesses S2);
determining that the forming of the second plurality of sidewall recesses has reached the carrier tape, to thereby define a first die and a second die (Fig. 3B, etching is performed until the tape 3 is reached and the dies are singulated).
Itou is silent regarding transitioning the first die and the second die on the carrier tape to a cleaning chamber and removing contaminants from the first plurality of sidewall recesses and the second plurality of sidewall recesses of the first die and the second die, and removing the first die and the second die from the carrier tape. While Itou does not discuss contaminants, these are well known to occur during Bosch DRIE processes as taught by Zhang (¶244) and Daub (¶¶4,16, 20, 32, 33, 37, 39-41). Doub teaches the plasma etching results in unwanted sidewall contamination and discloses spraying solvents in a cleaning chamber to clean the residues (Fig. 5). Residual contamination from Bosch DRIE is well known in the art, and it is also well known to perform cleaning using a wet chemical/solvent clean to remove the unwanted residues as taught by Doub. In view of Doub, a PHOSITA would find it obvious to perform a cleaning step following Itou’s etching to remove residual contaminants. Also, while both wet and dry cleaning can be used, one may want to avoid aggressive oxygen plasma ashing since this can also attack and damage the exposed dicing tape, therefore a PHOSITA would find the wet chemical cleaning options disclosed by Doub is a better option. Doub offering a process compatible with Itou’s existing process flow wherein the solvents can be sprayed directly on the dies while still mounted on a tape frame (Fig. 5). With respect to the removing the dies from the tape, this would be obvious to a PHOSITA as this is common practice after dicing. A PHOSITA would recognize that in both Itou and Doub, a wafer mounted on a tape is diced, and following dicing the dies are conventionally picked from the tape for further processing, e.g. testing, binning/sorting, and packaging, as this is standard process flow. Doub further teaches after the cleaning, the singulated dies are picked from the tape (Fig. 11). A PHOSITA would find it obvious to perform this conventional process step after Itou’s dicing and Doub’s cleaning steps are completed and the tape carrier is no longer necessary.
(Re Claim 12) wherein forming the first plurality of sidewall recesses comprises performing a first processing cycle with first process parameters, and further wherein forming the second plurality of sidewall recesses comprises performing a second processing cycle with second process parameters (see first and second etching routines ¶¶57-81).
(Re Claim 13, see §112 rejection above) implementing the first process parameters and the second process parameters based on a first quantity of the contaminants in the first plurality of sidewall recesses and on a second quantity of the contaminants in the second plurality of sidewall recesses (¶¶65-66 and 79-80, each process includes a deposition step which forms the passivation/contaminants and a subsequent removal step that removes the passivation/contaminants from the bottom of the trench while leaving passivation/contaminants in the scallops in the sidewalls).
(Re Claim 14) wherein the first processing cycle and the second processing cycle include a deposition of a passivation layer, an anisotropic etch, and an isotropic etch, wherein at least a portion of the passivation layer is included in the contaminants (see first and second etching routines ¶¶57-81, residual contaminants discussed above).
(Re Claim 15) wherein the removing comprises rinsing the first die and the second die using a solvent spray to remove the contaminants (see discussion above, Doub sprays solvents to clean the residues, Fig. 5, ¶¶4,16, 20, 32, 33, 37, 39-41).
(Re Claim 16) further comprising: forming the first plurality of sidewall recesses each with less than a first width; and forming the second plurality of sidewall recesses each with at least a second width that is greater than the first width (see Figs. 3A-4, first recesses S1 have a width less than the second recesses S2).
(Re Claim 17) Itou teaches a method of performing semiconductor die singulation, comprising (see Figs. 1-5C and ¶¶19-89):
mounting a substrate attached to carrier tape on a mounting chuck (Figs. 1-2: wafer 1, tape 3, mounting chuck 111);
defining a dicing channel in the substrate (Figs. 3A-3B);
forming a first plurality of sidewall recesses in sidewalls of the dicing channel and extending along a first length of the sidewalls from a first surface of the substrate, the first plurality of sidewall recesses each defining less than a first depth, wherein the forming the first plurality of sidewall recesses results in first residual contaminants formed in at least some of the first plurality of sidewall recesses (see Figs. 3A and 4, first recesses S1, residual contaminants discussed below);
forming a second plurality of sidewall recesses in the sidewalls of the dicing channel and extending along a second length of the sidewalls between the first plurality of sidewall recesses and a second surface of the substrate that is attached to the carrier tape, the second plurality of sidewall recesses each defining at least a second depth that is greater than the first depth, wherein the forming the second plurality of sidewall recesses results in second residual contaminants formed in at least some of the second plurality of sidewall recesses (see Figs. 3B and 4, second recesses S2, residual contaminants discussed below);
determining that the forming of the second plurality of sidewall recesses has reached the carrier tape, to thereby define a first die and a second die (Fig. 3B, etching is performed until the tape 3 is reached and the dies are singulated).
Itou is silent regarding transitioning the first die and the second die on the carrier tape to a cleaning chamber; rinsing the first residual contaminants from the first plurality of sidewall recesses and the second residual contaminants from the second plurality of sidewall recesses of the first die and the second die using a solvent spray; and removing the first die and the second die from the carrier tape.
While Itou does not discuss contaminants, these are well known to occur during Bosch DRIE processes as taught by Zhang (¶244) and Daub (¶¶4,16, 20, 32, 33, 37, 39-41). Doub teaches the plasma etching results in unwanted sidewall contamination and discloses spraying solvents in a cleaning chamber to clean the residues (Fig. 5). Residual contamination from Bosch DRIE is well known in the art, and it is also well known to perform cleaning using a wet chemical/solvent clean to remove the unwanted residues as taught by Doub. In view of Doub, a PHOSITA would find it obvious to perform a cleaning step following Itou’s etching to remove residual contaminants. Also, while both wet and dry cleaning can be used, one may want to avoid aggressive oxygen plasma ashing since this can also attack and damage the exposed dicing tape, therefore a PHOSITA would find the wet chemical cleaning options disclosed by Doub is a better option. Doub offering a process compatible with Itou’s existing process flow wherein the solvents can be sprayed directly on the dies while still mounted on a tape frame (Fig. 5). With respect to the removing the dies from the tape, this would be obvious to a PHOSITA as this is common practice after dicing. A PHOSITA would recognize that in both Itou and Doub, a wafer mounted on a tape is diced, and following dicing, the dies are conventionally picked from the tape for further processing, e.g. testing, binning/sorting, and packaging, as this is standard process flow. Doub further teaches after the cleaning, the singulated dies are picked from the tape (Fig. 11). A PHOSITA would find it obvious to perform this conventional process step after Itou’s dicing and Doub’s cleaning steps are completed and the tape carrier is no longer necessary.
(Re Claim 18) wherein forming the first plurality of sidewall recesses comprises performing a first processing cycle with first process parameters, and further wherein forming the second plurality of sidewall recesses comprises performing a second processing cycle with second process parameters (see first and second etching routines ¶¶57-81).
(Re Claim 19) wherein the first processing cycle and the second processing cycle include a deposition of a passivation layer, an anisotropic etch, and an isotropic etch, wherein at least a portion of the passivation layer is included in the first residual contaminants and/or the second residual contaminants (see first and second etching routines ¶¶57-81, residual contaminants discussed above).
(Re Claim 20) further comprising: forming the first plurality of sidewall recesses each with less than a first width; and forming the second plurality of sidewall recesses each with at least a second width that is greater than the first width (see Figs. 3A-4, first recesses S1 have a width less than the second recesses S2).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Itou et al. (US 2018/0240678), Zhang (US 2009/0239353), and Doub et al. (US 2015/0357241) as applied above and further in view of Bhardwaj et al. (US 6,051,503) and Gauldin et al. (US 2014/0242780).
(Re Claim 5) wherein the first process parameters include an isotropic etching flow rate that is less than an isotropic etching flow rate of the second process parameters.
Itou is silent regarding using a different flow rate for the two different etch processes. It is noted Itou apparently accomplishes the different scallop sizes through changing the time and power during each etch (¶¶64,76) while the underlying objective is a faster or slower etch rate, the larger scallops corresponding to faster etch rates and that minimizing etching time is desirable (¶¶67,81). A PHOSITA would be motivated to look to related art to teach alternatives for controlling the process, in particular how to achieve faster or slower etch rates. Related art from Bhardwaj discloses the etch rate is also affected by the gas glow (col 2 lines 9-15) and teaches an example wherein the gas flows are changed during different stages of an etching process (Fig. 20). Related art from Gauldin teaches (¶181): The plasma dicing process typically follows a chemically assisted etch mechanism, where the etch rate of the exposed materials is in part a function of the concentration of available reactants. For the case of Silicon in a Fluorine-containing plasma (e.g., SF6 plasma), the etch rate is typically a function of free Fluorine (e.g., SF6 partial pressure, SF6 mass flow rate, etc.). In view of Bhardwaj and Gauldin, a PHOSITA would recognize the etch rate can be increased through higher gas flow rates which would be advantageous since the cycle times could be proportionally decreased. Thus a PHOSITA would find it obvious to increase the etching gas flow for Itou’s second etch process to accomplish the same high etch rate while saving time.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Itou et al. (US 2018/0240678), Zhang (US 2009/0239353), and Doub et al. (US 2015/0357241) as applied above and further in view of Grivna et al. (US 2010/0120230).
(Re Claim 10) comprising: forming a third plurality of sidewall recesses in the sidewall of the substrate and extending along a third length of the sidewall between the first plurality of sidewall recesses and the second plurality of sidewall recesses, the third plurality of sidewall recesses each defining at least a third depth that is between the first depth and the second depth.
Itou is silent regarding forming a third plurality of sidewall recesses in the sidewall of the substrate and extending along a third length of the sidewall between the first plurality of sidewall recesses and the second plurality of sidewall recesses, the third plurality of sidewall recesses each defining at least a third depth that is between the first depth and the second depth. Related art from Grivna teaches a Bosch process can be used to form scallops of increasing sizes to provide a tapered die sidewall shape which is advantageous as this avoids die collisions in pick-and-place operations (see Figs. 16-22 and ¶¶65-78). In view of Grivna, a PHOSITA would be motivated to modify Itou’s process to form scallops of increasing dimensions as the etch proceeds through the wafer to the tape to provide the benefits of reduced chipping and higher yield in subsequent pick-and -place operations. By adjusting the Bosch process to achieve larger and larger scallops as the depth increases to form the tapered profile, the third sidewall recesses will be formed as claimed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related Bosch etching, cleaning, and dicing processes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898