DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 05/22/2026 has been entered. Claims 1-20, remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over disclosed prior art, Meyer et al., (United States Patent Application Publication Number, US 2021/0233828 A1) hereinafter referenced as Meyer, in view of disclosed prior art, Im et al., (United States Patent Application Publication Number, US 2021/0249332 A1) hereinafter referenced as Im, and in view of Nakamura et al., United States Patent Application Publication Number, US 2014/0332951 A1) hereinafter referenced as Nakamura.
Regarding claim 1, Meyer teaches a semiconductor device module comprising: a ceramic substrate (Fig.1, element #11, paragraph [0039], row 7) having a first surface (Fig.1, top surface of element #11) and a second surface opposite the first surface (Fig.1, bottom surface of element #1); a patterned metal layer disposed on the first surface of the ceramic substrate (Fig.1, element #12, paragraph [0039], rows 10-17); a semiconductor die disposed on the patterned metal layer (Fig.1, element #4, paragraph [0004], rows 11-13); a cooling structure
having a first surface and a second surface opposite the first surface (Fig.1, first surface if the top surface of element #20, and second surface is the bottom surface of element #20),the first surface being bonded to the second surface of the ceramic substrate (Fig.1, top surface of element #20 is bonded to the bottom surface of element #11).
Meyer does not teach the first surface being directly bonded to the second surface of the ceramic substrate. Im teaches the first surface of the cooling structure being directly bonded to the second surface of the ceramic substrate (Fig.1, top surface of element #110 is directly bonded to the bottom surface of the ceramic substrate, element #120, paragraph [0026], rows 8-12). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Im and disclose the first surface of a cooling structure being directly bonded to the second surface of the ceramic substrate. As disclosed by Im, such implementation can improve the thermal dissipation performance as compared to other cooling approaches (paragraph [0023], rows 9-14).
Meyer further teaches the second surface defining a fluidic interface surface (Fig.1, bottom surface of element #20 has an inlet and an outlet, elements #32 and #31) and the cooling structure including a plurality of fluidic-cooling channels (Fig.1, elements #30, paragraph [0041], rows 8-10).
Im teaches a molding compound that: encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die (Fig.1, the molding compound, element #160 encapsulates the ceramic substrate, element #120, the patterned metal layer, element #130 and the die, element #150). The combination of Meyer and Im does not teach a molding compound that: encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and lateral sides of the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound. Nakamura teaches a molding compound encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and lateral sides of the cooling structure (Fig.9, element #76 encapsulates, the ceramic substrate, element #72, the patterned metal layer, element #73, the semiconductor die, element #74 and the lateral sides of the cooling structure, element #71). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Nakamura and disclose a molding compound encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and lateral sides of the cooling structure. The molding compound protects the encapsulated parts from degradation due to external environmental factors and increases the structural stability of the module.
Nakamura discloses the bottom surface of the cooling structure, which corresponds to the fluidic interface surface of Meyer, is the exposed by the molding compound. Therefore, the combination of Meyer and Nakamura teaches a fluidic interface surface of the cooling structure is exposed through the molding compound. Leaving the surface exposed from the molding compound allows the heat to dissipate away from the die and for inlets and the outlets disposed on the fluidic interface surface to be used for cooling fluid circulation.
Regarding claim 2, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claim 1 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 1, wherein the plurality of fluidic-cooling channels are configured to be in fluidic communication with a coolant distributor (Fig.2, element #40, paragraph [0041], rows 14-16).
Regarding claim 3, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claim 1 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 1, wherein the cooling structure includes a plurality of copper sheets defining the plurality of fluidic-cooling channels (paragraph [0033], rows 1-5 and paragraph [0034], rows 1-3).
Regarding claim 4, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claim 1 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 1, wherein a fluidic-cooling channel of the plurality of fluidic-cooling channels includes: an inlet portion; an outlet portion; and a U-turn portion that fluidically couples the inlet portion with the outlet portion (Fig.3 annotated below, bottom of elements #34 are the inlet and outlet portions respectively, element #33 is the U-turn portion, paragraph [0049], rows 1-5).
Regarding claim 5, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1 and 4 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 4, wherein: the inlet portion is arranged along a first axis and the outlet portion is arranged along a second axis, the first axis and the second axis being orthogonal to the second surface of the ceramic substrate (Fig.1, the inlet and outlet portions are arranged along vertical direction, and the second surface of the ceramic substrate is along horizontal direction) ; and the U-turn portion is arranged along a third axis that is parallel to the second surface of the ceramic substrate (Fig.1, the U-turn portion is arranged along the horizontal direction).
Regarding claim 6, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1 and 4 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 4, wherein: the inlet portion and the outlet portion are defined by a first plurality of copper sheets of the cooling structure (Fig.3, annotated below, copper sheets between the two doted lines); and the U-turn portion is defined by a second plurality of copper sheets of the cooling structure (Fig.3, annotated below, copper sheets above the top dotted line, paragraph [0022], rows 19-22).
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Regarding claim 7, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1, 4 and 6 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 6, wherein: the fluidic-cooling channel is a first fluidic-cooling channel (Fig.3, first fluidic channel is element #30 on the front side of the figure, the second fluidic channel is the one right behind it); the first plurality of copper sheets (sheets between the dotted lines in annotated Fig.3 above) further defines: a barrier between the inlet portion and the outlet portion of the first fluidic-cooling channel (Fig.3, the inlet and outlet portions, elements #34, are openings in the copper sheets, and the plurality of sheets between the dotted lines form a barrier between them, Fig.4 between the channels there is a copper barrier); and a first portion of a barrier between the inlet portion of the first fluidic-cooling channel and an inlet portion of a second fluidic-cooling channel (Fig.4, the first plurality of cooper sheets form a lower portion of a barrier between the inlets of the two channels furthermost to the right); and the second plurality of copper sheets (sheets above the top dotted line in annotated Fig.3 above) further defines a second portion of the barrier between the inlet portion of the first fluidic-cooling channel and the inlet portion of the second fluidic-cooling channel (Fig.4, the second plurality of cooper sheets, form a top portion of the barrier between the inlets of the two channels furthermost to the right).
Regarding claim 8, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1, 4, 6 and 7 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 7, wherein the inlet portion of the first fluidic-cooling channel is adjacent to the inlet portion of the second fluidic-cooling channel (Fig.4, the first and second channels are the ones furthermost to the right, their inlets are adjacent, connected to inlet part #41).
Regarding claim 9, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1, 4, 6 and 7 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 7, wherein: the first plurality of copper sheets (sheets between the dotted lines in annotated Fig.3 above) further defines a first portion of a barrier between the outlet portion of the first fluidic-cooling channel and an outlet portion of a second fluidic-cooling channel (Fig.4, the first plurality of cooper sheets, form a lower portion of a barrier between the outlets of the two channels furthermost to the right) and the second plurality of copper sheets (sheets above the top dotted line in annotated Fig.3 above) further defines a second portion of the barrier between the outlet portion of the first fluidic-cooling channel and the outlet portion of the second fluidic-cooling channel (Fig.4, the second plurality of cooper sheets, form a top portion of the barrier between the outlets of the two channels furthermost to the right).
Regarding claim 10, the combination of Meyer, Im and Nakamura teaches the semiconductor module of claims 1, 4, 6, 7 and 9 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 9, wherein the outlet portion of the first fluidic-cooling channel is adjacent to the outlet portion of the second fluidic-cooling channel (Fig.4, the first and second channels are the ones furthermost to the right, their outlets are adjacent, connected to outlet part #42).
Regarding claim 11, Meyer teaches an electronic device assembly comprising: a semiconductor device module (Fig.1, the entire structure) including: a ceramic substrate (Fig.1, element #11, paragraph [0039], row 7) having a first surface (Fig.1, top surface of element #1) and a second surface opposite the first surface (Fig.1, bottom surface of element #1); a patterned metal layer disposed on the first surface of the ceramic substrate (Fig.1, element #12, paragraph [0039], rows 10-17); a semiconductor die disposed on the patterned metal layer (Fig.1, element #4, paragraph [0004], rows 11-13); a cooling structure disposed on the second surface of the ceramic substrate (Fig.1, element #20, paragraph [0040], rows 1-2), the cooling structure including a plurality of stacked metal sheets defining a plurality of fluidic-cooling channels (paragraph [0041], rows 8-10), a first metal sheet of the stacked metal sheets (top metal sheet above the U-turn element #3, paragraph [0021], rows 15-18) being bonded to the second surface of the ceramic substrate (Fig.1, top surface of element #20 is bonded to the bottom surface of element #11).
Meyer does not teach the metal sheet is directly bonded to the second surface of the ceramic substrate without an adhesive. Im teaches the top layer of the cooling structure is directly bonded to the second surface of the ceramic substrate without an adhesive (Fig.1, top surface of element #110 is directly bonded to the bottom surface of the ceramic substrate, element #120, paragraph [0026], rows 8-12, 27-29). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Im and disclose the top layer of the cooling structure is directly bonded to the second surface of the ceramic substrate without an adhesive. As disclosed by Im, such implementation can improve the thermal dissipation performance as compared to other cooling approaches (paragraph [0023], rows 9-14).
Meyer does not teach a molding compound that: encapsulates the ceramic substrate, the patterned metal layer and the semiconductor die; and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound. Im teaches a molding compound that: encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die (Fig.1, the molding compound, element #160 encapsulates the ceramic substrate, element #120, the patterned metal layer, element #130 and the die, element #150). The combination of Meyer and Im does not teach a molding compound that: encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and partially encapsulates the cooling structure, such that a fluidic interface surface of the cooling structure is exposed through the molding compound. Nakamura teaches a molding compound encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and partially encapsulates the cooling structure (Fig.9, element #76 encapsulates, the ceramic substrate, element #72, the patterned metal layer, element #73, the semiconductor die, element #74 and the lateral sides of the cooling structure, element #71). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Nakamura and disclose a molding compound encapsulates the ceramic substrate, the patterned metal layer, the semiconductor die; and partially encapsulates the cooling structure. The molding compound protects the encapsulated parts from degradation due to external environmental factors and increases the structural stability of the module.
Meyer further teaches the bottom surface of the cooling structure defining a fluidic interface surface (Fig.1, bottom surface of element #20 has an inlet and an outlet, elements #32 and #31).Nakamura discloses the bottom surface of the cooling structure, which corresponds to the fluidic interface surface of Meyer, is the exposed by the molding compound. Therefore, the combination of Meyer and Nakamura teaches a fluidic interface surface of the cooling structure is exposed through the molding compound. Leaving the surface exposed from the molding compound allows the heat to dissipate away from the die and for inlets and the outlets disposed on the fluidic interface surface to be used for cooling fluid circulation.
Mayer further teaches a coolant distributor coupled with the fluidic interface surface of the cooling structure (Fig.7, element #40, paragraph [0053], rows 8-11 and 15-17, is coupled to the inlet and outlet portions of the fluidic channel and the bottom interface of the cooling structure).
Regarding claim 12, the combination of Meyer, Im and Nakamura teaches the electronic device assembly of claim 11 as set forth in the obviousness rejection. Meyer further teaches the electronic device assembly of claim 11, wherein: the plurality of fluidic-cooling channels include respective inlet portions, respective outlet portions, and respective U-turn portions, the respective U-turn portions fluidically coupling the respective inlet portions with the respective outlet portions (Fig.3, bottom of elements #34 are the inlet and outlet portions respectively, element #33 is the U-turn portion, paragraph [0049], rows 1-6); and the coolant distributor (Fig.8, element #40, paragraph [0053], rows 1-2 and paragraph [0054], rows 1-2) including: at least one coolant-inlet channel configured to provide a coolant flow to the respective inlet portions (Fig.8, element #41, paragraph [0054], row 4); and at least one coolant-outlet channel configured to receive the coolant flow from the respective outlet portions (Fig.8, element #42, paragraph [0054], row 4).
Regarding claim 13, the combination of Meyer, Im and Nakamura teaches the electronic device assembly of claims 11 and 12 as set forth in the obviousness rejection. Meyer further teaches the electronic device assembly of claim 12, wherein: a coolant-inlet channel of the at least one coolant-inlet channel includes a ramped portion having a first slope; and a coolant-outlet channel of the at least one coolant-outlet channel includes a ramped portion having a second slope opposite the first slope (paragraph [0054], rows 4-11).
Claims 14, 15 and 16 rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of Im, Nakamura and in view of De Sousa et al., (United States Patent Application Publication Number, US 2022/0015271 A1), hereinafter referenced as De Sousa.
Regarding claim 14, the combination of Meyer, Im and Nakamura teaches the electronic device assembly of claims 11 and 12 as set forth in the obviousness rejection. Meyer further teaches the electronic device assembly of claim 12, wherein: a coolant-inlet channel of the at least one coolant-inlet channel can include a fluidic-ingress port that is disposed on a first side of the coolant distributor; and a coolant-outlet channel of the at least one coolant-outlet channel can include a fluidic-egress port that is disposed on a second side of the coolant distributor (Fig.9, the ports are disposed on the side).
The combination of Meyer, Im and Nakamura does not teach the fluidic egress port is disposed on a second side opposite to the first side. De Sousa teaches a fluidic-ingress port that is disposed on a first side; and a fluidic-egress port that is disposed on a second side, opposite to the first side (Fig.6, the fluidic-ingress port is disposed to the left side and the fluidic-egress port is disposed to the right side). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of De Sousa and disclose a fluidic-ingress port that is disposed on a first side; and a fluidic-egress port that is disposed on a second side, opposite to the first side. This forces the fluid to flow the full length of the cooling structure which maximizes heat dissipation and helps distribute heat more evenly across the entire structure.
Regarding claim 15, the combination of Meyer, Im and Nakamura teaches the electronic device assembly of claim 11 as set forth in the obviousness rejection. The combination of Meyer, Im and Nakamura does not teach the electronic device assembly of claim 11, further comprising a fluidic-cooling jacket, at least the coolant distributor and an interface between the cooling structure and the coolant distributor being fluidically sealed in the fluidic-cooling jacket. De Sousa teaches the electronic device assembly, further comprising a fluidic-cooling jacket (Fig.2, element #10, paragraph [0037], row 1), at least the coolant distributor (Fig.2, element #21, paragraph [0037], row 1), and an interface between the cooling structure and the coolant distributor being fluidically sealed in the fluidic-cooling jacket (Fig.3, the cooling structure, element #22, paragraph [0037], rows 2-3 and the distributor, element #21 form a cooling chamber inside the jacket, with a gasket to prevent leaks, paragraph [0037], rows 21-22). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of De Sousa and disclose a fluidic-cooling jacket, at least the coolant distributor and an interface between the cooling structure and the coolant distributor being fluidically sealed in the fluidic-cooling jacket. As disclosed by De Sousa, the cooling jacket comprises the cooling fluid inlet and outlet, and includes flow pathways and passages that direct the cooling fluid to the distributor and the semiconductor dies.
Regarding claim 16, the combination of Meyer, Im and Nakamura teaches the electronic device assembly of claim 11 as set forth in the obviousness rejection and the combination of Meyer, Im, Nakamura and De Sousa teaches the electronic device assembly of claim 15 as set forth in the obviousness rejection. Meyer suggests the interface between the cooling structure and the coolant distributor is sealed (paragraph [0017], rows 10-12). The combination of Meyer, Im and Nakamura does not teach the electronic device assembly of claim 15, where the interface between the cooling structure and the coolant distributor includes a sealing member. De Sousa teaches, where the interface between the cooling structure and the coolant distributor includes a sealing member (Fig.2, interface the cooling structure, element #22, paragraph [0037], rows 2-3 and the distributor, element #21 includes a gasket element #19, to prevent leaks, paragraph [0037], rows 21-22). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of De Sousa and disclose where the interface between the cooling structure and the coolant distributor includes a sealing member. As disclosed by De Sousa, the sealing member ensures the coolant does not leak (paragraph [0037], rows 21-22)
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Meyer in view of disclosed prior art, Funakoshi et al., (United States Patent Application Publication Number, US 2009/0321924 A1), hereinafter referenced as Funakoshi, and in view of Nakamura.
Regarding claim 17, Meyer teaches a semiconductor device module comprising: a first ceramic substrate (Fig.1, element #11, paragraph [0039], row 7) having a first surface (Fig.1, top surface of element #11) and a second surface opposite the first surface (Fig.1, bottom surface of element #11); a first patterned metal layer disposed on the first surface of the first ceramic substrate (Fig.1, element #12, paragraph [0039], rows 1-17); a semiconductor die disposed on the first patterned metal layer (Fig.1, element #4, paragraph [0004], rows 11-13);
Meyer does not teach a second ceramic substrate having a first surface and a second surface opposite the first surface; a second patterned metal layer disposed on the first surface of the second ceramic substrate, the second patterned metal layer being disposed on the semiconductor die. Funakoshi teaches a second ceramic substrate (Fig.1, element #20, paragraph [0043], rows 1-2 and paragraph [0037], rows 1-3) having a first surface (Fig.1, bottom surface of element #20) and a second surface opposite the first surface (Fig.1, top surface of element #20); a second patterned metal layer disposed on the first surface of the second ceramic substrate (Fig.1, formed by element #21 and #22, paragraph [0038], rows 1-2), the second patterned metal layer being disposed on the semiconductor die (Fig.1, the patterned metal layer is disposed on the semiconductor die, element #1, paragraph [0039], row 3). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Funakoshi and disclose a second ceramic substrate having a first surface and a second surface opposite the first surface; a second patterned metal layer disposed on the first surface of the second ceramic substrate, the second patterned metal layer being disposed on the semiconductor die. As disclosed by Funakoshi, the second pattern layer provides electrical connections with semiconductor die terminals, while the second substrate allows connecting the semiconductor die with a top cooling structure to provide enhanced cooling of the device from both top and bottom sides.
Meyer teaches a first cooling structure disposed on the second surface of the first ceramic substrate (Fig.1, element #20, paragraph [0040], rows 1-2), the first cooling structure including a first plurality of fluidic-cooling channels (paragraph [0041], rows 8-10).
Meyer does not teach a second cooling structure disposed on the second surface of the second ceramic substrate, the second cooling structure including a second plurality of fluidic-cooling channels. Funakoshi teaches a second cooling structure disposed on the second surface of the second ceramic substrate (Fig.1, formed by elements #25, #26, #35, and #37 paragraph [0045], rows 1-2 and 7-8, is disposed on the top surface of element #20), the second cooling structure including a second plurality of fluidic-cooling channels (Fig.1, region between fins, element #35 form channels, elements #40). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Funakoshi and disclose a second cooling structure disposed on the second surface of the second ceramic substrate, the second cooling structure including a second plurality of fluidic-cooling channels. As disclosed by Funakoshi, the second cooling structure provides enhanced cooling of the semiconductor device.
Meyer does not teach and a molding compound that: encapsulates the first ceramic substrate, the first patterned metal layer, the semiconductor die, the second ceramic substrate and the second patterned metal layer; and partially encapsulates the first cooling structure and the second cooling structure, such that: a surface of the first cooling structure is exposed through and coplanar with a first surface of the molding compound; and a surface of the second cooling structure is exposed through and coplanar with a second surface of the molding compound opposite the first surface of the molding compound. Funakoshi teaches a molding compound that: encapsulates the first ceramic substrate, the first patterned metal layer, the semiconductor die, the second ceramic substrate and the second patterned metal layer; and partially encapsulates the first cooling structure and the second cooling structure (Fig.1, element #44, paragraph [0048], rows 6-7), such that: a surface of the first cooling structure is exposed through a first surface of the molding compound (Fig.1, top surface of element #26 is, and is exposed through the top surface of the molding compound); and a surface of the second cooling structure is exposed through a second surface of the molding compound opposite the first surface of the molding compound (Fig.1, bottom surface of element #19 is exposed through the bottom surface of the molding compound). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Funakoshi and disclose a molding compound that: encapsulates the first ceramic substrate, the first patterned metal layer, the semiconductor die, the second ceramic substrate and the second patterned metal layer; and partially encapsulates the first cooling structure and the second cooling structure, such that: a surface of the first cooling structure is exposed through a first surface of the molding compound; and a surface of the second cooling structure is exposed through a second surface of the molding compound opposite the first surface of the molding compound. The molding compound protects the two substrates, the metal patterns and the semiconductor die from degradation due to external environmental factors. Partially encapsulating the cooling structures together with the substrates and the die, increases the structural stability of the module, and leaving the surfaces exposed allows for heat to dissipate away from the die.
The combination of Meyer and Funakoshi does not teach a surface of the first cooling structure is exposed through and coplanar with a first surface of the molding compound; and a surface of the second cooling structure is exposed through and coplanar with a second surface of the molding compound. Nakamura teaches a surface of the first cooling structure is coplanar with a first surface of the molding compound (Fig.9, bottom surface of the cooling structure, element #71 is exposed and coplanar with the bottom surface of the molding compound). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Nakamura and disclose a surface of the first cooling structure is coplanar with a first surface of the molding compound. Having the exposed surface of the molding compound and the surface of cooling structure coplanar eliminates the presence of exposed cooling structure corners, that may be subject to mechanical damage. Same applies to the second cooling structure being coplanar with a second surface of the molding compound.
Regarding claim 18, the combination of Meyer, Funakoshi and Nakamura teaches the semiconductor device module of claim 17 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 17, wherein a fluidic-cooling channel of the first plurality of fluidic-cooling channels, or of the second plurality of fluidic-cooling channels includes: an inlet portion; an outlet portion; and a U-turn portion that fluidically couples the inlet portion with the outlet portion (Fig.3, bottom of elements #34 are the inlet and outlet portions respectively, element #33 is the U-turn portion, paragraph [0049], rows 1-5).
Regarding claim 19, the combination of Meyer, Funakoshi and Nakamura teaches the semiconductor device module of claims 17 and 18 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 18, wherein: the inlet portion is arranged along a first axis and the outlet portion is arranged along a second axis, the first axis and the second axis being orthogonal to the second surface of the first ceramic substrate (Fig.1, the inlet and outlet portions are arranged along vertical direction, and the second surface of the ceramic substrate is along horizontal direction); and the U-turn portion is arranged along a third axis that is parallel to the second surface of the first ceramic substrate (Fig.1, the U-turn portion is arranged along the horizontal direction).
Regarding claim 20, the combination of Meyer, Funakoshi and Nakamura teaches the semiconductor device module of claims 17 and 18 as set forth in the obviousness rejection. Meyer further teaches the semiconductor device module of claim 18, wherein: the inlet portion and the outlet portion are defined by a first plurality of copper sheets Fig.3, annotated above, copper sheets between the two doted lines); and the U-turn portion is defined by a second plurality of copper sheets (Fig.3, annotated above, copper sheets above the top dotted line, paragraph [0022], rows 19-22).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi et al. in view of Nakamura.
Regarding claim 17, Funakoshi teaches a semiconductor device module comprising: a first ceramic substrate (Fig.1, element #20, paragraph [0043], rows 1-2 and paragraph [0037], rows 1-3) having a first surface (Fig.1, bottom surface of element #20) and a second surface opposite the first surface (Fig.1, top surface of element #20); a first patterned metal layer disposed on the first surface of the first ceramic substrate (Fig.1, formed by elements #21 and #22, paragraph [0038], rows 1-2); a semiconductor die disposed on the first patterned metal layer (Fig.1, element #1, paragraph [0039], row 3) ; a second ceramic substrate (Fig.1, element #14, paragraph [0037], rows 1-3) having a first surface a(Fig.1, top surface of element #14) and a second surface opposite the first surface (Fig.1, bottom surface of element #14); a second patterned metal layer disposed on the first surface of the second ceramic substrate (Fig.1, formed by elements #15 and #27, paragraph [0039], rows 405), the second patterned metal layer being disposed on the semiconductor die (Fig.1, elements #15 and #27 are disposed on the bottom of element #1); a first cooling structure disposed on the second surface of the first ceramic substrate (Fig.1, formed by elements #25, #26, #35, and #37 paragraph [0045], rows 1-2 and 7-8), the first cooling structure including a first plurality of fluidic-cooling channels (Fig.1, region between fins, element #35 form channels, elements #40); a second cooling structure disposed on the second surface of the second ceramic substrate Fig.1, formed by elements #18, #19, #32, and #34 paragraph [0040], rows 1-2 and 7-8), the second cooling structure including a second plurality of fluidic-cooling channels (Fig.1, region between fins element #32 form channels, elements #40); and a molding compound that: encapsulates the first ceramic substrate, the first patterned metal layer, the semiconductor die, the second ceramic substrate and the second patterned metal layer; and partially encapsulates the first cooling structure and the second cooling structure (Fig.1, element #44, paragraph [0048], rows 6-7), such that: a surface of the first cooling structure is exposed through a first surface of the molding compound (Fig.1, top surface of element #26 is exposed through the bottom surface of the molding compound, element #44); and a surface of the second cooling structure is exposed through a second surface of the molding compound opposite the first surface of the molding compound (Fig.1, bottom surface of element #19 is exposed through the bottom surface of the molding compound, element #44).
Funakoshi does not teach a surface of the first cooling structure is coplanar with a first surface of the molding compound and a surface of the second cooling structure is coplanar with a second surface of the molding compound. Nakamura teaches a surface of the first cooling structure is coplanar with a first surface of the molding compound (Fig.9, bottom surface of the cooling structure, element #71 is exposed and coplanar with the bottom surface of the molding compound. It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Nakamura and disclose a surface of the first cooling structure is coplanar with a first surface of the molding compound. Embedding the cooling structure in the molding compound increases the mechanical stability of the device, while exposing the surface of the cooling structure allows heat to dissipate away from the die. Furthermore, having the exposed surface of the molding compound and the surface of cooling structure coplanar eliminates the presence of exposed cooling structure corners, that may be subject to mechanical damage. Same applies to the second cooling structure being coplanar with a second surface of the molding compound.
Response to Arguments
Applicant’s arguments filed on 05/22/2026 have been fully considered but they
are not persuasive. Applicant’s arguments with respect to claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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