DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 20, 30-31 and 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) in view of CHENG (US 20230154925).
Regarding claim 17, CHUNG discloses a method (the method as shown in fig 1-17, see para 14-44), comprising:
providing a workpiece (the method shown in fig 7A, see para 25) comprising:
a substrate (the method shown in fig 2 which is used as a substrate for the growth of 210 which comprises 202, 204 and 206, see fig 2, para 18) comprising a well region having a first doping polarity (206 can be an n-type region, see fig 2, para 18),
a vertical stack (the layer stack 210, see fig 3, para 19) of alternating channel layers (channel layers 210B, see fig 3, para 19) and sacrificial layers (sacrificial layers 210A, see fig 3, para 19) over and in direct contact with the well region (210 is over and in direct contact with 206, see fig 3), and
a dummy gate stack (the stack of layers 225 comprising 220, 222 and 224, see fig 6-7, para 24) intersecting with the vertical stack (225 and 210 intersect, see fig 7),
recessing portions of the vertical stack not covered by the dummy gate stack to form source/drain trenches (the source/drain trenches 228 are formed by recessing 210, see fig 9, para 27), the source/drain trenches exposing the well region (228 exposes 206, see fig 9);
forming a dielectric layer to fill a lower portion of the source/drain trenches (the SiO dielectric layer 230 is formed from which fills at least a lower portion of 228, see fig 11, para 29);
forming source/drain features (the source/drain features 240 formed in 228 and directly on 230, see fig 12, para 31) on the dielectric layer to fill an upper portion of the source/drain trenches (240 fills an upper portion of 228, see fig 11-12), the source/drain features comprising the first doping polarity (240 can be n-doped, see fig 12, para 31);
selectively removing the dummy gate stack to form a gate trench (220 and 222 are removed to form trench 256, see fig 14, para 33);
selectively removing the sacrificial layers of the vertical stack to form gate openings (210A is removed to form 256 in fig 15, see para 34); and
forming a gate structure in the gate trench and gate openings (260 is formed in the openings, see fig 16, para 37).
CHUNG fails to explicitly disclose a method for forming a varactor.
CHENG teaches a method for forming a varactor (the method of fig 1-7 which uses the same process steps for form the FET devices on the left in fig 7 and the varactor on the right in fig 7 with the S/D regions linked together, see para 29-52).
CHUNG and CHENG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the varactor use of the device as CHENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the varactor use of the device as CHENG in order to make an NFET or PFET based varactor (See CHENG para 2).
Regarding claim 20, CHUNG and CHENG disclose the method of claim 17.
CHUNG further discloses a method, wherein the well region and the source/drain features are N-type features (206 and 240 can be n-type, see fig 12, para 18 and 31), and wherein the forming of the gate structure comprises:
conformally depositing a gate dielectric layer (fig 16, 264, para 37) over the workpiece; and
conformally depositing an N-type work function layer (266 can be a work function layer, see fig 16, para 41) over the gate dielectric layer.
Regarding claim 30, CHUNG discloses a method (the method as shown in fig 1-17, see para 14-44), comprising:
forming an active region (the fin comprising 202', 204, 206 and 210 over 202, see fig 4, para 22) over a substrate (the substrate 202, see fig 4, para 22), the active region comprising a base fin (the fin comprising 202', 204 and 206 over 202 in fig 4, see para 22) and a plurality of channel layers (channel layers 210B, see fig 4-5, para 19) interleaved by a plurality of sacrificial layers (the sacrificial layers 210B, see fig 4-5, para 19) over the base fin, wherein a top portion of the base fin is doped with dopants having a first doping polarity (206, which is a top portion of the base fin, can be n-doped, see fig 4, para 18);
forming an isolation feature adjacent to the active region (218 is formed adjacent to 202'-210, see fig 5, para 23);
forming a trench extending through the plurality of channel layers and the plurality of sacrificial layers (the source/drain trench 228, see fig 9B, para 27), wherein the trench exposes the top portion of the base fin (the trench 228 exposes a top surface of 206, see fig 9, para 26-27);
forming an insulation layer in the trench (insulator 230 is formed in 228, see fig 11, para 29);
epitaxially forming a semiconductor feature over the insulation layer and in the trench (epi feature 240 is formed in the trench 228 and over the isolation region 218, see fig 12, para 30), wherein the semiconductor feature is doped with dopants having the first doping polarity (240 can be n-doped, see fig 12, para 31);
selectively removing the plurality of sacrificial layers (210 are removed selectively, see fig 15, para 34-35); and
forming a gate structure (260 is formed in the openings, see fig 16, para 37) wrapping around and over the plurality of channel layers (260 wraps around 210B, see fig 16B), wherein the gate structure comprises a gate dielectric layer (fig 16, 264, para 37) and a gate electrode (fig 16, 266, para 40) over the gate dielectric layer.
CHUNG fails to explicitly disclose a method for forming a varactor.
CHENG teaches a method for forming a varactor (the method of fig 1-7 which uses the same process steps for form the FET devices on the left in fig 7 and the varactor on the right in fig 7 with the S/D regions linked together, see para 29-52).
CHUNG and CHENG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the varactor use of the device as CHENG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the varactor use of the device as CHENG in order to make an NFET or PFET based varactor (See CHENG para 2).
Regarding claim 31, CHUNG and CHENG disclose the method of claim 30.
CHUNG further discloses, wherein a portion of the insulation layer extends on a top surface of the isolation feature (230 is at least indirectly on a top surface of 218, see fig 16).
Regarding claim 34, CHUNG and CHENG disclose the method of claim 30.
CHUNG further discloses, wherein the trench does not extend through the top portion of the base fin (228 does not extend through 206, since its bottom terminates inside 206, see fig 11).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) and CHENG (US 20230154925) further in view of RACHMADY (US 20200294969).
Regarding claim 18, CHUNG and CHENG disclose the method of claim 17.
CHUNG further discloses a method, wherein the forming of the dielectric layer comprises:
depositing a dielectric material layer over the workpiece (the dielectric layer which will be formed into 230 formed by CVD along the entire sidewalls of 228 and 226, see fig 11, para 29), the dielectric material layer comprising a first portion filling the lower portion of the source/drain trenches (the portion of the dielectric layer that is removed to expose the sides of 210B, see fig 11, para 29); and
recessing the first portion of the dielectric material layer, thereby forming the dielectric layer (the removal of the part of the dielectric layer that is removed along sidewalls of 210B to form 230, see fig 11, para 29).
CHUNG fails to explicitly disclose a method comprising depositing a dielectric material layer over the workpiece, the dielectric material layer comprising a first portion filling the lower portion of the source/drain trenches, a second portion directly over the dummy gate stack, and a third portion extending along sidewalls of the source/drain trenches; and
removing the second portion and third portion of the dielectric material layer thereby forming the dielectric layer.
RACHMADY teaches a method comprising depositing a dielectric material layer (fig 9, 152, para 24) over the workpiece, the dielectric material layer comprising a first portion filling the lower portion of the source/drain trenches (the portion of 152 below 106-2, see fig 9 and 10, para 24), a second portion directly over the dummy gate stack (the portion of 152 above 114, see fig 9 and 10, para 24), and a third portion extending along sidewalls of the source/drain trenches (the portion of 152 along sidewalls of 106-2 and above, see fig 9 and 10, para 152); and
removing the second portion and third portion of the dielectric material layer, thereby forming the dielectric layer (all the portions of 152 above 154 are removed, see fig 11, para 40).
CHUNG, CHENG and RACHMADY are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the second and third dielectric material portions of RACHMADY because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the second and third dielectric material portions of RACHMADY in order to make a device with low contact resistance (see RACHMADY para 22).
Claim(s) 19, 32 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) and CHENG (US 20230154925) further in view of CHIANG (US 20200294863).
Regarding claim 19, CHUNG and CHENG disclose the method of claim 17.
CHUNG fails to explicitly disclose a method, wherein the workpiece further comprises:
an isolation feature disposed between the vertical stack and another vertical stack of alternating channel layers and sacrificial layers,
wherein a portion of the dielectric layer is disposed directly on the isolation feature.
CHIANG teaches a method, wherein the workpiece further comprises:
an isolation feature (fig 2H, 107, para 17) disposed between the vertical stack and another vertical stack of alternating channel layers and sacrificial layers (107 is disposed between stacks 106, see fig 2D, para 17),
wherein a portion of the dielectric layer is disposed directly on the isolation feature (dielectric 136 is formed directly on 107, see fig 2H, para 33).
CHUNG, CHENG and CHIANG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the isolation geometry of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the isolation geometry of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Regarding claim 32, CHUNG and CHENG disclose the method of claim 30.
CHUNG fails to explicitly disclose a method, further comprising:
before the forming of the insulation layer, forming an undoped semiconductor layer in the trench.
CHIANG teaches a method, further comprising:
before the forming of the insulation layer, forming an undoped semiconductor layer in the trench (undoped semiconductor 242, see fig 13, para 35).
CHUNG, CHENG and CHIANG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the undoped semiconductor of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the undoped semiconductor of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Regarding claim 33, CHUNG and CHENG disclose the method of claim 30.
CHUNG fails to explicitly disclose a method, wherein a top surface of the isolation feature is above a dopant boundary of the top portion of the base fin.
CHIANG teaches a method, wherein a top surface of the isolation feature is above a dopant boundary of the top portion of the base fin (a top surface of isolation 107 is above a top surface of the fin 102F, see fig 2G, para 17).
CHUNG, CHENG and CHIANG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the isolation geometry of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the isolation geometry of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Claim(s) 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) and CHENG (US 20230154925) further in view of LIN (US 20210202497).
Regarding claim 35, CHUNG and CHENG disclose the method of claim 30.
CHUNG fails to explicitly disclose a method, further comprising:
forming inner spacer features configured to provide isolation between the gate structure and the semiconductor feature.
LIN teaches a method, further comprising:
forming inner spacer features configured to provide isolation between the gate structure and the semiconductor feature (fig 1G, 720, para 43).
CHUNG, CHENG and LIN are analogous art because they both are directed towards methods of making nanochannel semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the inner spacers of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the inner spacers of LIN in order to increase device density (see LIN para 93).
Regarding claim 36, CHUNG and CHENG disclose the method of claim 35.
CHUNG fails to explicitly disclose a method, wherein a top surface of the insulation layer is below a top surface of a bottommost inner spacer feature of the inner spacer features.
LIN teaches a method, wherein a top surface of the insulation layer is below a top surface of a bottommost inner spacer feature of the inner spacer features (at top surface of insulation layer 510 is below the top surface of the bottommost 720, see fig 1G).
CHUNG, CHENG and LIN are analogous art because they both are directed towards methods of making nanochannel semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG and CHENG with the inner spacers of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG and CHENG with the inner spacers of LIN in order to increase device density (see LIN para 93).
Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (US 20200294969) in view of CHUNG (US 20210098634).
Regarding claim 21, RACHMADY discloses a method, comprising:
forming a fin-shaped structure (fin 146, see fig 3, para 42) extending over a doped region in a substrate (the substrate 102 can be p-doped, so any region of 102 is a doped region, see fig 3, para 19) and extending lengthwise along a first direction (146 extend lengthwise along the horizontal direction in fig 3B), the fin-shaped structure comprising a channel region (the central region of the fin which is not etched between trenches 148, see fig 7, para 36), a first source/drain region (the region of the fin what will be etched to form left trench 148, see fig 7, para 36), and a second source/drain region (the region of the fin what will be etched to form right trench 148, see fig 7, para 36) adjacent to the channel region;
forming a dummy gate stack (the stack 110, 112 and 114, see fig 4, para 33) over the fin-shaped structure, the dummy gate stack extending lengthwise along a second direction different from the first direction (the dummy gate stack extends lengthwise in the horizontal direction in fig 5A, see para 34);
forming a first trench extending through the first source/drain region (left trench 148, see fig 7, para 36) and a second trench extending through the second source/drain region (right trench 148, see fig 7, para 36), the first trench and the second trench each exposing the doped region (the trenches 148 both expose a top surface of the substrate 102 which is doped, see fig 7B);
depositing a dielectric layer (152 can be a dielectric such as aluminum oxide, see fig 9, para 24) in the first and second trenches (152 is in the trenches 148, see fig 9) and on the doped region (152 is at least indirectly on 102, see fig 9);
after the deposition of the dielectric layer, forming a first epitaxial feature in the first trench (left epitaxial material 118-2, see fig 14, para 22 and 25) and a second epitaxial feature in the second trench (right epitaxial material 118-2, see fig 14, para 22 and 25), wherein the first and second epitaxial features and the doped region have a same doping polarity (118-2 can be p-doped, see fig 14, para 22), wherein the first and second epitaxial features are vertically spaced apart from the doped region by the dielectric layer (118-2 are spaced apart from doped region 102 by 152, see fig 14), and
replacing the dummy gate stack with a gate structure (the dummy gate stack is replaced by 122 and 124, see fig 16 and 17, para 26).
RACHMADY fails to explicitly disclose a method comprising forming an isolation feature alongside the fin-shaped structure;
wherein the first epitaxial feature overhangs the isolation feature.
CHUNG teaches a method comprising forming an isolation feature (fig 5A, 218, para 23) alongside the fin-shaped structure (fig 5, 202, para 23);
wherein the first epitaxial feature overhangs the isolation feature (epitaxial feature 240 overlaps 218 along the z-axis, see fig 12A, para 30).
RACHMADY and CHUNG are analogous art because they both are directed towards methods of making nanochannel FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the isolation feature geometry of CHUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the isolation feature geometry of CHUNG in order to improve performance (see CHUNG para 45).
Regarding claim 22, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY further discloses a method, wherein the channel region comprises a plurality of channel layers (fig 3, 106-2, para 20) interleaved by a plurality of sacrificial layers (fig 3, 104, para 31), and the method further comprises:
after the forming of the first and second epitaxial features, selectively removing the plurality of sacrificial layers (104 is removed, see fig 15, para 43), wherein the gate structure further wraps around the plurality of channel layers (124 wraps around 106, see fig 17, para 45).
Regarding claim 23, RACHMADY and CHUNG disclose the method of claim 22.
RACHMADY further discloses a method, further comprising:
forming inner spacer features between the gate structure and the first and second epitaxial features (spacers 116 are between 106 and 118, see fig 14, para 27).
Regarding claim 24, RACHMADY and CHUNG disclose the method of claim 23.
RACHMADY further discloses a method, wherein the dielectric layer and the inner spacer features comprise different compositions (116 can be SiON and 152 can be AlO, see para 27 and 24).
Regarding claim 25, RACHMADY and CHUNG disclose the method of claim 22.
RACHMADY further discloses a method, wherein a top surface of the dielectric layer is below a bottom surface of a bottommost channel layer of the plurality of channel layers (a top surface of 152 extends below a bottom surface of the bottom-most 106-2, see fig 14, para 24).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (US 20200294969) and CHUNG (US 20210098634) in view of TSUI (US 20210118882).
Regarding claim 26, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, further comprising:
forming conductive features over the first and second epitaxial features to electrically couple the first epitaxial feature to the second epitaxial feature.
TSUI teaches a method, further comprising:
forming conductive features over the first and second epitaxial features to electrically couple the first epitaxial feature to the second epitaxial feature (metal line 74 connects 62 and 63, see fig 6, para 21).
RACHMADY, CHUNG and TSUI are analogous art because they both are directed towards methods of making GAA FET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY and CHUNG with the conductive features of TSUI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY and CHUNG with the conductive features of TSUI in order to enhance circuit performance (see TSUI para 47).
Claim(s) 27is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (US 20200294969) and CHUNG (US 20210098634) in view of CHOI (US 20230084804).
Regarding claim 27, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, wherein the dielectric layer is formed of an oxygen-free dielectric material.
CHOI teaches a method, wherein the dielectric layer is formed of an oxygen-free dielectric material (dielectric 105 can be SiN, see fig 6, para 65).
RACHMADY, CHUNG and CHOI are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY and CHUNG with the oxygen free dielectric of CHOI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY and CHUNG with the oxygen free dielectric of CHOI in order to improve performance (see CHOI para 70).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (US 20200294969) and CHUNG (US 20210098634) in view of CHIANG (US 20200294863).
Regarding claim 28, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, wherein a portion of the dielectric layer is disposed directly on the isolation feature.
CHIANG teaches a method, wherein a portion of the dielectric layer is disposed directly on the isolation feature (dielectric 136 is formed directly on 107, see fig 2H, para 33).
RACHMADY, CHUNG and CHIANG are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY and CHUNG with the dielectric layer geometry of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY and CHUNG with the dielectric layer geometry of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (US 20200294969) and CHUNG (US 20210098634) in view of CHANG (US 20210375864).
Regarding claim 29, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, further comprising:
before the deposition of the dielectric layer, forming undoped semiconductor layers in the first and second trenches.
CHANG teaches a method, further comprising:
before the deposition of the dielectric layer, forming undoped semiconductor layers in the first and second trenches (undoped semiconductor 242 formed in all the trenches, see fig 13, para 35).
RACHMADY, CHUNG and CHANG are analogous art because they both are directed towards methods of making semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY and CHUNG with the dielectric layer geometry of CHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY and CHUNG with the dielectric layer geometry of CHANG in order to benefit the formation of the other epitaxial layers (see CHANG para 35).
Response to Arguments
Applicant’s arguments with respect to claim(s) 17 and 30 have been considered but are moot because the new ground of rejection does not rely the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 21 have been fully considered but they are not persuasive.
Regarding claim 21, the applicant argues that RACHMADY does not disclose a method wherein the dielectric layer 152 is on the doped region 102 because 152 and 102 are spaced apart from each other in fig 12B of RACHMADY. This argument is unpersuasive because the word “on” does not require direct contact. “On” is used as a function word to indicate position in close proximity with (definition taken from Merriam Webster on 7/27/2026), thus there can be intervening layers between two layers that are “on” each other. The office notes that RACHMADY does not disclose a device wherein the dielectric layer is directly on the doped region, but the claims does not currently require this.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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