DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the method of claims 17-20 in the reply filed on 1/7/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17, 20, 30-31 and 34 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHUNG (US 20210098634).
Regarding claim 17, CHUNG discloses a method, comprising:
providing a workpiece (the device shown in figs 17, see para 43) comprising:
a substrate comprising a well region having a first doping polarity (the substrate 202, 204 and 206 includes n-doped layer 206 which is part of an n-well, see fig 2, para 18) ,
a vertical stack (fig 3, 210, para 19) of alternating channel layers (fig 3, 210B, para 19) and sacrificial layers (fig 3, 210A, para 19) over and in direct contact with the well region (210 is over and in direct contact with 206, see fig 3), and
a dummy gate stack (the stack 225 comprising 220, 222 and 224, see fig 7, para 24) intersecting with the vertical stack,
recessing portions of the vertical stack not covered by the dummy gate stack to form source/drain trenches (the trenches 228 formed on either side of 226, see fig 9, para 27), the source/drain trenches exposing the well region (228 exposes 206, see fig 9);
forming a dielectric layer to fill a lower portion of the source/drain trenches (the dielectric 230 which fills lower portions 229 of trench 228, see fig 10-11, para 28);
forming source/drain features on the dielectric layer to fill an upper portion of the source/drain trenches, the source/drain features comprising the first doping polarity (240 can be an n-type epitaxial layer formed as an S/D structure, see fig 12, para 31);
selectively removing the dummy gate stack to form a gate trench (222 is removed to form gate trench 256, see fig 14, para 33);
selectively removing the sacrificial layers of the vertical stack to form gate openings (210A are removed to form the gate openings, see fig 15, para 34); and
forming a gate structure in the gate trench and gate openings (gate stack 260, see fig 16, para 37).
Regarding claim 20, CHUNG discloses the method of claim 17, wherein the well region and the source/drain features are N-type features (206 and 240 can be n-type, see fig 12, para 18 and 31), and wherein the forming of the gate structure comprises:
conformally depositing a gate dielectric layer (fig 16, 264, para 37) over the workpiece; and
conformally depositing an N-type work function layer (266 can be a work function layer, see fig 16, para 41) over the gate dielectric layer.
Regarding claim 30, CHUNG discloses a method, comprising:
forming an active region (the fin 202' and layers 204, 206 and 210, see fig 4, para 22) over a substrate (substrate 202, see fig 4C, para 22), the active region comprising a base fin (the fin 202', see fig 4, para 22) and a plurality of channel layers (210B, see fig 5, para 22) interleaved by a plurality of sacrificial layers (210A, see fig 5, para 22) over the base fin, wherein a top portion of the base fin is doped with dopants having a first doping polarity (206 can be n-doped, see fig 2, para 18);
forming an isolation feature (fig 5, 218, para 23) adjacent to the active region;
forming a trench (S/D trench 228, see fig 9, para 27) extending through the plurality of channel layers and the plurality of sacrificial layers, wherein the trench exposes the top portion of the base fin (228 exposes a top surface of 206, see fig 9);
forming an insulation layer in the trench (230 is formed in the trench, see fig 11, para 28);
epitaxially forming a semiconductor feature over the insulation layer and in the trench (epi semiconductor layer 240, see fig 12, para 30), wherein the semiconductor feature is doped with dopants having the first doping polarity (240 can be n-doped, see para 30);
selectively removing the plurality of sacrificial layers (210A is removed to form 256, see fig 15, para 34); and
forming a gate structure wrapping around and over the plurality of channel layers (260 wraps around 210B, see fig 16, para 37), wherein the gate structure comprises a gate dielectric layer (fig 16, 264, para 37) and a gate electrode (fig 16, 266, para 37) over the gate dielectric layer.
Regarding claim 31, CHUNG discloses the method of claim 30, wherein a portion of the insulation layer extends on a top surface of the isolation feature (230 is above and at least indirectly on a top surface of isolation 218, see fig 14, para 28).
Regarding claim 34, CHUNG discloses the method of claim 30, wherein the trench does not extend through the top portion of the base fin (the trench 228 does not extend through 206 to 202, see fig 9C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) in view of RACHMADY (UD 20200294969).
Regarding claim 18, CHUNG discloses the method of claim 17.
CHUNG fails to explicitly disclose a method, wherein the forming of the dielectric layer comprises:
depositing a dielectric material layer over the workpiece, the dielectric material layer comprising a first portion filling the lower portion of the source/drain trenches, a second portion directly over the dummy gate stack, and a third portion extending along sidewalls of the source/drain trenches; and
removing the second portion and third portion of the dielectric material layer, thereby forming the dielectric layer.
RACHMADY teaches a method, wherein the forming of the dielectric layer comprises:
depositing a dielectric material layer (fig 9, 152, para 24) over the workpiece, the dielectric material layer comprising a first portion filling the lower portion of the source/drain trenches (the portion of 152 below 106-2, see fig 9 and 10, para 24), a second portion directly over the dummy gate stack (the portion of 152 above 114, see fig 9 and 10, para 24), and a third portion extending along sidewalls of the source/drain trenches (the portion of 152 along sidewalls of 106-2 and above, see fig 9 and 10, para 152); and
removing the second portion and third portion of the dielectric material layer, thereby forming the dielectric layer (all the portions of 152 above 154 are removed, see fig 11, para 40).
CHUNG and RACHMADY are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the dielectric material formation method of RACHMADY because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the dielectric material formation method of RACHMADY in order to make a device with low contact resistance (see RACHMADY para 22).
Claim(s) 19 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) in view of CHIANG (US 20200294863).
Regarding claim 19, CHUNG discloses the method of claim 17.
CHUNG fails to explicitly disclose a method, wherein the workpiece further comprises:
an isolation feature disposed between the vertical stack and another vertical stack of alternating channel layers and sacrificial layers,
wherein a portion of the dielectric layer is disposed directly on the isolation feature.
CHIANG teaches a method, wherein the workpiece further comprises:
an isolation feature (fig 2H, 107, para 17) disposed between the vertical stack and another vertical stack of alternating channel layers and sacrificial layers (107 is disposed between stacks 106, see fig 2D, para 17),
wherein a portion of the dielectric layer is disposed directly on the isolation feature (dielectric 136 is formed directly on 107, see fig 2H, para 33).
CHUNG and CHIANG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the isolation features of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the isolation features of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Regarding claim 33, CHUNG discloses the method of claim 30.
CHUNG fails to explicitly disclose a method, wherein a top surface of the isolation feature is above a dopant boundary of the top portion of the base fin.
CHIANG teaches a method, wherein a top surface of the isolation feature is above a dopant boundary of the top portion of the base fin (a top surface of isolation 107 is above a top surface of the fin 102F, see fig 2G, para 17).
CHUNG and CHIANG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the isolation features of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the isolation features of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Claim(s) 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (UD 20200294969) in view of CHUNG (US 20210098634).
Regarding claim 21, RACHMADY discloses a method, comprising:
forming a fin-shaped structure (fin 146, see fig 3, para 42) extending over a doped region (the substrate 102 can be p-doped, see fig 3, para 19) and extending lengthwise along a first direction (146 extend lengthwise along the horizontal direction in fig 3B), the fin-shaped structure comprising a channel region (the central region of the fin which is not etched between trenches 148, see fig 7, para 36), a first source/drain region (the region of the fin that will be etched to form left trench 148, see fig 7, para 36), and a second source/drain region (the region of the fin that will be etched to form right trench 148, see fig 7, para 36) adjacent to the channel region;
forming a dummy gate stack (the stack 110, 112 and 114, see fig 4, para 33) over the fin-shaped structure, the dummy gate stack extending lengthwise along a second direction different from the first direction (the dummy gate stack extends lengthwise in the horizontal direction in fig 5A, see para 34);
forming a first trench extending through the first source/drain region (left trench 148, see fig 7, para 36) and a second trench extending through the second source/drain region (right trench 148, see fig 7, para 36);
depositing a dielectric layer (152 can be a dielectric such as aluminum oxide, see fig 9, para 24) in the first and second trenches;
after the deposition of the dielectric layer, forming a first epitaxial feature in the first trench (left epitaxial material 118-2, see fig 14, para 22 and 25) and a second epitaxial feature in the second trench (right epitaxial material 118-2, see fig 14, para 22 and 25), wherein the first and second epitaxial features and the doped region have a same doping polarity (118-2 can be p-doped, see fig 14, para 22), wherein the first and second epitaxial features are vertically spaced apart from the doped region by the dielectric layer (118-2 are spaced apart from doped region 102 by 152, see fig 14), and
replacing the dummy gate stack with a gate structure (the dummy gate stack is replaced by 122 and 124, see fig 16 and 17, para 26).
RACHMADY fails to explicitly disclose a method comprising forming an isolation feature alongside the fin-shaped structure,
wherein the first epitaxial feature overhangs the isolation feature.
CHUNG teaches a method comprising forming an isolation feature (fig 5A, 218, para 23) alongside the fin-shaped structure (fig 5, 202, para 23),
wherein the first epitaxial feature overhangs the isolation feature (epitaxial feature 240 overlaps 218 along the z-axis, see fig 12A, para 30).
RACHMADY and CHUNG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the isolation feature of CHUNG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the isolation feature of CHUNG in order to achieve desired tensile stress and/or compressive stress in the channel regions (see CHUNG para 31).
Regarding claim 22, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY further discloses a method, wherein the channel region comprises a plurality of channel layers (fig 3, 106-2, para 20) interleaved by a plurality of sacrificial layers (fig 3, 104, para 31), and the method further comprises:
after the forming of the first and second epitaxial features, selectively removing the plurality of sacrificial layers (104 is removed, see fig 15, para 43), wherein the gate structure further wraps around the plurality of channel layers (124 wraps around 106, see fig 17, para 45).
Regarding claim 23, RACHMADY and CHUNG disclose the method of claim 22.
RACHMADY further discloses a method, further comprising:
forming inner spacer features between the gate structure and the first and second epitaxial features (spacers 116 are between 106 and 118, see fig 14, para 27).
Regarding claim 24, RACHMADY and CHUNG disclose the method of claim 23.
RACHMADY further discloses a method, wherein the dielectric layer and the inner spacer features comprise different compositions (116 can be SiON and 152 can be AlO, see para 27 and 24).
Regarding claim 25, RACHMADY and CHUNG disclose the method of claim 22.
RACHMADY further discloses a method, wherein a top surface of the dielectric layer is below a bottom surface of a bottommost channel layer of the plurality of channel layers (a top surface of 152 extends below a bottom surface of the bottom-most 106-2, see fig 14, para 24).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (UD 20200294969) in view of CHUNG (US 20210098634) and further in view of TSUI (US 20210118882).
Regarding claim 26, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, further comprising:
forming conductive features over the first and second epitaxial features to electrically couple the first epitaxial feature to the second epitaxial feature.
TSUI teaches a method, further comprising:
forming conductive features over the first and second epitaxial features to electrically couple the first epitaxial feature to the second epitaxial feature (metal line 74 connects 62 and 63, see fig 6, para 21).
RACHMADY and TSUI are analogous art because they both are directed towards methods of making nanowire transistor methods and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the conductive feature of TSUI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the conductive feature of TSUI in order to enhance circuit performance (see TSUI para 47).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (UD 20200294969) in view of CHUNG (US 20210098634) and further in view of CHOI (US 20230084804).
Regarding claim 27, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, wherein the dielectric layer is formed of an oxygen-free dielectric material.
CHOI teaches a method, wherein the dielectric layer is formed of an oxygen-free dielectric material (dielectric 105 can be SiN, see fig 6, para 65).
RACHMADY and CHOI are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the dielectric material of CHOI because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the dielectric material of CHOI in order to improve performance (see CHOI para 70).
Claim(s) 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (UD 20200294969) in view of CHUNG (US 20210098634) and further in view of CHIANG (US 20200294863).
Regarding claim 28, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, wherein a portion of the dielectric layer is disposed directly on the isolation feature.
CHIANG teaches a method, wherein a portion of the dielectric layer is disposed directly on the isolation feature (dielectric 136 is formed directly on 107, see fig 2H, para 33).
RACHMADY and CHIANG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the isolation feature geometry of CHIANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the isolation feature geometry of CHIANG in order to save a cell height budget of the device (see CHANG para 15).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over RACHMADY (UD 20200294969) in view of CHUNG (US 20210098634) and further in view of CHANG (US 20210375864).
Regarding claim 29, RACHMADY and CHUNG disclose the method of claim 21.
RACHMADY fails to explicitly disclose a method, further comprising:
before the deposition of the dielectric layer, forming undoped semiconductor layers in the trenches.
CHANG teaches a method, further comprising:
before the forming of the insulation layer, forming an undoped semiconductor layer in the trench (undoped semiconductor 242, see fig 13, para 35).
RACHMADY and CHANG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of RACHMADY with the undoped semiconductor of CHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of RACHMADY with the undoped semiconductor of CHANG in order to benefit the formation of the other epitaxial layers (see CHANG para 35).
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) in view of CHANG (US 20210375864).
Regarding claim 32, CHUNG discloses the method of claim 30.
CHUNG fails to explicitly disclose a method, further comprising:
before the forming of the insulation layer, forming an undoped semiconductor layer in the trench.
CHANG teaches a method, further comprising:
before the forming of the insulation layer, forming an undoped semiconductor layer in the trench (undoped semiconductor 242, see fig 13, para 35).
CHUNG and CHANG are analogous art because they both are directed towards methods of making nanowire transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the undoped semiconductor of CHANG because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the undoped semiconductor of CHANG in order to benefit the formation of the other epitaxial layers (see CHANG para 35).
Claim(s) 35-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUNG (US 20210098634) in view of LIN (US 20210202497).
Regarding claim 35, CHUNG discloses the method of claim 30.
CHUNG fails to explicitly disclose a method, further comprising:
forming inner spacer features configured to provide isolation between the gate structure and the semiconductor feature.
LIN teaches a method, further comprising:
forming inner spacer features configured to provide isolation between the gate structure and the semiconductor feature (fig 1G, 720, para 43).
CHUNG and LIN are analogous art because they both are directed towards methods of making semiconductor nanowire transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the spacers of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the spacers of LIN in order to increase device density (see LIN para 93).
Regarding claim 36, CHUNG discloses the method of claim 35.
CHUNG fails to explicitly disclose a method, wherein a top surface of the insulation layer is below a top surface of a bottommost inner spacer feature of the inner spacer features.
LIN teaches a method, wherein a top surface of the insulation layer is below a top surface of a bottommost inner spacer feature of the inner spacer features (at top surface of insulation layer 510 is below the top surface of the bottommost 720, see fig 1G).
CHUNG and LIN are analogous art because they both are directed towards methods of making semiconductor nanowire transistors and one of ordinary skill in the art would have had a reasonable expectation of success to modify the method of CHUNG with the spacers of LIN because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the method of CHUNG with the spacers of LIN in order to increase device density (see LIN para 93).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/LYNNE A GURLEY/Supervisory Patent Examiner, Art Unit 2811