Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II without traverse: claims 1-10, submission of new claims 21-30 in the “Response to Election / Restriction Filed - 03/26/2026”, cancellation of non-elected claim(s) 11-20 is/are acknowledged. This office action considers claims 1-10, 21-30, in “Claims - 03/26/2026”, pending for prosecution.
Amendments to para. [0087] of the specification is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 9, 21-22, 24, 26, 28-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20140185264 A1 – hereinafter Chen).
Regarding Claim 1, Chen teaches a method for forming a package structure (see the entire document; Fig. 1(c); specifically, ([0018] - [0029]), and as cited below), comprising:
receiving a first chip structure ({301, 101} – Fig. 1(c) – [0024]-[0025]), wherein the first chip structure ({301, 101}) has a plurality of conductive bonding structures (203 – [0026]) and a dielectric bonding structure (101 is a polymer – see [0018]) surrounding the conductive bonding structures (101 surrounds 203), and top surfaces of the conductive bonding structures (203) and the dielectric bonding structure (101) are coplanar (as seen in Fig. 1(c));
bonding a second chip structure (307 – [0029]) to the dielectric bonding structure (101) and the conductive bonding structures (203) through dielectric-to-dielectric bonding (113 to 101) and metal-to-metal bonding (203 to 217);
forming an insulating layer (113 – Fig. 1C – [0025]) over the first chip structure ({301, 101}), wherein the insulating layer (113) laterally surrounds the second chip structure (113 surrounds 307); and
forming a capacitor element (left 305 – [0029]) laterally spaced apart from the second chip structure (307), wherein the insulating layer (113) at least partially surrounds the capacitor element (113 surrounds 305).
Regarding Claim 9, Chen teaches the method for forming a package structure as claimed claim 1, further comprising: forming a second capacitor element (right 305) laterally spaced apart from the second chip structure (307), wherein the insulating layer (113) at least partially surrounds the second capacitor element (right 305).
Regarding Claim 21, Chen teaches a method for forming a package structure (see the entire document; Fig. 1(c); specifically, ([0018] - [0029]), and as cited below), comprising:
receiving a first chip structure ({301, 101} – Fig. 1(c) – [0024]-[0025]), wherein the first chip structure has a dielectric bonding structure (101) and a plurality of conductive bonding structures (203) embedded in the dielectric bonding structure (101);
bonding a second chip structure (307 – [0029]) to the dielectric bonding structure (101) and the conductive bonding structures (203);
forming an insulating layer (113 – Fig. 1C – [0025]) over the first chip structure ({301, 101}), wherein the insulating layer (113) laterally surrounds the second chip structure (307); and
forming a capacitor element (right 305 – [0029]) at least partially embedded in the insulating layer (113 surrounds 305).
Regarding Claim 22, Chen teaches the method for forming a package structure as claimed in claim 21, further comprising: forming a conductive structure (219 under 307) at least partially embedded in the insulating layer (113), wherein the conductive structure (219) is laterally spaced apart from the capacitor element (left 305).
Regarding Claim 24, Chen teaches the method for forming a package structure as claimed in claim 22, wherein the capacitor element (right 305) is electrically connected to the conductive structure (203).
Regarding Claim 26, Chen teaches a method for forming a package structure (see the entire document; Fig. 1(c); specifically, ([0018] - [0029]), and as cited below), comprising:
receiving a first chip structure ({301, 101} – Fig. 1(c) – [0024]-[0025]), wherein the first chip structure ({301, 101}) has a dielectric bonding structure (101) and a plurality of conductive bonding structures (203);
planarizing surfaces of the dielectric bonding structure (all surfaces of 101 are planar) and the conductive bonding structure (all surfaces of 203 are planar);
bonding a second chip structure (307) to the dielectric bonding structure (101) and the conductive bonding structures (203) after the planarizing of the surfaces of the dielectric bonding structure (101) and the conductive bonding structures (203);
forming an insulating layer (113) over the first chip structure ({301, 101}); and
forming a capacitor element (right 305) at least partially embedded in the insulating layer (right 305 is embedded by 113).
Regarding Claim 28, Chen teaches the method for forming a package structure as claimed in claim 26, further comprising: forming a second capacitor element (left 305) at least partially embedded in the insulating layer (113).
Regarding Claim 29, Chen teaches the method for forming a package structure as claimed in claim 28, wherein the second capacitor element (left 305) is laterally disposed between the capacitor element (right 305) and the second chip structure (307).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Smith et al. (US 20090020849 A1 - hereinafter Smith).
Regarding Claim 27, Chen teaches claim 26 from which claim 27 depends. But Chen does not expressly wherein the insulating layer is formed before the formation of the capacitor element.
However, it is well known in the art to for an insulating layer before the formation of a capacitor as is also taught by Smith (Smith – [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming wherein the insulating layer is formed before the formation of the capacitor element as taught by Smith into Chen.
An ordinary artisan would have been motivated to integrate Smith structure into Chen structure in the manner set forth above for, at least, for the obvious reason of addressing defects in the insulating layer after its formation before the formation of the capacitor.
Allowable Subject Matter
Claims 2-8, 10, 23, 25, 30 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The method for forming a package structure as claimed in claim 1, further comprising: forming a first conductive layer, wherein the insulating layer laterally surrounds the first conductive layer; forming a capacitor dielectric layer over the first conductive layer; and forming a second conductive layer over the capacitor dielectric layer, wherein the first conductive layer, the capacitor dielectric layer, and the second conductive layer together form the capacitor element.
Claims 3-8 depend from claim 2.
Regarding claim 10: The method for forming a package structure as claimed in claim 1, further comprising: disposing a third chip structure over the first chip structure, wherein the capacitor element is between the second chip structure and the third chip structure.
Regarding claim 23: The method for forming a package structure as claimed in claim 22, wherein: the capacitor element has a first conductive layer, a second conductive layer, and a capacitor dielectric layer between the first conductive layer and the second conductive layer, the conductive structure has a third conductive layer and a fourth conductive layer over the third conductive layer, the third conductive layer and the first conductive layer are formed simultaneously, and the fourth conductive layer and the second conductive layer are formed simultaneously.
Regarding Claim 25, Chen teaches the method for forming a package structure as claimed in claim 21, further comprising: forming a second capacitor element at least partially embedded in the insulating layer, wherein the second chip structure is laterally disposed between the capacitor element and the second capacitor element.
Regarding claim 30: The method for forming a package structure as claimed in claim 26, wherein the capacitor element is formed with slanted sidewalls.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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