DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Foreign Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 01/05/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/23/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of group II in the reply filed on 06/04/2026 is acknowledged.
Claims 1-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/04/2026.
Claims 17-20 and 21-36 are pending examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17, 19, 22, 24-26 and 28-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (PG Pub 2021/0408233; hereinafter Xie).
PNG
media_image1.png
824
784
media_image1.png
Greyscale
Regarding claim 17, refer to Fig. 1 through Fig. 16 (with primary emphasis on Fig. 4, Fig. 8, Fig. 13 and Fig. 16 provided above), Xie teaches a method for forming a semiconductor structure 100, comprising:
forming a first fin structure 130 (“fin-1”) and a second fin structure 130 (“fin-2”) over a substrate 102 (see Fig. 4), wherein the first fin structure comprises first semiconductor material layers (122,124,126) and second semiconductor material layers (114,116,118) alternately stacked (see Fig. 4), and the second fin structure comprises first semiconductor material layers (114,116,118) and second semiconductor material layers (122,124,126) alternately stacked (see Fig. 4);
forming a first dummy gate structure 204 over the first fin structure and the second fin structure (see Fig. 4);
removing a portion of the first fin structure 302 (see Fig. 4) to form a first S/D structure 902 on a first side the first dummy gate structure (“s1”);
removing a portion of the second fin structure (“s2”) to form a second S/D structure on the first side the first dummy gate structure (see Fig. 4);
replacing the first dummy gate structure with a first gate structure 1310 (Fig. 13);
forming a first dielectric wall structure 502 between the first S/D structure and the second S/D structure (see Fig. 5); and
forming a second dielectric wall structure 1302 to divide the first gate structure into two portions, wherein the second dielectric wall structure overlaps a portion of the first dielectric wall structure (the portion abutting 704; see Fig. 16).
Regarding claim 19, refer to the figures cited above, Xie teaches forming an isolation structure 202 over the substrate 102, wherein the first fin structure (“fin-1”) and the second fin structure (“fin-2”) extend above the isolation structure (see Fig. 13) (see Fig. 4); and removing a portion of the isolation structure when forming the first dielectric wall structure 502, wherein a bottom surface of the first dielectric wall structure is lower than a top surface of the isolation structure (see Fig. 5).
Regarding claim 22, refer to the figures cited above, Xie teaches forming a bottom surface of the second dielectric wall structure 1302-bottom is higher than a bottom surface of the first dielectric wall structure 502-bottom (see Fig. 16).
Regarding claim 24, refer to the figures cited above, Xie teaches forming a gate spacer layer 208 adjacent to the first dummy gate structure 204, wherein the first dielectric wall structure passes through the gate spacer layer (is in the center thereof).
Regarding claim 25, refer to Fig. 1 through Fig. 16 (with primary emphasis on Fig. 4, Fig. 8, Fig. 13 and Fig. 16 provided above), Xie teaches a method for forming a semiconductor structure 100, comprising:
forming a first stack structure (“fin-1”) and a second stack structure (“fin-2”) along a first direction (y-direction) over a substrate 102, respectively, wherein the first stack structure comprises first semiconductor material layers (122,124,126) and second semiconductor material layers (122,124,126) alternately stacked (see Fig. 4), and the second stack structure comprises first semiconductor material layers (114,116,118) and second semiconductor material layers (122,124,126) alternately stacked (see Fig. 4);
forming a first dummy gate structure 204 along a second direction (y-direction) over the first stack structure and the second stack structure (see Fig. 4);
removing a portion of the first stack structure 302 (see Fig. 4) to form a first S/D structure 902 on a first side the first dummy gate structure (“s1”);
removing a portion of the second stack structure (“s2”) to form a second S/D structure on the first side the first dummy gate structure (see Fig. 4);
forming a first dielectric wall structure 502 between the first S/D structure and the second S/D structure (see Fig. 5);
wherein the first dielectric wall structure is along the first direction and between the first stack structure and the second stack structure (see Fig. 4);
removing the first semiconductor material layers (SiGe) to form first nanostructures and second nanostructures (see Fig. 13), wherein the first dielectric wall structure is between the first nanostructures and second nanostructures (belonging respectively to the first and second fin structures; see Fig. 8);
forming a first gate structure 1310 on the first nanostructures (on fin-1; see Fig. 16); and
forming a second gate structure 1310 on the second nanostructures (on fin-2; see Fig. 16);
Regarding claim 26, refer to the figures cited above, Xie teaches forming an isolation structure 202 over the substrate 102; and removing a portion of the isolation structure when forming the first dielectric wall structure 502, wherein a bottom surface of the first dielectric wall structure is lower than a top surface of the isolation structure (see Fig. 16).
Regarding claim 28, refer to the figures cited above, Xie teaches removing a portion of the first dielectric wall structure 502 to form a trench 302 (see Fig. 6); and forming a second dielectric wall structure 1302 in the trench (see Fig. 13).
Regarding claim 29, refer to the figures cited above, Xie teaches forming a gate spacer layer 208 adjacent to the first dummy gate structure 204 (see Fig. 12), wherein the first dielectric wall structure 502 passes through the gate spacer layer (see Fig. 12).
Regarding claim 30, refer to the figures cited above, Xie forming an S/D contact structure (S/D contact) over the first S/D structure 1604 (see Fig. 16), wherein a top surface of the S/D contact structure is higher than a top surface of the first dielectric wall structure (see Fig. 16).
Allowable Subject Matter
2. Claims 31-36 are allowable.
Claims 18, 20-21, 23 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 18 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 18, forming a gate spacer layer on a sidewall surface of the first dummy gate structure; removing a top portion of the first dummy gate structure; removing a top portion of the gate spacer layer; removing a bottom portion of the first dummy gate structure to form a T-shaped trench; and forming the first gate structure in the T-shaped trench.
Claim 20 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 20, removing a portion of the first dielectric wall structure when forming the second dielectric wall structure.
Claim 21 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 21, removing the first semiconductor material layers to form first nanostructures and second nanostructures, wherein the second dielectric wall structure is between the first nanostructures and second nanostructures.
Claim 23 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 23, forming an isolation structure over the substrate; and removing a portion of the isolation structure to form the second dielectric wall structure, wherein a bottom surface of the second dielectric wall structure is lower than a top surface of the isolation structure.
Claim 27 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 27, the first dielectric wall structure has a first portion between the first S/D structure and the second S/D structure and a second portion between the first gate structure and the second gate structure, the first portion has a first width along the second direction, the second portion has a second width along the second direction, and the first width is smaller than the second width.
Claim 31 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 31, forming a first stack structure and a second stack structure along a first direction over a substrate, forming a first dummy gate structure along a second direction over the first stack structure and the second stack structure; forming a first dielectric wall structure between the first stack structure and the second stack structure; removing the first dummy gate structure to form a trench, wherein the first dielectric wall structure is exposed by the trench; removing a portion of the first stack structure and a portion of the second stack structure to form first nanostructures and second nanostructures, wherein the first dielectric wall structure is between the first nanostructures and second nanostructures; forming a gate dielectric layer on a sidewall surface of the first dielectric wall structure; and forming a gate electrode on the gate dielectric layer, wherein the gate electrode comprises a first portion and a second portion, the first portion is separated from the second portion by the first dielectric wall structure. Claims 32-36 would be allowable, because they depend on allowable claim 31.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTINA A SYLVIA/Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights