DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6 July 2026 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Hayato Tanoue et al. (WO 2021/172085 A1; hereinafter “Tanoue”) in view of Katsuhiro Korematsu (US 2023/0150067 A1; hereinafter “Korematsu”).
Regarding Claim 1, Tanoue teaches a processing method of a bonded wafer formed through bonding (T, Fig. 2, para [0013] describes a method of bonding a wafer T), by a joining layer (Fw, Fig. 2, para [0014] describes a surface film Fw joining wafers S and W), a front surface of a first wafer and a front surface or a back surface of a second wafer (W and D, Fig. 2, para [0014] describes joining a front surface Wa of a first wafer W comprising a device layer D bonded to a front surface Sa of a second wafer S), the first wafer having, on the front surface thereof, a device region in which a plurality of devices are formed (D, Fig. 2, para [0014] describes a device layer D on a front surface of the first wafer W) and an outer circumferential surplus region that surrounds the device region and that includes a chamfered part formed at an outer circumferential edge thereof (We, Fig. 2, para [0014] describes a peripheral edge We that is chamfered and surrounding the device region D), the processing method comprising:
a coordinate generation step of detecting an outermost circumference of the joining layer and generating coordinates of the outermost circumference of the joining layer (para [0042] describes an IR camera being used in an alignment apparatus that is used to detect a boundary Ad of an unbonded region Ae wherein the unbonded region will be an outermost circumference of the joining layer Fw that bonds the wafer S and W together wherein the wafer processing system 1 and/or the interface modification apparatus 60 must generate coordinates for further processing the bonded wafer with reference to the boundary Ad detected);
a modified layer forming step (M1, Fig. 6, para [0026] describes a peripheral modification layer M1 forming step) of forming a plurality of modified layers in a form of rings inside the first wafer through holding a side of the second wafer by a first chuck table (M1 and M2, Fig. 6, para [0029] describes two chucks 83 on a rotary table 81 wherein a first chuck 83 is used to hold a side of the second wafer while forming a plurality of modified layers M1 and M2 in a form of rings inside the first wafer W as shown in Fig. 6 and Fig. 7), positioning the focal points of the laser beams inside the first wafer on an inner side in a radial direction relative to the chamfered part from a back surface of the first wafer (Ad, Fig. 6, para [0043] describes wherein the focal points used to form the modified layers M1 are positioned on an inner side in a radial direction relative to the chamfered part from a back surface of the first wafer W using the boundary Ad as a reference point), and executing irradiation with the laser beams (para [0026] describes wherein a laser is irradiated to the interior of the first wafer W to form the modified layers M1 and M2); and
a grinding step of holding the side of the second wafer by a second chuck table (S and 83, Fig. 2 and Fig. 3, para [0049] describes holding the side of the second wafer S by a second chuck table 83) and grinding the back surface of the first wafer to thin the first wafer (W, para [0049] describes wherein a grinding step to thin the first wafer W is performed at a same time as the step involving holding the side of the second wafer S by a second chuck table 83 wherein para [0053] describes the grinding unit 84 used in the grinding step to grind the separated surface of the first wafer Wd1), after the modified layer forming step is executed (Fig. 4 depicts wherein the modified layer M1 forming step happens prior to the wafer grinding process Wd1), wherein,
in the modified layer forming step, the focal points of the branch laser beams are formed in a form of descending stairs in such a manner as to get closer to the joining layer in a direction from the inner side toward an outer side in the radial direction of the first wafer (M1, Fig. 6 depicts wherein in the modified layer M1 forming step the focal points used to form the modified layers M1 are formed in a form of descending stairs in such a manner as to get closer to the joining layer Fw in a direction from the inner side Ac toward an outer side Ae in the radial direction of the first wafer W), a crack that extends from the modified layer formed by a lowermost one of the focal points reaches the coordinates of the outermost circumference of the joining layer generated in the coordinate generation step (C1 and Ad, Fig. 6, para [0038] describes a crack C1 that extends from the modified layer M1 formed by a lowermost one of the focal points closest to the boundary Ad which reaches the coordinates of the outermost circumference of the joining layer Fw generated in the coordinate generation step of setting the boundary Ad wherein the crack is controlled to extends from the surface Wa but does not reach the back surface of the first wafer W).
Tanoue fails to explicitly disclose a focal point setting step of causing a laser beam with a wavelength having transmissibility with respect to the first wafer to branch into a plurality of branch laser beams and setting focal points of the respective branch laser beams at different positions; wherein the modified layer forming step simultaneously forms a plurality of modified layers in a form of rings inside the first wafer through holding a side of the second wafer by a first chuck table, wherein: in the modified forming layer forming step, the focal points of the branch laser beams are formed simultaneously in a form of descending stairs in such a manner as to get closer to the joining layer in a direction from the inner side toward an outer side in the radial direction of the first wafer.
However, Korematsu teaches a similar processing method of a bonded wafer comprising:
a focal point setting step (63, Fig. 1, para [0074] describes an input receiving unit 63 which receives inputs for setting focal points of a branched laser light L) of causing a laser beam with a wavelength having transmissibility with respect to the first wafer to branch into a plurality of branch laser beams and setting focal points of the respective branch laser beams at different positions (3 and 32, Fig. 1 and Fig. 2, para [0046] and para [0047] describes wherein a laser irradiation unit 3 comprises a spatial light modulator 32 which branches an input laser light L into a plurality of laser lights L1 and L2 having a laser beam with a wavelength having transmissibility with respect to a first wafer 11 wherein the laser beams have focal points determined by the input receiving unit 63 at different positions such as C1 and C2);
wherein the modified layer forming step simultaneously forms a plurality of modified layers in a form of rings inside the first wafer through holding a side of the second wafer by a first chuck table (121 and 122, Fig. 2, para [0048] and para [0049] describes forming a plurality of modified layers 121 and 122 inside a wafer 11 simultaneously with two branched lasers L1 and L2 wherein a second side of the wafer 11a is held by a support portion stage 2 further wherein upon combining Tanoue with Korematsu, the modified layers 12 of Korematsu would be in an annular shape M1 and M2 as disclosed by Tanoue), wherein:
in the modified forming layer forming step, the focal points of the branch laser beams are formed simultaneously in a form of descending stairs in such a manner as to get closer to the joining layer in a direction from the inner side toward an outer side in the radial direction of the first wafer (C1 and C2, L1 and L2, Fig. 2, para [0047] describes focal points C1 and C2 of branched laser beams L1 and L2 being formed simultaneously in a form of descending stairs as shown by the distance Dx and Dz in Fig. 2 wherein the descending stair focal points C1 and C2 are formed in such a manner as to gradually get closer to a lowest surface 11a of a wafer 11 wherein upon combining Tanoue with Korematsu, the lowest surface of the wafer 11 would be at a side closest to the joining layer Fw of Tanoue in a direction from an inner side toward an outer side of the bonded wafer as described by Tanoue at the outer circumference detected by the IR Camera of Tanoue).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Tanoue with Korematsu to further disclose a processing method of a bonded wafer comprising a focal point setting step of causing a laser beam with a wavelength having transmissibility with respect to a first wafer to branch into a plurality of branch laser beams and setting focal points of the respective branch laser beams at different positions and further wherein the modified layer forming step simultaneously forms a plurality of modified layers in a form of rings inside the first wafer through holding a side of the second wafer by a first chuck table, wherein in the modified forming layer forming step, the focal points of the branch laser beams are formed simultaneously in a form of descending stairs in such a manner as to get closer to the joining layer in a direction from the inner side toward an outer side in the radial direction of the first wafer in order to provide the advantage of providing a laser process which may have a plurality of laser beams with a plurality of focal points, improving processing speed and suppressing deterioration processing quality (Korematsu, para [0111] and para [0022]).
Regarding Claim 2, the combination of Tanoue and Korematsu teaches the processing method according to claim 1, wherein,
in the grinding step, the modified layers are removed due to the grinding of the back surface of the first wafer (Tanoue, M1 and M2, Fig. 4(f), para [0053] describes wherein in the grinding step P5 of Fig. 5, the modified layers M1 and M2 are removed due to the grinding of the back surface of the first wafer W), and the chamfered part is removed from the first wafer due to the cracks (Tanoue, W, Fig. 4(e) depicts wherein the chamfered part Ae is removed from the first wafer W due to the cracks C1).
Regarding Claim 3, the combination of Tanoue and Korematsu disclose the processing method according to claim 1, wherein the plurality of focal points of the branch laser beams (Korematsu, C1 and C2, L1 and L2, Fig. 2, para [0047] describes focal points C1 and C2 of branched laser beams L1 and L2 being formed simultaneously in a form of descending stairs as shown by the distance Dx and Dz in Fig. 2) are formed in such a manner as to gradually get closer to the joining layer in a direction from an inner side toward an outer side of the bonded wafer at the outer circumference of the bonded wafer (Korematsu, C1 and C2, Fig. 2 depicts wherein the focal points C1 and C2 of the branched laser beams L1 and L2 are formed in such a manner as to gradually get closer to a lowest surface 11a of a wafer 11 wherein upon combining Tanoue with Korematsu, the lowest surface of the wafer 11 would be at a side closest to the joining layer Fw of Tanoue in a direction from an inner side toward an outer side of the bonded wafer as described by Tanoue at the outer circumference detected by the IR camera of Tanoue).
Response to Arguments
Applicant’s arguments, see page 4, lines 6-21, page 5, lines 1-22, page 6, lines 1-22, page 7, lines 1-22 and page 8, lines 1-20, filed 17 August 2026, with respect to the rejections of claims 1-3 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of newly found prior art reference, Hayato Tanoue et al. (WO 2021/172085 A1; hereinafter “Tanoue”), disclosed in the IDS document submitted by the Applicant on 6 July 2026.
The Applicant argues on page 4, lines 6-21, page 5, lines 1-22, page 6, lines 1-22, page 7, lines 1-22 and page 8, lines 1-20 of the remarks that the prior art of record, Lu, in combination with prior art of record Nakamura and Korematsu, fail to disclose or suggest a processing method where “a crack that extends from the modified layer formed by a lowermost one of the focal points reaches the coordinates of the outermost circumference of the joining layer generated in the coordination generation step” as recited in previously presented claim 1. The Examiner finds this argument to be persuasive. However, newly found prior art, Tanoue, teaches a similar processing method comprising a crack that extends from the modified layer formed by a lowermost one of the focal points reaches the coordinates of the outermost circumference of the joining layer generated in the coordinate generation step (Tanoue, C1 and Ad, Fig. 6, para [0038] describes a crack C1 that extends from the modified layer M1 formed by a lowermost one of the focal points closest to the boundary Ad which reaches the coordinates of the outermost circumference of the joining layer Fw generated in the coordinate generation step of setting the boundary Ad wherein the crack is controlled to extend from the surface Wa but does not reach the back surface of the first wafer W), as disclosed in the 35 U.S.C. 103 rejection above. The 35 U.S.C. 103 rejection for claim 1 disclosed above does not rely upon any of the previously considered prior art of record contested in the Applicant’s arguments submitted 17 August 2026 and therefore the Examiner has presented the new ground of rejection in view of newly found prior art, Tanoue, above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights