Attorney’s Docket Number: 2023-0822/24061.4851US01
Filing Date: 10/23/2023
Claimed Priority Date: 7/14/2023 (PRO 63/513,600)
Inventors: Lin et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the election filed 3/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of invention I, reading on a method, in the reply filed on 3/13/2026, is acknowledged. The applicant cancelled claims 18-20, added claims 21-23, and indicated that claims 1-17 and 21-23 read on the elected invention. The examiner agrees.
Claim Objections
Claim 13 is objected to because of the following informalities: “…wherein the first epitaxial layer is in physical with the dielectric film…” is improper. For the purposes of examination, the line will be construed to recite “…wherein the first epitaxial layer is in physical contact with the dielectric film…”. Appropriate correction is required.
Claim 14 is objected to because of the following informalities: “…wherein each of the first epitaxial layer and the second epitaxial layer is in physical with the dielectric film…” is improper. For the purposes of examination, the line will be construed to recite “…wherein each of the first epitaxial layer and the second epitaxial layer are in physical contact with the dielectric film…”. Appropriate correction is required.
Claim 21 is objected to because of the following informalities: “…removing the dummy gate stack to from a gate trench” is improper. For the purposes of examination, the line will be construed to recite “…removing the dummy gate stack to form a gate trench”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "…the base epitaxial layer…" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the first recitation of the limitation “…the base epitaxial layer…” will be construed to recite “…a base epitaxial layer…”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 9, 21, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (US 20220122893 A1).
Regarding claim 1, Lai (see, e.g., figs. 1A-25B) shows all aspects of the instant invention, including a method comprising:
Forming a stack (e.g., epitaxial stack 212) over a substrate (e.g., substrate 202), the stack (e.g., epitaxial stack 212) comprising a plurality of channel layers (e.g., plurality of channel layers 216, see fig. 10A) interleaved by a plurality of sacrificial layers (e.g., plurality of sacrificial layers 214 in fig. 10A);
Patterning (see, e.g., paragraph 19 “…patterns the epitaxial stack 212 to form semiconductor fins 220 (also referred to as fins 220), as shown in Fig. 4…”) the stack (e.g., epitaxial stack 212) and a top portion of the substrate (see, e.g., paragraph 19” In various embodiments, each of the fins 220 includes an upper portion 220A (also termed as epitaxial portion 220A) of the interleaved epitaxial layers 214 and 216 and a bottom portion 220B that is formed by patterning a top portion of the substrate 202”) to form a fin-shape structure (e.g., fins 220), the fin-shape structure (e.g., fins 220) comprising a channel region (e.g., span of plurality of channel layers 216) and a source/drain region (see, e.g., paragraph 22 “By patterning the sacrificial gate structure 224, the stacked epitaxial layers 214 and 216 are partially exposed on opposite sides of the sacrificial gate structure 224, thereby defining source/drain (S/D) regions…”);
Forming a dummy gate stack (e.g., method 110 “Form dummy gate stacks on the fins”, see sacrificial gate structure 224) over the channel region (e.g., span of plurality of channel layers 216) of the fin-shape structure (e.g., fins 220);
Depositing a gate spacer layer (e.g., gate spacers 232) over the dummy gate stack (see, e.g., operation 112 “Form gate sidewall spacers on sidewalls of the dummy gate stack” or paragraph 23 “…forms gate spacers 232 on sidewalls of the sacrificial gate structure 224….”);
Recessing (see, e.g., paragraph 24) the source/drain region (see. e.g., operation 114 “…recess portions of the fins 220 to form S/D trenches 234 (or termed as S/D recesses 234) in the S/D regions….”) to form a source/drain trench (e.g., S/D trenches 234) that exposes sidewalls (see, e.g., fig. 11A) of the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 10A) and the plurality of sacrificial layers (e.g., plurality of sacrificial layers 214 in fig. 10A);
Selectively and partially recessing (e.g., operation 118 + paragraph 26 “…laterally etches end portions of the epitaxial layers 214”) the plurality of sacrificial layers (e.g., plurality of sacrificial layers 214) to form a plurality of inner spacer recesses (e.g., cavities 238, see fig. 12A);
Forming a plurality of inner spacer features (e.g., operation 120 “Depositing an insulating dielectric layer on end portions of the sacrificial layers…”, see inner spacers 240’, see paragraph 29) in the plurality of inner spacer recesses (e.g., cavities 238, see fig. 12A);
Depositing a dielectric film (e.g., insulating dielectric layer 240, see, e.g., paragraph 24) in the source/drain trench (e.g., S/D trenches 234), a top surface of the dielectric film (e.g., insulating dielectric layer 240) being below a top surface of the substrate (e.g., substrate 202);
Forming (see, e.g., paragraph 31) an epitaxial feature (e.g., epitaxial S/D features 254) over the dielectric film (e.g., insulating dielectric layer 240, see, e.g., paragraph 24), the epitaxial feature (e.g., epitaxial S/D features 254) being in contact (e.g., note direct contact between left-side epitaxial S/D feature 254 and plurality of channel layers 216) with the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 16A), a bottom surface (see, e.g., annotated fig. 1 below) of the epitaxial feature (e.g., epitaxial S/D features 254) being below the top surface (see, e.g., annotated fig. 1, noting that the epitaxial S/D features 254 extend/recess below the top surface of the substrate 202) of the substrate (e.g., substrate 202) in the fin-shape structure (e.g., fins 220);
After the forming of the epitaxial feature (e.g., epitaxial S/D features 254), removing the dummy gate stack (e.g., operation 134 + paragraph 36 “…removes the sacrificial gate structure 224”, see fig. 20A);
Releasing (e.g., operation 136 “…releases channel structures from the channel region of the GAA device…The plurality of epitaxial layers 214 may be selectively removed”) the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 21A) in the channel region (e.g., span of plurality of channel layers 216) as a plurality of channel members (see, e.g., freed channel structures 216, see paragraph 37 and fig. 21A), and;
Forming a gate structure (e.g., metal gate structure 268) wrapping around (see, e.g., paragraph 38 “…forms a metal gate structure 268 in the gate trench 264 wrapping each of the channel structures 216 in the channel region…”) each of the plurality of channel members (see, e.g., channel structures 216 of fig. 22A, see paragraph 37 and fig. 22A).
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Annotated Fig. 1
Regarding claim 9, Lai (see, e.g., figs. 1A-25B) shows wherein the source/drain trench (e.g., S/D trench 234) exposes a sidewall (see, e.g., fig. 12A) of the substrate (e.g., substrate 202), and wherein the epitaxial feature (e.g., epitaxial S/D feature 254) is in physical contact with the sidewall (see, e.g., fig. 16A and note the epitaxial S/D feature 254 is now in direct physical contact with at least part of the substrate 202 that was previously exposed via the S/D trench 234) of the substrate (e.g., substrate 202).
Regarding claim 21, Lai (see, e.g., figs. 1A-25B) shows all aspects of the instant invention, including a method comprising:
Forming a stack (e.g., epitaxial stack 212) over a substrate (e.g., substrate 202), the stack (e.g., epitaxial stack 212) comprising a plurality of channel layers (e.g., plurality of channel layers 216, see fig. 10A) interleaved by a plurality of sacrificial layers (e.g., plurality of sacrificial layers 214 in fig. 10A);
Patterning (see, e.g., paragraph 19 “…patterns the epitaxial stack 212 to form semiconductor fins 220 (also referred to as fins 220), as shown in Fig. 4…”) the stack (e.g., epitaxial stack 212) to form a fin-shape structure (e.g., fins 220), the fin-shape structure (e.g., fins 220);
Forming a dummy gate stack (e.g., method 110 “Form dummy gate stacks on the fins”, see sacrificial gate structure 224) across the fin-shape structure (e.g., fins 220);
Depositing a gate spacer layer (e.g., gate spacers 232) over a sidewall of the dummy gate stack (see, e.g., operation 112 “Form gate sidewall spacers on sidewalls of the dummy gate stack” or paragraph 23 “…forms gate spacers 232 on sidewalls of the sacrificial gate structure 224….”);
Recessing (see, e.g., paragraph 24) a region of the fin-shape structure (e.g., fins 220) adjacent to the gate spacer layer (e.g., gate spacers 232) to form a trench (see. e.g., operation 114 “…recess portions of the fins 220 to form S/D trenches 234 (or termed as S/D recesses 234) in the S/D regions….”) that exposes sidewalls (see, e.g., fig. 11A) of the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 10A) and the plurality of sacrificial layers (e.g., plurality of sacrificial layers 214 in fig. 10A);
Depositing a dielectric film (e.g., insulating dielectric layer 240, see, e.g., paragraph 24) in the trench (e.g., S/D trenches 234), a top surface of the dielectric film (e.g., insulating dielectric layer 240) being below a top surface of the substrate (e.g., substrate 202);
Forming (see, e.g., paragraph 31) an epitaxial feature (e.g., epitaxial S/D features 254) over the dielectric film (e.g., insulating dielectric layer 240, see, e.g., paragraph 24), the epitaxial feature (e.g., epitaxial S/D features 254) abutting (e.g., note direct contact between left-side epitaxial S/D feature 254 and plurality of channel layers 216) the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 16A), a bottom surface (see, e.g., annotated fig. 1 above) of the epitaxial feature (e.g., epitaxial S/D features 254) being below the top surface (see, e.g., annotated fig. 1, noting that the epitaxial S/D features 254 extend/recess below the top surface of the substrate 202) of the substrate (e.g., substrate 202);
After the forming of the epitaxial feature (e.g., epitaxial S/D features 254), removing the dummy gate stack (e.g., operation 134 + paragraph 36 “…removes the sacrificial gate structure 224”, see fig. 20A) to form a gate trench (e.g., gate trench 264);
Releasing (e.g., operation 136 “…releases channel structures from the channel region of the GAA device…The plurality of epitaxial layers 214 may be selectively removed”) the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 21A) in the gate trench (e.g., gate trench 264) as a plurality of channel members (see, e.g., freed channel structures 216, see paragraph 37 and fig. 21A), and;
Depositing a gate structure (e.g., metal gate structure 268) in the gate trench (e.g., gate trench 264), the gate structure (e.g., metal gate structure 268) wrapping around (see, e.g., paragraph 38 “…forms a metal gate structure 268 in the gate trench 264 wrapping each of the channel structures 216 in the channel region…”) at least one of the plurality of channel members (see, e.g., channel structures 216 of fig. 22A, see paragraph 37 and fig. 22A)
Regarding claim 23, Lai (see, e.g., figs. 1A-25B) shows wherein the trench (e.g., S/D trench 234) exposes a sidewall (see, e.g., fig. 12A) of the substrate (e.g., substrate 202), and wherein the epitaxial feature (e.g., epitaxial S/D feature 254) interfaces with the sidewall (see, e.g., fig. 16A and note the epitaxial S/D feature 254 is now in direct physical contact with at least part of the substrate 202 that was previously exposed via the S/D trench 234) of the substrate (e.g., substrate 202).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of More (US 20220059703 A1).
Regarding claim 2, Lai (see, e.g., figs. 1A-25B) fails to show prior to the depositing of the dielectric film, depositing a base epitaxial layer in the source/drain trench.
More (see, e.g., fig. 9A), in a similar device to Lai, teaches prior to depositing (see, e.g., paragraph 64 “The cover layer 51 is formed by using one or more deposition (e.g., dielectric layer deposition)”) a dielectric film (e.g., cover layer 51 + paragraph 64 “…the cover layer 51 is a…dielectric layer, such as silicon nitride, silicon oxide…”), depositing (see, e.g., paragraph 62 “The epitaxial growth is a selective growing including etching operations and deposition operations…”) a base epitaxial layer (e.g., base epitaxial layer 49) in a source/drain trench (e.g., source/drain space 21).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the base epitaxial layer deposition prior to the dielectric film depositing of More within the device of Lai, in order to improve the short channel effects and improve leakage current reduction within the device (see, e.g., paragraph 101 of More).
Regarding claim 3, More (see, e.g., fig. 9A) teaches wherein a dopant concentration of the epitaxial feature (e.g., source/drain epitaxial layer 50) is greater than a dopant concentration (see, e.g., paragraph 84 “…the dopants…diffuse into the base epitaxial layer, thereby forming a lightly doped region…higher dopant concentration than the base epitaxial layer 49”) of the base epitaxial layer (e.g., base epitaxial layer 49).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the epitaxial feature>base epitaxial dopant configuration of More within the device of Lai in view of More, in order to modify the dopant profile within the device and provide the aforementioned short channel effects as expected, while still maintaining the expected higher dopant standard of the source/drain region.
Regarding claim 4, More (see, e.g., fig. 9A) teaches wherein the base epitaxial layer (e.g., base epitaxial layer 49) is dopant free (see, e.g., paragraph 101 “…a base epitaxial layer 49, which is a non-doped semiconductor layer…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dopant free base epitaxial layer configuration within the device of Lai in view of More, in order to achieve the expected result of improving the short channel effects (as previously mentioned) in addition to reducing the cost during fabrication of the device by skipping the dopant step.
Regarding claim 5, Lai (see, e.g., figs. 1A-25B) teaches wherein the epitaxial feature (e.g., epitaxial S/D features 254) is doped with boron (see, e.g., paragraph 31 “…the epitaxial S/D features 254 include silicon-germanium (SiGe) doped with boron…”).
Regarding claim 6, Lai (see, e.g., figs. 1A-25B) shows wherein the epitaxial feature (e.g., epitaxial S/D features 254) comprise silicon germanium (see, e.g., paragraph 31 “…the epitaxial S/D features 254 include silicon-germanium (SiGe)”).
More (see, e.g., fig. 9A) teaches wherein the base epitaxial layer (e.g., base epitaxial layer 49) comprises silicon germanium (see, e.g., paragraph 34 “…the base epitaxial layer 49 are made of the same material …SiGe…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the silicon germanium of More within the base epitaxial layer of Lai in view of More to use a silicon germanium composition because it is recognized in the semiconductor art for its usage in epitaxial materials, as taught by More, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v.
Regarding claim 22, Lai (see, e.g., figs. 1A-25B) fails to show prior to the depositing of the dielectric film, depositing an undoped epitaxial layer in the trench.
More (see, e.g., fig. 9A), in a similar device to Lai, teaches prior to depositing (see, e.g., paragraph 64 “The cover layer 51 is formed by using one or more deposition (e.g., dielectric layer deposition)”) a dielectric film (e.g., cover layer 51 + paragraph 64 “…the cover layer 51 is a…dielectric layer, such as silicon nitride, silicon oxide…”), depositing (see, e.g., paragraph 62 “The epitaxial growth is a selective growing including etching operations and deposition operations…”) an undoped epitaxial layer (e.g., base epitaxial layer 49 + paragraph 101 “…a base epitaxial layer 49, which is a non-doped semiconductor layer…”) in a trench (e.g., source/drain space 21).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the base epitaxial layer deposition prior to the dielectric film depositing of More within the device of Lai, in order to improve the short channel effects and improve leakage current reduction within the device (see, e.g., paragraph 101 of More).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of More further in view of Chu (US 20220069135 A1).
Regarding claim 7, Lai in view of More fails to explicitly teach wherein a germanium content of the epitaxial feature is greater than a germanium content of the base epitaxial layer.
Chu (see, e.g., fig. 13B), in a similar device to Lai in view of More teaches wherein a germanium content of an epitaxial feature (e.g., second epitaxial layer 238) is greater than a germanium content (see, e.g., paragraph 30 “Compared to the first epitaxial layer 236 (or the alternative first epitaxial layer 2360), the second epitaxial layer 238 includes a greater germanium content to enhance the strain on the channel layers 208…”) of a base epitaxial layer (e.g., first epitaxial layer 236/2360B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the superior germanium configuration of the epitaxial feature to the base epitaxial layer of Chu within the device of Lai in view of More, in order to enhance the strain between the source/drain and the channel layers, increasing the carrier mobility within the device.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of More further in view of Lie (US 20200052107 A1).
Regarding claim 10, Lai (see, e.g., figs. 1A-25B) shows depositing a dielectric material layer (e.g., insulating dielectric layer 240, see, e.g., fig. 13A) on the sidewalls of the plurality of channel layers (e.g., plurality of channel layers 216, see fig. 13A) and the plurality of sacrificial layers (e.g., plurality of sacrificial layers 214 in fig. 13A); and etching (see, e.g., paragraph 29) back the dielectric material layer (e.g., insulating dielectric layer 240) to remove the dielectric material layer, wherein a portion of the dielectric material layer remains as the dielectric film (e.g., insulating dielectric layer 240 portion laying in the recess of the substrate, see fig. 15A).
Lai (see, e.g., figs. 1A-25B), however, fails to show wherein the depositing of the dielectric film includes depositing a dielectric material layer on a top surface of the base epitaxial layer, while it also fails to show that the etching back of the dielectric material layer removes the dielectric material layer from the sidewalls of the plurality of channel layers and the plurality of sacrificial layers, and wherein the portion of the dielectric material layer remaining is on the top surface of the base epitaxial layer.
More (see, e.g., fig. 9A), in a similar device to Lai, teaches prior to depositing (see, e.g., paragraph 64 “The cover layer 51 is formed by using one or more deposition (e.g., dielectric layer deposition)”) a dielectric film (e.g., cover layer 51 + paragraph 64 “…the cover layer 51 is a…dielectric layer, such as silicon nitride, silicon oxide…”), depositing (see, e.g., paragraph 62 “The epitaxial growth is a selective growing including etching operations and deposition operations…”) a base epitaxial layer (e.g., base epitaxial layer 49) in a source/drain trench (e.g., source/drain space 21).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the base epitaxial layer deposition prior to the dielectric film depositing of More within the device of Lai, in order to improve the short channel effects and improve leakage current reduction within the device (see, e.g., paragraph 101 of More). Note that this base epitaxial layer is deposited below the dielectric film within the recess, so it must be done before the dielectric film deposition step, hence the dielectric material layer would be deposited directly onto the top surface of the base epitaxial layer before being etched to have a remaining portion disposed on top of said base epitaxial layer.
Lai in view of More, however, fails to teach that the etching back of the dielectric material layer removes the dielectric material layer from the sidewalls of the plurality of channel layers and the plurality of sacrificial layers.
Lie (see, e.g., fig. 10), in a similar device to Lai in view of More, teaches etching (see, e.g., paragraph 77) back a dielectric material layer (e.g., isolation fill layer + paragraph 74) to remove the dielectric material layer (e.g., isolation fill layer + paragraph 74) from the sidewalls (e.g., sidewall spacers 140/protective layer segment 185) of a plurality of channel layers (e.g., nanosheet channel layer segments 135).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material layer deposition of Lie on top of the inner space features of Lai in view of More, dividing the spacer feature deposition and dielectric recess deposition into two distinct steps, in order to properly protect the inner spacer during the dielectric recess filling process.
Claims 11-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Lie further in view of Chu.
Regarding claim 11, Lai (see, e.g., figs. 1A-25B) shows most aspects of the instant invention, including a method comprising:
forming a plurality of channel members (e.g., plurality of channel layers 216, see fig. 10A) over a fin-shape substrate (e.g., substrate 202);
Forming a plurality of inner spacer features (e.g., operation 120 “Depositing an insulating dielectric layer on end portions of the sacrificial layers…”, see inner spacers 240’, see paragraph 29) interleaving (e.g., cavities 238, see fig. 12A) the plurality of channel members (e.g., plurality of channel layers 216, see fig. 10A);
Depositing a dielectric material layer (e.g., insulating dielectric layer 240, see, e.g., fig. 14) on sidewalls of the fin-shape substrate (e.g., substrate 202) and the plurality of channel members (e.g., plurality of channel layers 216, see fig. 10A),
Etching back (see, e.g., paragraph 29 “…partially removes the insulating dielectric layer 240 from the S/D recesses in an etching process…”) the dielectric material layer (e.g., insulating dielectric layer 240) to form a dielectric film (e.g., insulating dielectric layer 240 portion laying in the recess of the substrate, see fig. 15A), a top surface of the dielectric film (e.g., insulating dielectric layer 240 portion laying in the recess of the substrate, see fig. 15A) being below a top surface of the fin-shape substrate (e.g., substrate 202);
Depositing a first epitaxial layer (e.g., epitaxial S/D feature 254) over the dielectric film (e.g., insulating dielectric layer 240 portion laying in the recess of the substrate, see fig. 15A), the first epitaxial layer (e.g., epitaxial S/D feature 254) being in contact with the plurality of channel members (e.g., plurality of channel layers 216, see fig. 10A);
Forming a gate structure (e.g., metal gate structure 268) wrapping around (see, e.g., paragraph 38 “…forms a metal gate structure 268 in the gate trench 264 wrapping each of the channel structures 216 in the channel region…”) each of the plurality of channel members (see, e.g., channel structures 216 of fig. 22A, see paragraph 37 and fig. 22A);
Wherein the first epitaxial layer (e.g., epitaxial S/D feature 254) comprises silicon germanium (see, e.g., paragraph 31 “In some embodiments, the epitaxial S/D features 254 include silicon-germanium…”).
Lai (see, e.g., figs. 1A-25B), however, fails to show depositing the dielectric material layer on sidewalls of the plurality of inner spacer features, and depositing a second epitaxial layer over the first epitaxial layer, the second epitaxial layer being in contact with the plurality of inner spacer features and the first epitaxial layer, and wherein the second epitaxial layer comprises silicon germanium, wherein a germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.
Lie (see, e.g., fig. 10), in a similar device to Lai, teaches depositing a dielectric material layer (e.g., isolation fill layer + paragraph 74) on sidewalls of the plurality of inner space features (e.g., sidewall spacers 140/protective layer segment 185), before etching (see, e.g., paragraph 77) and leaving the dielectric material layer (e.g., isolation fill layer + paragraph 74) within a recess (e.g., recess within substrate 110).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material layer deposition of Lie on top of the inner space features of Lai, dividing the spacer feature deposition and dielectric recess deposition into two distinct steps, in order to properly protect the inner spacer during the dielectric recess filling process.
Lai in view of Lie, however, fails to teach depositing a second epitaxial layer over the first epitaxial layer, the second epitaxial layer being in contact with the plurality of inner spacer features and the first epitaxial layer, and wherein the second epitaxial layer comprises silicon germanium, wherein a germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer.
Chu (see, e.g., fig. 13A), in a similar device to Lai in view of Lie, teaches a first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B) being in contact (see, e.g., contact between 236T and channel layers 208) with a plurality of channel members (e.g., channel layers 208), and depositing (see, e.g., paragraph 30) a second epitaxial layer (e.g., second epitaxial layer 238) over the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B), the second epitaxial layer (e.g., second epitaxial layer 238) being in contact with a plurality of inner spacer features (e.g., inner spacer features 234) and the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B), and wherein the second epitaxial layer (e.g., second epitaxial layer 238) comprises silicon germanium (see, e.g., paragraph 30 “…the second epitaxial layer 238 includes silicon germanium (SiGe)…”), wherein a germanium content of the second epitaxial layer (e.g., second epitaxial layer 238) is greater than a germanium content (see, e.g., paragraph 30 “Compared to the first epitaxial layer 236 (or the alternative first epitaxial layer 2360), the second epitaxial layer 238 includes a greater germanium content to enhance the strain on the channel layers 208…”) of the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the entire first epitaxial layer and second epitaxial layer configuration (omitting the aforementioned original first epitaxial layer 254 of Lai) of Chu within the device of Lai in view of Lie, in order to enhance the strain between the source/drain and the channel layers, increasing the carrier mobility within the device.
Regarding claim 12, Chu teaches wherein a bottom surface of the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B) is below the top surface of a fin-shape substrate (e.g., substrate 202).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the first epitaxial layer protrusion of Chu within the device of Lai in view of Lie further in view of Chu, in order to achieve the expected result of providing a high-quality uniform foundation on the substrate. In addition, note the original epitaxial feature of Lai also extended below the top surface of the fin-shape substrate.
Regarding claim 13, Lai in view of Lie further in view of Chu teaches wherein the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B added via Chu) is in physical contact (see, e.g., fig. 25A, noting that etch protection layer 242 is in direct contact with the insulating dielectric layer 240 and the original epitaxial feature 254 (replaced by the first epitaxial layer 236 + second epitaxial layer 254) and is also a dielectric, see paragraph 28) with the dielectric film (e.g., insulating dielectric layer 240 + etch protection layer 242 + paragraph 28), and the first epitaxial layer (e.g., first epitaxial layer 236, comprised of both first channel sidewall portions 236T and first substrate portion 236B added via Chu) separates (e.g., note that Chu’s first epitaxial layer directly separates the second epitaxial layer from the substrate area, also see the claim rejection regarding claim 11 above) the second epitaxial layer (e.g., second epitaxial layer 238 added via Chu) from the dielectric film (e.g., insulating dielectric layer 240 + etch protection layer 242 + paragraph 28 + 42, see fig. 25A).
Regarding claim 15, Lai in view of Lie further in view of Chu teaches wherein the second epitaxial layer (e.g., second epitaxial layer 238 added via Chu) caps a void (e.g., air gap 256) between (e.g., note that second epitaxial layer 238 added via Chu is placed substantially within the same position as the epitaxial feature 254 was placed) the dielectric film (e.g., insulating dielectric layer 240 portion laying in the recess of the substrate, see fig. 20A) and the second epitaxial layer (e.g., second epitaxial layer 238 added via Chu).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Lie further in view of Chu and More.
Regarding claim 16, Lai (see, e.g., figs. 1A-25B) in view of Lie further in view of Chu fails to teach prior to depositing of the dielectric film, depositing a base epitaxial layer in the source/drain trench.
More (see, e.g., fig. 9A), in a similar device to Lai in view of Lie further in view of Chu, teaches prior to the depositing (see, e.g., paragraph 64 “The cover layer 51 is formed by using one or more deposition (e.g., dielectric layer deposition)”) of a dielectric material layer (e.g., cover layer 51 + paragraph 64 “…the cover layer 51 is a…dielectric layer, such as silicon nitride, silicon oxide…”), depositing (see, e.g., paragraph 62 “The epitaxial growth is a selective growing including etching operations and deposition operations…”) an undoped (see, e.g., paragraph 101 “…a base epitaxial layer 49, which is a non-doped semiconductor layer…”) epitaxial layer (e.g., base epitaxial layer 49) in physical contact with the sidewall of the fin-shape substrate (e.g., fin structure 11).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the base epitaxial layer deposition prior to the dielectric film depositing of More within the device of Lai in view of Lie further in view of Chu, in order to improve the short channel effects and improve leakage current reduction within the device (see, e.g., paragraph 101 of More).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Lai in view of Lie further in view of Chu and Jung (US 20200303504 A1).
Regarding claim 17, Lai in view of Lie further in view of Chu fails to teach the dielectric film comprises a metal oxide or a metal nitride.
Jung (see, e.g., fig. 9F) teaches a dielectric film (e.g., dielectric film 112) comprises a metal oxide (see, e.g., paragraph 34 “The dielectric film 112 may include metal oxide…”) or a metal nitride.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the metal oxide of Jung within the dielectric film of Lai in view of Lie further in view of Chu to use a metal oxide composition because it is recognized in the semiconductor art for its usage in dielectric materials, as taught by Jung, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v.
Allowable Subject Matter
Claims 8 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8: the primary art of record, Lai in view of More neither anticipates nor renders obvious wherein a germanium content of the epitaxial feature is less than a germanium content of the base epitaxial layer. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Regarding claim 14, the primary art of record, Lai in view of Lie further in view of Chu neither anticipates nor renders obvious wherein each of the first epitaxial layer and the second epitaxial layer are in physical contact with the dielectric film. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Conclusion
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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