DETAILED ACTION
This correspondence is in response to the communications received 02/02/2026. Claims 23-27 have been added. Claims 14-20 have been canceled. Claims 1-13 and 21-27 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-13 and newly added claims 21-27 in the reply filed on 02/02/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/23/2023 and 01/28/2025 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 11, a device (300), comprising:
an active region (210) that includes a plurality of interleaving first semiconductor layers (220) and second semiconductor layers (230);
a PIN diode (200) formed in the active region, the PIN diode including a P-type component (200A), an N-type component (200B), and an undoped component disposed between the P-type component and the N-type component ("The P-type component 200A and the N-type component 200B of the PIN diode 200 are separated by an undoped portion of the active region 210, which may also be referred to as the intrinsic portion of the PIN diode 200", [0031]); and
a first conductive contact (320A) and a second conductive contact (320B) disposed over a first side of the PIN diode (see Fig. 3), wherein the first conductive contact and the second conductive contact are electrically coupled to the P-type component and the N-type component (see Fig. 3), respectively;
a dielectric structure (250) disposed over a second side of the PIN diode opposite from the first side (see Fig. 3); and
one or more doped regions ("doped regions 600A and 600B (e.g., P-type doped regions containing boron)", [0048]) disposed between the PIN diode and the dielectric structure (see Fig. 8), wherein the one or more doped regions each include a P-type dopant.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 7,560,784 B2, published 07/14/2009).
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Regarding claim 1, Figs. 11A and 11B of Cheng disclose a device (see title), comprising:
a diode (“In one embodiment of the invention, a P+ polysilicon stripe 1110 may be deposited adjacent to the PIN diode as illustrated in FIG. 11”, col. 8, lines 49-51, thus the structure shown in Figs. 11A and 11B is a diode) that includes a P-type region (“P+ doped layer 150”, col. 4, line 26), an N-type region (“semiconductor fin 121 may project outwards from a surface of the N+ doped layer 120 as illustrated in FIG. 1. Fin 121 may have a similar concentration of dopant as the N+ doped layer 120”, col. 4, lines 11-14), and an undoped intrinsic region (“intrinsic layer 140”, col. 4, line 25) disposed between the P-type region and the N-type region (as seen in Fig. 11A, 140 is disposed between 150 and 121);
an interconnect structure (120 is an interconnect structure as it connects 121 to the N+ contacts seen in Fig. 11B) disposed over a first side of the diode (as seen in Fig. 11A, 120 is disposed over the bottom side of the diode);
a plurality of conductive vias (“contacts 1120”, col. 8, line 54, Cheng does not specify that 1120 are vias, therefore a secondary reference will be used to teach this limitation below) disposed over a second side of the diode (as seen in Fig. 11A, 1120 are disposed over the top side of the diode as seen in Fig. 11A), the second side being different from the first side (as seen in Fig. 11A, the top side of the diode is different from the bottom side of the diode); and
one or more doped regions (“P+ polysilicon stripe 1110”, col. 8, lines 49-50) disposed between the diode and the conductive vias (as seen in Fig. 11A, 1110, is between 1120 and the diode formed by 150, 121, and 140).
Cheng fails to disclose “a plurality of conductive vias”.
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However, in a similar field of endeavor, Figs. 10A and 10B of Cheng teach a plurality of conductive vias (“The photoresist layer may be patterned and exposed to light to develop a mask defining regions for contacts 1010. Subsequently, an oxide RIE process may be performed down to the nitride etch stop layer 810. For a P+ contact, a recess may be formed in the nitride etch stop layer 810 to form a via exposing the P+ doped layer 150. For the N+ doped layer 120, a recess may be formed in the nitride etch stop layer and a final oxide RIE process may be performed on the exposed STI layer 130 to form vias exposing the N+ doped layer 120. Once the vias are open, a suitable metal, for example, tungsten or N+ doped polysilicon may be deposited in the vias and planarized”, col. 8, lines 29-41, thus 1010 are vias, as 1010 are equivalent to 1120 in Figs. 11A and 11B, 1120 are also vias).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a plurality of conductive vias” as taught by Figs. 10A and 10B of Cheng in the system of Figs. 11A and 11B of Cheng for the purpose of providing an electrical connection to buried device elements thereby enabling device functionality.
Regarding claim 2, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose wherein the one or more doped regions are doped with a P-type dopant (as discussed previously, 1110 is P+ polysilicon).
Regarding claim 3, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose wherein one or more doped regions each have a wider lateral dimension than the P-type region or the N-type region in a cross-sectional side view (as seen in the cross-sectional view of Fig. 11A, 1110 has a wider lateral dimension than 150 and 121).
Regarding claim 4, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose further comprising a first isolation structure (the left portion of “shallow trench isolation (STI) layer 130”, col. 4, lines 18-19, is a first isolation structure) and a second isolation structure (the right portion of 130 is a second isolation structure);
wherein:
the diode is disposed between the first isolation structure and the second isolation structure in a cross-sectional side view (as seen in Fig. 11A, 150, 121, and 140 are horizontally between the left and right portions of 130); and
the one or more doped regions span laterally from the first isolation structure to the second isolation structure (as seen in Fig. 11A, 1110, spans laterally from the left portion of 130 to the right portion of 130).
Regarding claim 5, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose wherein the one or more doped regions include a first doped region vertically aligned with the P-type region of the diode (as seen in Fig. 11A, the top horizontal region of 1110 is vertically aligned with 150) and a second doped region vertically aligned with the N-type region of the diode (as seen in Fig. 11A, the vertical portions of 1110 are vertically aligned with 121).
Regarding claim 6, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose further comprising a dielectric layer (“oxide layer 910”, col. 8, line 12, where “Oxide layer 910 may be deposited using a suitable CVD process and may have a thickness of around 50 nm to 200 nm over the top of fin 121. Oxide layer 910 may provide passivation for exposed semiconductor surfaces and may provide an insulating substrate upon which upper levels, for example, metal wiring, may be formed”, col. 8, lines 13-19, insulating oxide layers are known in the art as dielectrics) disposed over the second side of the diode (as seen in Fig. 11A, 910 is disposed over the top side of the diode formed by 150, 121, and 140), wherein the conductive vias each extend vertically through the dielectric layer (as seen in Fig. 11A, 1120 extend vertically through 910).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 7,560,784 B2, published 07/14/2009) in view of Gaul et al. (US 20240072041 A1, filed 08-24-2022) in view of Iguchi et al. (US 10,727,060 B2, published 07/28/2020).
Regarding claim 10, Figs. 10A-11B of Cheng disclose the device of claim 1, Figs. 11A and 11B of Cheng further disclose wherein the diode is formed in a first region of the device (as seen in Fig. 11A, the diode formed by 150, 121, and 140 is in a first region).
Cheng fails to disclose “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed.”
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However, in a similar field of endeavor, Figs. 1-21 of Gaul teach a second region (“second Region II”, [0015], which is a “logic/SRAM active area”, [0015], Gaul also teaches “first Region I”, [0015], which is a “a diode active area”, [0015]. As per [0050], “Referring to FIG. 1, a top-down diagram, the present process flow will involve the formation of an ideal vertical P-N-P diode in a first region (Region I)”, Gaul discloses a PNP diode, however a secondary reference will be used below to equate the PIN diode of Cheng and the PNP diode of Gaul) in which a plurality of gate-all- around (GAA) transistors is formed (“Referring to FIG. 1, a top-down diagram, the present process flow will involve the formation of …a gate-all-around nanosheet logic/SRAM device in a second region (Region II) of the substrate 102 (see logic/SRAM active area)”, [0050], where “For ease and clarity of description, the fabrication of a single ideal vertical P-N-P diode and nanosheet logic/SRAM device is depicted in the figures. However, it is to be understood that multiple integrated nanosheet/diode devices can be produced on a common substrate in the same manner as described herein”, [0050]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second region in which a plurality of gate-all-around (GAA) transistors is formed” as taught by Gaul in the system of Cheng for the purpose of shrinking device size by incorporating multiple types of devices on the same substrate.
Cheng in combination with Gaul fails to disclose “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed”.
However, in a similar field of endeavor, Iguchi states “the p-n junction-diode has been described as a typical example of a semiconductor device, but the semiconductor device is not limited to the p-n junction-diode. For example, a p-i-n diode, a p-n-p diode, a p-i-p diode, an n-p-n diode, an n-i-n diode and the like may be used”, col. 20, lines 63-67, and col. 21, line 1, thus the PIN diode disclosed by Cheng and the PNP diode disclosed by Gaul can be considered equivalent structures and the first region disclosed by Cheng can be combined with the second region disclosed by Gaul).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed” as taught by Iguchi in the system of Cheng in combination with Gaul for the purpose of identifying functionally similar diode structures.
Claims 11 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 7,560,784 B2, published 07/14/2009) in view of Nishikawa et al. (US 20170077218 A1, published 03/16/2017).
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Regarding claim 11, Figs. 11A and 11B of Cheng disclose a device (see title), comprising:
an active region (together “P+ doped layer 150”, col. 4, line 26, “semiconductor fin 121”, col. 4, line 11, and “intrinsic layer 140”, col. 4, line 25, form an active region, Cheng does not specify that 150, 121, and 140 are an active region, however a secondary reference will be used to teach this limitation below) that includes a plurality of interleaving first semiconductor layers and second semiconductor layers (“in a particular embodiment, N+ doped layer 120, fin 121, and P+ doped layer 150 may be made from silicon and the intrinsic layer 140 may be made from one of germanium and silicon germanium”, col. 5, lines 2-5, thus silicon is a first semiconductor layer and germanium is a second semiconductor layer, and as seen in Fig. 11A, 121, 140, and 150 are interleaving);
a PIN diode (“In one embodiment of the invention, a P+ polysilicon stripe 1110 may be deposited adjacent to the PIN diode as illustrated in FIG. 11”, col. 8, lines 49-51, thus the structure shown in Figs. 11A and 11B is a PIN diode) formed in the active region, the PIN diode including a P-type component (150), an N-type component (“semiconductor fin 121 may project outwards from a surface of the N+ doped layer 120 as illustrated in FIG. 1. Fin 121 may have a similar concentration of dopant as the N+ doped layer 120”, col. 4, lines 11-14), and an undoped component (140) disposed between the P-type component and the N-type component (as seen in Fig. 11A, 140 is disposed between 150 and 121, as 150, 121, and 140 form the active region, the PIN diode is necessarily in the active region);
a first conductive contact (“contacts 1120”, col. 8, line 54, specifically the top portion of 1120 visible in Fig. 11B, and denoted “1120P” in annotated Fig. 11B is a first conductive contact) and a second conductive contact (the top portion of 1120 visible in Fig. 11B, and denoted “1120N” in annotated Fig. 11B is a second conductive contact) disposed over a first side of the PIN diode (as seen in Figs. 11A and 11B, the top portions of 1120 are disposed on the upper side of the PIN diode) wherein the first conductive contact and the second conductive contact are electrically coupled to the P-type component (“The P+ polysilicon stripe 1110 may be formed, for example, by conventional CVD deposition of poly-crystalline silicon, adjacent to the P+ doped region 150 such that one or more contacts 1120 are electrically coupled with the P+ doped layer 150, as illustrated in FIG. 11”, col. 8, lines 51-55, “contacts 1120” as referenced by Cheng in Fig. 11A include a vertical portion and the top portion denoted 1120P discussed above) and the N-type component (Cheng does not explicitly disclose an electrical connection between 1120N and 120, however in a separate embodiment Cheng states “Contacts 1010 may be formed in the oxide layer 910 to provide access to the cathode (N+) and anode (P+) regions of the PIN diode, as illustrated in the cross sectional view of the PIN diode in FIG. 10”, col. 8, lines 20-24, thus one having ordinary skill in the art would recognize that the embodiment shown in Figs. 11A and 11B would have a similar structure where 1120N is electrically conned to the cathode, 121, of the PIN diode), respectively;
a dielectric structure (“shallow trench isolation (STI) layer 130”, col. 4, lines 18-19 where “a LOCal Oxidation of Silicon (LOCOS) procedure may be used to develop STI layer 130”, col. 6, lines 55-56, silicon oxide is known in the art as a dielectric, thus 130 is a dielectric structure) disposed over a second side of the PIN diode opposite from the first side (as seen in Fig. 11A, 130 is disposed over a bottom side of the PIN diode, opposite from the top side); and
one or more doped regions (“P+ polysilicon stripe 1110”, col. 8, lines 49-50) disposed between the PIN diode and the dielectric structure (as seen in Fig. 11A, a portion of 1110 is between a portion of 150/140/121 and a portion of 130), wherein the one or more doped regions each include a P-type dopant (as mentioned previously, 1110 includes P+ dopant).
Cheng fails to disclose “an active region”.
However, in a similar field of endeavor, Figs. 1 and 2 of Nishikawa teach an active region (“the PIN diode 100 is configured to include an active region and a termination region surrounding the active region. The active region functions as a region where current flows mainly at the time of forward bias of the PIN diode 100”, [0019], thus as the current must necessarily flow between 150 and 121 under forward bias, 150, 121, and 140 form an active region).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an active region” as taught by Nishikawa in the system of Cheng for the purpose of identifying the region in which current will flow during device use.
Regarding claim 21, Figs. 11A-11B of Cheng in combination with Figs. 1 and 2 of Nishikawa disclose the device of claim 11, Figs. 11A and 11B of Cheng further disclose wherein one or more doped regions each have a wider lateral dimension than the P-type region or the N-type region in a cross-sectional side view (as seen in the cross-sectional view of Fig. 11A, 1110 has a wider lateral dimension than 150 and 121).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al (US 7,560,784 B2, published 07/14/2009) in view of Nishikawa et al. (US 20170077218 A1, published 03/16/2017) in view of Gaul et al. (US 20240072041 A1, filed 08-24-2022) in view of Iguchi et al. (US 10,727,060 B2, published 07/28/2020).
Regarding claim 23, Figs. 11A-11B of Cheng in combination with Figs. 1 and 2 of Nishikawa disclose the device of claim 11, Figs. 11A and 11B of Cheng further disclose wherein the diode is formed in a first region of the device (as seen in Fig. 11A, the diode formed by 150, 121, and 140 is in a first region).
Cheng in combination with Nishikawa fails to disclose “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed.”
However, in a similar field of endeavor, Figs. 1-21 of Gaul teach a second region (“second Region II”, [0015], which is a “logic/SRAM active area”, [0015], Gaul also teaches “first Region I”, [0015], which is a “a diode active area”, [0015]. As per [0050], “Referring to FIG. 1, a top-down diagram, the present process flow will involve the formation of an ideal vertical P-N-P diode in a first region (Region I)”, Gaul discloses a PNP diode, however a secondary reference will be used below to equate the PIN diode of Cheng and the PNP diode of Gaul) in which a plurality of gate-all- around (GAA) transistors is formed (“Referring to FIG. 1, a top-down diagram, the present process flow will involve the formation of …a gate-all-around nanosheet logic/SRAM device in a second region (Region II) of the substrate 102 (see logic/SRAM active area)”, [0050], where “For ease and clarity of description, the fabrication of a single ideal vertical P-N-P diode and nanosheet logic/SRAM device is depicted in the figures. However, it is to be understood that multiple integrated nanosheet/diode devices can be produced on a common substrate in the same manner as described herein”, [0050]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a second region in which a plurality of gate-all-around (GAA) transistors is formed” as taught by Gaul in the system of Cheng in combination with Nishikawa for the purpose of shrinking device size by incorporating multiple types of devices on the same substrate.
Cheng in combination with Nishikawa and Gaul fails to disclose “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed”.
However, in a similar field of endeavor, Iguchi states “the p-n junction-diode has been described as a typical example of a semiconductor device, but the semiconductor device is not limited to the p-n junction-diode. For example, a p-i-n diode, a p-n-p diode, a p-i-p diode, an n-p-n diode, an n-i-n diode and the like may be used”, col. 20, lines 63-67, and col. 21, line 1, thus the PIN diode disclosed by Cheng and the PNP diode disclosed by Gaul can be considered equivalent structures and the first region disclosed by Cheng can be combined with the second region disclosed by Gaul).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the device further comprises a second region in which a plurality of gate-all- around (GAA) transistors is formed” as taught by Iguchi in the system of Cheng in combination with Nishikawa and Gaul for the purpose of identifying functionally similar diode structures.
Allowable Subject Matter
Claims 7-9, 12, 13, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the device as recited in the claims of the instant application.
Regarding claim 7, the prior art of Cheng et al (US 7,560,784 B2) discloses a similar device but fails to disclose the specific claims of the instant application regarding the multilayered structure of the undoped region e.g. “wherein the undoped intrinsic region includes a plurality of first semiconductor layers and a plurality of second semiconductor layers, the first semiconductor layers interleaving with the second semiconductor layers.”
Claims 8 and 9 are allowable by virtue of their dependence on claim 7.
Regarding claim 12, the prior art of Cheng et al (US 7,560,784 B2) in combination with Nishikawa et al. (US 20170077218 A1) discloses a similar device but fails to disclose the specific claims of the instant application regarding the arrangement of the conductive vias and the dielectric structure, e.g. “further comprising one or more conductive vias that each extend through the dielectric structure”.
Regarding claim 13, the prior art of Cheng et al (US 7,560,784 B2) in combination with Nishikawa et al. (US 20170077218 A1) discloses a similar device but fails to disclose the specific claims of the instant application regarding the arrangement of each doped region of the one or more doped regions and the P-type and N-type components, e.g. “wherein each doped region of the one or more doped regions is spaced apart from the P-type component and from the N-type component.”
Regarding claim 22, the prior art of Cheng et al (US 7,560,784 B2) discloses a similar device but fails to disclose the specific claims of the instant application regarding the multilayered structure of the undoped region e.g. “wherein the undoped component of the PIN diode includes a plurality of interleaving silicon layers and silicon germanium layers.”
Claims 24-27 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the device as recited in the claims of the instant application.
Regarding claim 24, the prior art of Cheng et al (US 7,560,784 B2) discloses a similar device but fails to disclose the specific claims of the instant application regarding the multilayered structure of the undoped region e.g. “wherein the undoped component includes a plurality of silicon layers and a plurality of silicon germanium layers that interleave with the silicon layers”.
Claims 25-27 are allowable by virtue of their dependence on claim 24.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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