Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-16 and 21-24 are pending in this application.
Applicant’s election without traverse of Invention I, claims 1-16 and newly added claims 21-24 in the reply filed on February 11, 2026 is acknowledged.
All nonelected claims were cancelled in the reply filed on February 11, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 23, 2023 is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed February 11, 2026. Claims 17-20 are cancelled. Claims 21-24 are newly added. The Examiner notes that claims 1-16 and 21-24 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Waller (“How to stop the antenna effect from destroying your circuit”, published September 2021) in view of Wei (US 2023/0069107 A1), Arakawa (US 2006/0226485 A1), and Li (US 2025/0056865 A1).
With respect to claim 1, Waller teaches in Fig. 3, which is annotated below:
A method, comprising:
providing a workpiece comprising:
a diode in a substrate,
a first transistor comprising a source/drain feature in and over the substrate,
and an interconnect structure disposed over the substrate
wherein the diode is electrically coupled to the S/D feature by a first part of the plurality of frontside conductive features of the interconnect structure);
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Waller fails to teach:
and an interconnect structure disposed over the substrate and comprising a multi-layer dielectric structure and a plurality of frontside conductive features disposed in the multi-layer dielectric structure,
providing a carrier piece comprising a carrier substrate and a bonding layer over the carrier substrate;
forming a first trench through the bonding layer;
forming a metal feature in the first trench;
attaching the carrier piece to the interconnect structure, such that the metal feature directly contacts one of the plurality of frontside conductive features,
wherein the metal feature is electrically coupled to the diode by a second part of the plurality of frontside conductive features of the interconnect structure;
performing a first plasma etching process to a back side of the substrate to form a second trench exposing a bottom surface of the S/D feature;
and forming a first backside conductive feature in the second trench and electrically coupled to the S/D feature.
Wei teaches in Figs. 4a to 4c:
and an interconnect structure disposed over the substrate (interconnect region 104) and comprising a multi-layer dielectric structure (dielectric layers 118) and a plurality of frontside conductive features (123) disposed in the multi-layer dielectric structure,
providing a carrier piece (carrier region 106) comprising a carrier substrate (carrier substrate 125) and a bonding layer (dielectric layer 126) over the carrier substrate (125);
forming a first trench (para. 41 “Recesses may be etched through dielectric layer 126 above one or more of the doped regions, such as doped regions 128 and 130, using RIE or any other suitable anisotropic dry etching technique. Afterwards, the recesses may be filled with conductive material to form conductive pads 124”) through the bonding layer (126);
forming a metal feature (pads 124) in the first trench;
attaching the carrier piece to the interconnect structure (see Fig. 4a, para. 43),
such that the metal feature directly contacts one of the plurality of frontside conductive features (para. 43 “Carrier region 106 may be aligned such that one or more of conductive pads 124 on carrier substrate 125 make contact with one or more corresponding conductive vias 123 of interconnect region 104”)
Waller discloses the claimed invention except for the carrier device and structure of the interlayer dielectric structure. Wei teaches that it is known to include an interlayer dielectric structure attached to a device layer as shown that connects to a carrier substrate to create a current path to prevent plasma damage. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the frontside interconnect structure with multiple layers of metal and dielectric connected carrier structure to the interconnect structure of Waller for the purpose of reducing damage during backside processing. See MPEP 2144.
Waller differs from the claimed invention because the diode appears to be a single well embedded in the substrate. Arakawa teaches that it is known for the diode to be a PN junction diode in which the N-well is connected to the device and the charge is routed through the p-well into another discharge path rather than directly into the substrate from the well. Wei teaches that such a discharge path may be into frontside carrier substrate rather than a backside support substrate. Therefore, further modifying Waller/Wei by Arakawa teaches:
wherein the metal feature (124 of Wei) is electrically coupled to the diode (diode of Waller modified to include PN diode 72 of Arakawa, see annotated Fig. 13 of Arakawa below) by a second part of the plurality of frontside conductive features of the interconnect structure;
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Waller/Wei discloses the claimed invention except for the connection between the diode and the carrier substrate. Arakawa teaches that it is known to route a discharge path through a diode into a substrate, and Wei teaches that the substrate can be a carrier substrate on the frontside of the device layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller such that the current path is routed through the diode into a second interconnection line such as the interconnection of Wei for the purpose of reducing damage during backside processing. See MPEP 2144.
Li teaches in Fig. 12A:
performing a first plasma etching process to a back side of the substrate to form a second trench exposing a bottom surface of the S/D feature (para. 103 “a plasma etch process using HBr chemistry can be conducted on the semiconductor structure 100 to selectively remove the BILD 710. As shown in the figures, etching the BILD 710 increases a size of the second openings 1206 exposing portions of one or more source/drain regions 140”);
and forming a first backside conductive feature (backside metal contacts 1360) in the second trench and electrically coupled to the S/D feature (source/drain regions 140).
Waller/Wei/Arakawa discloses the claimed invention except the plasma etching to create a backside contact connected to the source/drain. Li teaches that it is known to use plasma etching to make a backside power rail attached to a S/D feature. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller/Wei/Arakawa such that a backside connection is created through plasma etching for the purpose of spacing apart wires in the device. See MPEP 2144.
With respect to claim 2, Waller further teaches:
and wherein the workpiece further comprises:
a second transistor adjacent to the diode and comprising an active region (channel portion between S and D) and a metal gate structure (“G”) disposed over the active region,
a gate via disposed over and contacting the metal gate structure, (see annotated Fig. 3 above.)
and third contacts disposed over the S/D feature (interface between S and interconnect) and electrically connecting the S/D feature to the first part of the plurality of frontside conductive features of the interconnect structure (see annotated Fig. 3 above).
Arakawa further teaches:
wherein the diode comprises a P well (portion of 72 labeled “P” in Arakawa) and an N well (portion of 72 labeled “N”),
first contacts (interface between “P” and interconnect structure) disposed over the P well (“P”) and electrically connecting the P well to the second part of the plurality of frontside conductive features of the interconnect structure (labeled in annotated Fig. 13 above), second contacts (interface between “N” and via 81) disposed over the N well (“N”) and electrically connecting the N well to the first part of the plurality of frontside conductive features (portion of 81 and 82 between “N” and semiconductor element 60) of the interconnect structure,
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 3, Waller modified by Arakawa and Wei further teaches:
wherein a first conductive path electrically coupling the S/D feature and the N well is formed by the second contacts (interface between N and 81 in Arakawa, analogous to the interface between the diode and the interconnect structure of Waller), the third contacts (interface between source and interconnect of Waller), and the first part of the plurality of frontside conductive features (see annotated Fig. 3 of Waller),
and wherein a second conductive path electrically coupling the P well (path between P and support substrate 51A of Arakawa) and the carrier substrate (carrier substrate of Wei, analogous to 51A of Arakawa) is formed by the first contacts (interface between P and 81), the second part of the plurality of frontside conductive features (portion of 81 between P and 51A, analogous to 123 of Wei), and the metal feature (124 of Wei).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 4, Waller further teaches:
wherein the metal gate structure (G of second transistor) is connected to the first part of the plurality of frontside conductive features by the gate via (see annotated Fig. 4 of Waller above).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 5, Wei teaches:
wherein during the performing of the first plasma etching process, the second transistor is free of electrical charges (para. 14 teaches that the purpose of Wei’s carrier and interconnection is to include a discharge pathway to ground for any plasma-induced charge that arises during backside processing)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 6, Waller modified by Arakawa and Wei further teaches:
wherein a conductive path electrically coupling the carrier substate (125 of Wei, analogous to 51a of Arakawa) and the S/D feature is formed by the metal feature (124 of Wei), the second part of the plurality of frontside conductive features (portion of 81 between P and 51A of Arakawa, analogous to 123 of Wei), the diode (72 of Arakawa), and the first part of the plurality of frontside conductive features (see annotated Fig. 3 of Waller).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 7, Wei further teaches:
further comprising electrically grounding the carrier substrate (para. 26 “electrically grounded carrier substrate 125).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 8, Li further teaches in para. 109 that the backside interconnect structure 1380 is a simplistically depicted but may be comprised of “a plurality of interconnect structures including, for example, backside power rails (BPRs) and backside power delivery network (BSPDN) made according to known techniques” It would be obvious to meet the limitation:
further comprising: forming a dielectric layer below a bottom surface of the workpiece; performing a second plasma etching process to a back side of the workpiece to form a third trench in the dielectric layer, the third trench exposing a bottom surface of the first backside conductive feature; and forming a second backside conductive feature in the third trench.
The ordinary artisan would be motivated to meet the above limitation for the purpose of forming a backside power delivery network comprising metal layers to distribute power inside dielectric layers to separate the metal layers.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 9, Wei further teaches:
wherein the workpiece further comprises an isolation feature (para. 22 “a dielectric layer 112 may be used to provide shallow trench isolation (STI)”) disposed over the diode (between the carrier substrate and the device substrate 506 which may include a diode).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 10, Waller teaches:
providing a first workpiece comprising:
a first transistor comprising a source/drain (S/D) feature,
a second transistor adjacent to the first transistor and comprising a gate structure,
a diode adjacent to the second transistor,
and an interconnect structure comprising a plurality of metal lines and vias,
wherein a first interconnect layer of the interconnect structure comprises a metal line electrically coupled to both the gate structure and the S/D feature (see annotated Fig. 3 above);
Waller fails to teach:
providing a second workpiece comprising:
a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate disposed over the first dielectric layer;
attaching the second workpiece to the first workpiece,
such that the metal feature is electrically coupled to the gate structure by the diode and the plurality of metal lines and vias;
performing a first plasma etching process to a back side of the first workpiece to form a first trench,
wherein the S/D feature is exposed in the first trench; and forming a first backside conductive feature in the first trench.
Wei teaches:
providing a second workpiece (carrier region 106) comprising:
a first dielectric layer (dielectric material 126), a metal feature extending through the first dielectric layer (contacts 124), and a carrier substrate (carrier substrate 125) disposed over the first dielectric layer;
attaching the second workpiece to the first workpiece (see Fig. 4A of Wei, the second workpiece 106 is connected to a first workpiece 104),
Waller differs from the claimed invention because the diode appears to be a single well embedded in the substrate. Arakawa teaches that it is known for the diode to be a PN junction diode in which the N-well is connected to the device and the charge is routed through the p-well into another discharge path rather than directly into the substrate from the well. Wei teaches that such a discharge path may be into frontside carrier substrate rather than a backside support substrate. Therefore, further modifying Waller/Wei by Arakawa teaches:
wherein the metal feature (124 of Wei) is electrically coupled to the gate structure (G of second transistor of Waller, analogous to gate electrode 64 of Arakawa) by the diode (diode of Waller modified to include PN diode 72 of Arakawa, see annotated Fig. 13 of Arakawa above) and the plurality of metal lines and vias (81 and 82 between “N” and 64 of Arakawa, analogous to the interconnect structure of Waller) by a second part of the plurality of frontside conductive features of the interconnect structure (portion of 81 and 82 between “P” and 51A in Arakawa);
Waller/Wei discloses the claimed invention except for the connection between the diode and the carrier substrate. Arakawa teaches that it is known to route a discharge path through a diode into a substrate, and Wei teaches that the substrate can be a carrier substrate on the frontside of the device layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller such that the current path is routed through the diode into a second interconnection line such as the interconnection of Wei for the purpose of reducing damage during backside processing. See MPEP 2144.
Li teaches in Fig. 12A:
performing a first plasma etching process to a back side of the first workpiece to form a first trench, wherein the S/D feature is exposed in the first trench; (para. 103 “a plasma etch process using HBr chemistry can be conducted on the semiconductor structure 100 to selectively remove the BILD 710. As shown in the figures, etching the BILD 710 increases a size of the second openings 1206 exposing portions of one or more source/drain regions 140”);
and forming a first backside conductive feature (backside metal contacts 1360) in the first trench.
Waller/Wei/Arakawa discloses the claimed invention except the plasma etching to create a backside contact connected to the source/drain. Li teaches that it is known to use plasma etching to make a backside power rail attached to a S/D feature. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller/Wei/Arakawa such that a backside connection is created through plasma etching for the purpose of spacing apart wires in the device. See MPEP 2144.
With respect to claim 11, Wei teaches:
wherein during the performing of the first plasma etching process, the second transistor is free of electrical charges (para. 14 teaches that the purpose of Wei’s carrier and interconnection is to include a discharge pathway to ground for any plasma-induced charge that arises during backside processing)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 12, Waller/Wei/Arakawa/Li teaches:
wherein during the performing of the first plasma etching process (etch process taught by Li),
a conductive path electrically coupling the S/D feature and the carrier substrate is formed by the plurality of metal lines and vias (interconnect between source and diode of Waller, modified by Arakawa and Wei to route the charge from the diode to a carrier substrate),
the diode (72 or Arakawa, analogous to the diode of Waller),
and the metal feature (124 of Wei).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 13, Li teaches:
wherein the gate structure (gate structure 124) wraps around a plurality of nanostructures (channel layers 112) of the second transistor and the first transistor (abstract “plurality of field effect transistors”).
The device of Waller/Arakawa differs from the claimed invention because Waller and Arakawa teach planar FETs. Li teaches that it is known for transistors to be gate all around field effect transistors that meet the limitations above. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to further modify the device of Waller/Wei/Arakawa/Li with the transistor structure of Li for the purpose of improving miniaturization and integration of the transistor device.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 14, Waller/Wei/Arakawa further teaches in Fig. 13 or Arakawa, Fig. 4 of Wei, and Fig. 3 of Waller:
wherein the diode comprises a P well (portion of 72 labeled “P” of Arakawa) and an N well (portion of 72 labeled “N” of Arakawa) laterally adjacent to the N well,
and a distance between the N well and the gate structure is less than a distance between the P well and the gate structure (“N” is closer to gate structure 64 than “P” in Fig. 13 of Arakawa),
wherein the plurality of metal lines and vias (81 and 82 of Arakawa, with the portion between the diode and the substrate analogous to 123 of Wei and the portion between the diode and transistor analogous to the interconnect structure of Waller) comprises a first portion connected to the metal feature (124 of Wei) and the P well (portion of 81 and 82 between “P” and 51A) and a second portion connected to each of the N well (portion of 81 and 82 connected to “N” and 64), the gate structure (64), and the S/D feature (interconnect structure of Waller connects gate structure to source), and wherein the first portion is spaced apart from the second portion (see Fig. 13 of Arakawa).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 15, Wei further teaches:
further comprising electrically grounding the carrier substrate (para. 26 “electrically grounded carrier substrate 125).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 16, Li further teaches in para. 109 that the backside interconnect structure 1380 is a simplistically depicted but may be comprised of “a plurality of interconnect structures including, for example, backside power rails (BPRs) and backside power delivery network (BSPDN) made according to known techniques” It would be obvious to meet the limitation:
further comprising: forming a second dielectric layer below the first backside conductive feature; performing a second plasma etching process to the back side of the first workpiece to form a second trench through the second dielectric layer, wherein the first backside conductive feature is exposed in the second trench; and forming a second backside conductive feature in the second trench.
The ordinary artisan would be motivated to meet the above limitation for the purpose of forming a backside power delivery network comprising metal layers to distribute power inside dielectric layers to separate the metal layers.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 21, Waller teaches in Fig. 3:
A method, comprising: providing a first structure comprising:
a first substrate,
a source/drain feature and a diode over the first substrate,
and an interconnect structure over the source/drain feature and the diode,
wherein the interconnect structure comprises a conductive route comprising a first portion,
wherein the first portion electrically connects the source/drain feature and an N well of the diode (See Fig. 4A, a circuit diagram associated with the structure of Fig. 5A. Node Nd2 is connected to the source of the transistor and to the anode of D2’ through the resistor R2);
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
Waller fails to teach:
wherein the interconnect structure comprises a conductive route comprising a first portion and a second portion,
providing a second structure comprising: a second substrate,
and a conductive feature connected to the second substrate;
bonding the first structure to the second structure,
such that the second portion of the conductive route electrically connects the conductive feature and a P well of the diode;
performing a first plasma etching process to a back side of the first substrate to form a first trench exposing the source/drain feature;
and forming a first backside conductive feature in the first trench.
Wei teaches in Figs. 4a to 4c:
providing a second structure comprising: a second substrate (carrier substrate 125),
and a conductive feature (conductive pads 124) connected to the second substrate (125);
bonding the first structure to the second structure (see Fig. 4a, the substrate 125 is bonded to the interconnects which connect to the device layer substrate),
Waller discloses the claimed invention except for the second substrate. Wei teaches that it is known to bond the device layer to a carrier substrate with wiring to create a current path to prevent plasma damage. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to wire a second substrate to the frontside of the device layer through the interconnect structure for the purpose of reducing damage during backside processing. See MPEP 2144.
Waller differs from the claimed invention because the diode appears to be a single well embedded in the substrate. Arakawa teaches that it is known for the diode to be a PN junction diode in which the N-well is connected to the device and the charge is routed through the p-well into another discharge path rather than directly into the substrate from the well. Wei teaches that such a discharge path may be into frontside carrier substrate rather than a backside support substrate. Therefore, further modifying Waller/Wei by Arakawa teaches:
wherein the interconnect structure (vias 81 and wiring pattern 82 of Arakawa, see Fig. 13) and comprises a conductive route comprising a first portion (portion of 81 and 82 between the N-well of 72 and the transistor), and a second portion
such that the second portion of the conductive route electrically connects the conductive feature and a P well of the diode (portion of 18 and 82 between P-well of diode 72 and substrate 51A, which has a function analogous to the carrier substrate 125 of Wei except stacked on the backside instead of the frontside);
such that the second portion of the conductive route (portion of 81 and 82 between P-well and 51A, which is analogous to 125 of Wei. Modifying with Wei instead routes the second portion to the metal feature 124 on the carrier 125) electrically connects the conductive feature (124 of Wei) and a P well of the diode (P of 72);
Waller/Wei discloses the claimed invention except for the connection between the diode and the carrier substrate. Arakawa teaches that it is known to route a discharge path through a diode into a substrate, and Wei teaches that the substrate can be a carrier substrate on the frontside of the device layer. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller such that the current path is routed through the diode into a second interconnection line such as the interconnection of Wei for the purpose of reducing damage during backside processing. See MPEP 2144.
Li teaches in Fig. 12A:
performing a first plasma etching process to a back side of the first substrate to form a first trench exposing the source/drain feature (para. 103 “a plasma etch process using HBr chemistry can be conducted on the semiconductor structure 100 to selectively remove the BILD 710. As shown in the figures, etching the BILD 710 increases a size of the second openings 1206 exposing portions of one or more source/drain regions 140”);
and forming a first backside conductive feature in the first trench (backside metal contacts 1360) in the second trench and electrically coupled to the S/D feature (source/drain regions 140).
Waller/Wei/Arakawa discloses the claimed invention except the plasma etching to create a backside contact connected to the source/drain. Li teaches that it is known to use plasma etching to make a backside power rail attached to a S/D feature. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Waller/Wei/Arakawa such that a backside connection is created through plasma etching for the purpose of spacing apart wires in the device. See MPEP 2144.
With respect to claim 22, Wei further teaches:
wherein during the plasma etching process, the second substrate is grounded.
(para. 26 “electrically grounded carrier substrate 125).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 23, Waller further teaches:
wherein the first structure further comprises a metal gate structure (G of second transistor as labelled in annotated Fig. 3 above) over the first substrate, wherein the first portion of the conductive route (“interconnect structure) is connected to the metal gate structure (see annotated Fig. 3 above).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
With respect to claim 24, Li further teaches in para. 109 that the backside interconnect structure 1380 is a simplistically depicted but may be comprised of “a plurality of interconnect structures including, for example, backside power rails (BPRs) and backside power delivery network (BSPDN) made according to known techniques” It would be obvious to meet the limitation:
further comprising: forming a dielectric layer below the first substrate and the first backside conductive feature; performing a second plasma etching process to the dielectric layer to form a second trench exposing the first backside conductive feature; and forming a second backside conductive feature in the second trench.
The ordinary artisan would be motivated to meet the above limitation for the purpose of forming a backside power delivery network comprising metal layers to distribute power inside dielectric layers to separate the metal layers.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Waller in view of Wei, Arakawa, and Li as explained above.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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