DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 01/21/2026.
Currently claims 1-7 and 15-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species A, claims 1-7 and 15-20, in the reply filed on 01/21/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/17/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 1, the instant claim recites “first largest planar surface" (claim 1, line 2) and “second largest planar surface" (claim 1, line 3). The term "largest" is a relative term. It modifies the target, the target being the “planar surface”. Therefore, neither the claim nor the specification reveal what acceptable range of “planar surface” is acceptable to be considered as “largest planar surface", rendering the claim indefinite. Clarification and/or correction are/is required. A review of the specification in para. [0062] or [0065] does not reveal sufficient definition of the term to define the metes and bounds of the claim. For the purpose of examination, the examiner did not give any weight to the term “largest”.
Regarding claim 15, the instant claim recites “first largest planar surface" (claim 15, line 2) and “second largest planar surface" (claim 15, line 3). The term "largest" is a relative term. It modifies the target, the target being the “planar surface”. Therefore, neither the claim nor the specification reveal what acceptable range of “planar surface” is acceptable to be considered as “largest planar surface", rendering the claim indefinite. Clarification and/or correction are/is required. A review of the specification in para. [0062] or [0065] does not reveal sufficient definition of the term to define the metes and bounds of the claim. For the purpose of examination, the examiner did not give any weight to the term “largest”.
Claims 2-7 and 16-20 are also rejected due to their dependence on a rejected base claim.
Regarding claim 4, the instant claim recites limitation in view of claim 1, where claim 4 recites “the metal layer comprises one of nickel, palladium, and gold; nickel and copper, or copper" (claim 4, line 1-2). It is unclear, whether the metal layer comprises one of “nickel, palladium, and gold” or “nickel and copper” or only “copper” or the metal layer comprises one of “nickel”, “palladium and gold”, “nickel and copper”, or “copper”, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as the latter, i.e., the metal layer comprises one of “nickel”, “palladium and gold”, “nickel and copper”, or “copper”.
Regarding claim 18, the instant claim recites limitation in view of claim 15, where claim 18 recites “the metal layer comprises one of nickel, palladium, and gold; nickel and copper, or copper" (claim 4, line 1-2). It is unclear, whether the metal layer comprises one of “nickel, palladium, and gold” or “nickel and copper” or only “copper” or the metal layer comprises one of “nickel”, “palladium and gold”, “nickel and copper”, or “copper”, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as the latter, i.e., the metal layer comprises one of “nickel”, “palladium and gold”, “nickel and copper”, or “copper”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148306 A1 (Lin) and further in view of US 2013/0299450 A1 (Song).
Regarding claim 1, Lin discloses, a method of electroless deposition (Figs. 5-7; [0018]) comprising:
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providing a semiconductor substrate (2; semiconductor wafer; Figs. 1-2; [0063]) comprising a first largest planar surface (10) and a second largest planar surface (12) (Figs. 1-2; [0063]);
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forming a backmetal layer (92/94/96; Fig. 5; [0070]) on the second largest planar surface (12, back side in Fig. 5);
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attaching a tape (100; tape; Fig. 16; [0095]) over the backmetal layer (92/94/96);
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electroless depositing a metal layer (104; over pad metallization, OPM, consists of nickel 106 and diffusion barrier 108, electroless deposited; Fig. 17; [0096]) on a pad (as annotated on Fig. 17) comprised on the first largest planar surface (10, top surface);
after electroless depositing, removing the tape (100) (Fig. 18; [0097]); and
But Lin fails to teach explicitly, after removing the tape, baking the semiconductor substrate.
However, in analogous art, Song discloses, after removing the tape, baking the semiconductor substrate ([0070] – [0071]; Song teaches that an annealing process can be performed if desired in order to remove water remaining in low-resistance metal pattern obtained by forming a plated layer and to improve the electrical properties and adhesivity of the plated layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin and Song before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of annealing the substrate as taught by Song since it improves the electrical properties and adhesivity of the plated layer ([0071]). Absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Song while forming an electroless deposition of Lin.
Regarding claim 3, Lin discloses, the method of claim 1, wherein the semiconductor substrate comprises silicon carbide ([0103]).
Regarding claim 4, Lin discloses, the method of claim 1, wherein the metal layer comprises one of nickel, palladium, and gold; nickel and copper, or copper ([0007]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and Song as applied to claim 1 and further in view of US 2022/0359230 A1 (Wirz).
Regarding claim 2, the combination of Lin and Song fails to teach explicitly, the method of claim 1, further comprising singulating the semiconductor substrate to form a plurality of semiconductor die.
However, in analogous art, Wirz discloses, the method of claim 1, further comprising singulating the semiconductor substrate (105) to form a plurality of semiconductor die (110; Fig. 3E; [0053]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin, Song and Wirz before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of singulating the semiconductor substrate as taught by Wirz since plurality of die on a substrate need to be singulated to make individual die before use. Absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Wirz while forming an electroless deposition of Lin.
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Song as applied to claim 1 and further in view of US 9,437,668 B1 (Deligianni).
Regarding claim 5, the combination of Lin and Song fails to teach explicitly, the method of claim 1, wherein baking the semiconductor substrate further comprises heating from ambient temperature to between 150 C to 350 C at a temperature ramp of less than or equal to 3 C per minute.
However, in analogous art, Deligianni discloses, the method of claim 1, wherein baking the semiconductor substrate further comprises heating from ambient temperature to between 150 C to 350 C at a temperature ramp of less than or equal to 3 C per minute (col. 9, lines 21-31).
Note: Deligianni teaches that the electrolessly plated substrates are annealed at a temperature from about 125 to 250° C for a time from about 15 to 60 minutes. It overlaps the claimed range of 150 C to 350 C. The temperature ramp is from 2.08 C to 8.33 C per minute (from 125/60 and 125/15 deg C/minute). It also overlaps the claimed range of less than or equal to 3 C per minute. In MPEP 2144.05 (I), it is stated that In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above claimed ranges since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233 (See MPEP 2144.05 (II) (A)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin, Song and Deligianni before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of substrate annealing temperature and ramp up slope as taught by Deligianni since this data is important for annealing, however, absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Deligianni while forming an electroless deposition of Lin.
Regarding claim 7, the combination of Lin, Song and Deligianni discloses, the method of claim 5, wherein baking the semiconductor substrate further comprises heating in a nitrogen atmosphere (col. 9, lines 21-31; Deligianni Ref.).
Claims 15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0148306 A1 (Lin) and further in view of US 2013/0299450 A1 (Song) and US 2021/0223489 A1 (Weng).
Regarding claim 15, Lin discloses, a method of electroless deposition (Figs. 5-7; [0018]) comprising:
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providing a semiconductor substrate (2; semiconductor wafer; Figs. 1-2; [0063]) comprising a first largest planar surface (10, top surface) and a second largest planar surface (12, back surface) (Figs. 1-2; [0063]);
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thinning the semiconductor substrate (2) from the second largest planar surface (12, back surface) to form an edge ring (80; silicon semiconductor layer; Fig. 5; [0066]);
forming a backmetal layer (92/94/96; Fig. 5; [0070]) on the second largest planar surface (12, back side in Fig. 5);
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electroless depositing a metal layer (104; over pad metallization, OPM, consists of nickel 106 and diffusion barrier 108, electroless deposited; Fig. 17; [0096]) on a pad (as annotated on Fig. 17) comprised on the first largest planar surface (10, top surface) and on the backmetal layer (92/94/96; Fig. 5; [0070]); and
But Lin fails to teach explicitly, baking the semiconductor substrate.
However, in analogous art, Song discloses, baking the semiconductor substrate ([0070] – [0071]; Song teaches that an annealing process can be performed if desired in order to remove water remaining in low-resistance metal pattern obtained by forming a plated layer and to improve the electrical properties and adhesivity of the plated layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin and Song before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of annealing the substrate as taught by Song since it improves the electrical properties and adhesivity of the plated layer ([0071]). Absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Song while forming an electroless deposition of Lin.
The combination of Lin and Song fails to teach explicitly, coupling a carrier to the first largest planar surface; demounting the carrier from the first largest planar surface;
However, in analogous art, Weng discloses, coupling a carrier (301) to the first largest planar surface (bottom surface of Fig. 3) (Fig. 3; [0068]); demounting the carrier (301) from the first largest planar surface (from the structure; Fig. 6; [0077]);
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin, Song and Weng before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of coupling a carrier to the structure before thinning it and to decouple it after other supporting structures are formed on the other side as taught by Weng since it provides a solid support to the device during thinning. Absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Weng while forming an electroless deposition of Lin.
Regarding claim 17, Lin discloses, the method of claim 15, wherein the semiconductor substrate comprises silicon carbide ([0103]).
Regarding claim 18, Lin discloses, the method of claim 15, wherein the metal layer comprises one of nickel, palladium and gold; nickel and copper, or copper ([0007]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin, Song and Weng as applied to claim 15 and further in view of US 9,437,668 B1 (Deligianni)
Regarding claim 19, Lin discloses, the method of claim 15, wherein baking the semiconductor substrate further comprises heating from ambient temperature to between 150 C to 350 C at a temperature ramp of less than or equal to 3 C per minute in a nitrogen atmosphere.
However, in analogous art, Deligianni discloses, the method of claim 15, wherein baking the semiconductor substrate further comprises heating from ambient temperature to between 150 C to 350 C at a temperature ramp of less than or equal to 3 C per minute in a nitrogen atmosphere (col. 9, lines 21-31).
Note: Deligianni teaches that the electrolessly plated substrates are annealed at a temperature from about 125 to 250° C for a time from about 15 to 60 minutes. It overlaps the claimed range of 150 C to 350 C. The temperature ramp is from 2.08 C to 8.33 C per minute (from 125/60 and 125/15 deg C/minute). It also overlaps the claimed range of less than or equal to 3 C per minute. In MPEP 2144.05 (I), it is stated that In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the above claimed ranges since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233 (See MPEP 2144.05 (II) (A)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lin, Song and Deligianni before him/her, to modify the teachings of an electroless deposition as taught by Lin and to include the teachings of substrate annealing temperature and ramp up slope as taught by Deligianni since this data is important for annealing, however, absent this important teaching in Lin, a person with ordinary skill in the art would be motivated to reach out to Deligianni while forming an electroless deposition of Lin.
Allowable Subject Matter
Claims 6, 16 and 20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2019/0148306 A1 (Lin), in combination with US 2013/0299450 A1 (Song), US 2022/0359230 A1 (Wirz) and US 9,437,668 B1 (Deligianni), fails to disclose, “the method of claim 5, further comprising removing the semiconductor substrate from an oven performing the baking when the semiconductor substrate has cooled to less than 50 C”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 16, the closest prior art, US 2019/0148306 A1 (Lin), in combination with US 2013/0299450 A1 (Song), US 2022/0359230 A1 (Wirz) and US 9,437,668 B1 (Deligianni), fails to disclose, “the method of claim 15, further comprising mounting the semiconductor substrate to a cutting tape, removing the edge ring, and singulating the semiconductor substrate to form a plurality of semiconductor die”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 20, the closest prior art, US 2019/0148306 A1 (Lin), in combination with US 2013/0299450 A1 (Song), US 2022/0359230 A1 (Wirz) and US 9,437,668 B1 (Deligianni), fails to disclose, “the method of claim 5, further comprising removing the semiconductor substrate from an oven performing the baking when the semiconductor substrate has cooled to less than 50 C”, in combination with the additionally claimed features, as are claimed by the Applicant.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0157749 A1 (Spory) – A method is disclosed including a die pad of a singular die, applying a nickel layer to the one or more die pads, applying a gold layer over the nickel layer, applying a solder paste over the gold layer, applying one or more solder balls to the solder paste, and mating the one or more solder balls to one or more bond pads of another die, a printed circuit board, or a substrate.
US 2004/0009631 A1 (Connell) - A semiconductor package is disclosed including a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
03/02/2026