DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 6/5/2026 is acknowledged.
Claims 10-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/5/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2023, 6/5/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (US 2021/0296367; hereinafter Seo) in view of Saito et al (US 2023/0309310; hereinafter Saito).
Regarding claim 1, Fig 4 of Seo discloses a transistor comprising:
a first insulating layer (102; Fig 4; ¶ [0101]) disposed on a substrate (101; Fig 4; ¶ [0099]);
a dummy layer (112; Fig 4; ¶ [0099]) disposed on the first insulating layer (102; Fig 4; ¶ [0101]);
a semiconductor layer (145; Fig 4; ¶ [0098]) disposed on the dummy layer (112; Fig 4; ¶ [0099]), the semiconductor layer including a first area (145 (left side); Fig 4), a second area (145 (right side); Fig 4), and a channel area (145; Fig 4; ¶ [0095]) disposed between the first and second areas;
a second insulating layer (114; Fig 4; ¶ [0099]) disposed on the semiconductor layer (145; Fig 4; ¶ [0098]);
a gate electrode (151; Fig 4; ¶ [0099]) overlapping the channel area (145; Fig 4; ¶ [0095]) with the second insulating (114; Fig 4; ¶ [0099]) interposed therebetween;
a third insulating layer (115; Fig 4; ¶ [0099]) disposed over the gate electrode (151; Fig 4; ¶ [0099]); a first electrode (161; Fig 4; ¶ [0098]) disposed on the third insulating layer (115; Fig 4; ¶ [0099]), the first electrode (161; Fig 4; ¶ [0098]) being electrically connected to the first area (145 (left side); Fig 4); and
a second electrode (162; Fig 4; ¶ [0098]) disposed on the third insulating layer (115; Fig 4; ¶ [0099]) spaced from the first electrode, the second electrode being electrically connected to the second area (145 (right side); Fig 4),
wherein the dummy layer (112; Fig 4; ¶ [0099]) includes hafnium oxide or zirconium oxide or titanium oxide (¶ [0108]), and
the semiconductor layer (145; Fig 4; ¶ [0098]) includes indium gallium zinc oxide (¶ [0116]).
However Seo does not expressly disclose the dummy layer includes indium oxide.
In the same field of endeavor, Saito discloses an insulating layer can comprise the materials such as hafnium oxide, zirconium oxide or indium oxide (¶ [0080]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the dummy layer can comprise indium oxide or hafnium oxide as taught by Saito for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
Regarding claim 2, Fig 4 of Seo discloses the semiconductor layer (145; Fig 4; ¶ [0098]) includes a back surface (Back surface; Fig 4) and a top surface (Top surface; Fig 4), which face each other in a thickness direction of the substrate (Fig 4); and
the dummy layer (112; Fig 4; ¶ [0099]) is disposed between the back surface of the semiconductor layer (145; Fig 4; ¶ [0098]) and the first insulating layer(102; Fig 4; ¶ [0101]).
Regarding claim 5, Fig 4 of Seo discloses the first insulating layer (102; Fig 4; ¶ [0101]) and the second insulating layer (114; Fig 4; ¶ [0099]) include silicon oxide (¶ [0102], [0117]).
Regarding claim 7, Fig 4 of Seo does not expressly disclose each of the first and second insulating layers has a hydrogen content of about 7.28E20 or less and an oxygen content of about 7.25E19 or less.
However, the ordinary artisan would have recognized the hydrogen content to be a result effective variable affecting the threshold voltage of an element. Thus, it would have been obvious to vary the hydrogen content of the insulating layers within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B
Claim(s) 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (US 2021/0296367; hereinafter Seo) in view of in view of Saito et al (US 2023/0309310; hereinafter Saito) and further in view of Takemura (US 2011/0309411; hereinafter Takemura).
Regarding claim 3, Seo in view of Saito does not expressly discloses a width of the dummy layer and a width of the semiconductor layer are same.
In the same field of endeavor, Takemura discloses a width of the dummy layer comprising indium oxide is less than 10 nm and a width of a semiconductor layer can be less than 10 nm (¶ [0038]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a width of the dummy layer and a width of the semiconductor layer are same as taught by Takemura for the purpose of forming semiconductor layers comprising claimed materials with desired thicknesses (¶ [0038]).
Regarding claim 4, Seo in view of Takemura as modified above in claim 3 discloses the dummy layer has a thickness of less than about 10 nm (¶ [0038] of Takemura).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (US 2021/0296367; hereinafter Seo) in view of in view of Saito et al (US 2023/0309310; hereinafter Saito) and further in view of Liang et al (US 2019/0019863; hereinafter Liang).
Regarding claim 7, Seo in view of Saito does not expressly disclose an additional layer provided at an interface between the top surface of the semiconductor layer and the second insulating layer.
In the same field of endeavor, Liang discloses an additional layer is provided at an interface between the top surface of the semiconductor layer and other layers formed on the semiconductor layer (¶ [0025]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that additional layers can be grown such on top of the semiconductor layer as the regrowth of the layered material is conducted to passivate the etched interface to make high-performance photonic components and integrated circuits. (¶ [0025])
Claim(s) 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (US 2021/0296367; hereinafter Seo) in view of Saito et al (US 2023/0309310; hereinafter Saito) as applied to claim 1 and further in view of Seo et al (US 2023/0217759; hereinafter Seo_1).
Regarding claim 8, Seo in view of Saito does not expressly disclose a bottom metal pattern disposed between the substrate and the first insulating layer.
In the same field of endeavor, Fig 3 of Seo_1 discloses a bottom metal pattern (LS; Fig 3; ¶ [0092]) disposed between a substrate (GLS; Fig 3) and a first insulating layer (BUF; Fig 3; ¶ [0093]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a bottom metal pattern is disposed between the substrate and the first insulating layer as the lower metal pattern functions to block external light from being incident into a semiconductor layer. (¶ [0092])
Regarding claim 9, Seo in view of Saito in view of Seo_1 (Seo_1 in particular) as modified above in claim 8 discloses the bottom metal pattern blocks light introduced into a back surface of the substrate (¶ [0092] of Seo_1).
Claim(s) 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al (US 2021/0296367; hereinafter Seo) in view of Saito et al (US 2023/0309310; hereinafter Saito) and Seo et al (US 2023/0217759; hereinafter Seo_1).
Regarding claim 18, Fig 4 of Seo discloses a display device, comprising:
a light emitting element (180; Fig 4; ¶ [0152]); and
a transistor electrically connected to the light emitting element, wherein the transistor includes:
a first insulating layer (102; Fig 4; ¶ [0101]) disposed on a substrate (101; Fig 4; ¶ [0099]);
a dummy layer (112; Fig 4; ¶ [0099]) disposed on the first insulating layer (102; Fig 4; ¶ [0101]);
a semiconductor layer (145; Fig 4; ¶ [0098]) disposed on the dummy layer (112; Fig 4; ¶ [0099]), the semiconductor layer including a first area (145 (left side); Fig 4), a second area (145 (right side); Fig 4), and a channel area (145; Fig 4; ¶ [0095]) disposed between the first and second areas;
a second insulating layer (114; Fig 4; ¶ [0099]) disposed on the semiconductor layer (145; Fig 4; ¶ [0098]);
a gate electrode (151; Fig 4; ¶ [0099]) overlapping the channel area (145; Fig 4; ¶ [0095]) with the second insulating (114; Fig 4; ¶ [0099]) interposed therebetween;
a third insulating layer (115; Fig 4; ¶ [0099]) disposed over the gate electrode (151; Fig 4; ¶ [0099]); a first electrode (161; Fig 4; ¶ [0098]) disposed on the third insulating layer (115; Fig 4; ¶ [0099]), the first electrode (161; Fig 4; ¶ [0098]) being electrically connected to the first area (145 (left side); Fig 4); and
a second electrode (162; Fig 4; ¶ [0098]) disposed on the third insulating layer (115; Fig 4; ¶ [0099]) spaced from the first electrode, the second electrode being electrically connected to the second area (145 (right side); Fig 4),
wherein the dummy layer (112; Fig 4; ¶ [0099]) includes hafnium oxide or zirconium oxide or titanium oxide (¶ [0108]), and
the semiconductor layer (145; Fig 4; ¶ [0098]) includes indium gallium zinc oxide (¶ [0116]).
However Seo does not expressly disclose the dummy layer includes indium oxide and a bottom metal pattern disposed on a substrate.
In the same field of endeavor, Saito discloses an insulating layer can comprise the materials such as hafnium oxide, zirconium oxide or indium oxide (¶ [0080]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the dummy layer can comprise indium oxide or hafnium oxide as taught by Saito for the purpose of substituting art recognized equivalents known to be used for the same purpose (MPEP 2144.06).
In the same field of endeavor, Fig 3 of Seo_1 discloses a bottom metal pattern (LS; Fig 3; ¶ [0092]) disposed between a substrate (GLS; Fig 3) and a first insulating layer (BUF; Fig 3; ¶ [0093]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a bottom metal pattern is disposed between the substrate and the first insulating layer as the lower metal pattern functions to block external light from being incident into a semiconductor layer. (¶ [0092])
Regarding claim 19, Fig 4 of Seo discloses the semiconductor layer (145; Fig 4; ¶ [0098]) includes a back surface (Back surface; Fig 4) and a top surface (Top surface; Fig 4), which face each other in a thickness direction of the substrate (Fig 4); and
the dummy layer (112; Fig 4; ¶ [0099]) is disposed between the back surface of the semiconductor layer (145; Fig 4; ¶ [0098]) and the first insulating layer (102; Fig 4; ¶ [0101]).
Regarding claim 20, Fig 4 of Seo discloses the light emitting element includes:
a pixel electrode (181; Fig 4; ¶ [0152]) electrically connected to the transistor;
a light emitting layer (182; Fig 4; ¶ [0152]) provided on the pixel electrode; and
a common electrode (183; Fig 4; ¶ [0152]) provided over the light emitting layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Lius et al (US 2023/0359097)
Seo et al (US 2023/0217759)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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