DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention II, Species III (claims 15-31) in the reply filed on 2/26/26 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 27 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In claim 27, the applicant states the limitation “wherein the diffusion barrier layer
comprises a different material that the first interfacial layer and the second interfacial layer.”; however, the limitation is not described in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15, 18, 20, and 31 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoo US 2018/0240804 A1. Yoo discloses (see, for example, FIG. 1) a fabricating method of a semiconductor device 1 comprising forming a gate structure 155/10, channel region of a semiconductor substrate 101, forming the gate structure comprises depositing an interfacial layer 115, depositing a zirconium-containing dielectric layer 135a, forming a gate electrode 155, and forming source/drain regions 102/103 in the semiconductor substrate 101. In paragraph [0023], Yoo discloses the dielectric layer 135a being a zirconium-containing dielectric layer, in paragraph [0034], Yoo discloses the material of the gate structure 10 includes a tetragonal crystal system.
Regarding claim 18, see, for example, FIG. 1, and paragraph [0031] wherein Yoo discloses depositing a diffusion barrier layer 145, and its material including aluminum oxide.
Regarding claim 20, see, for example, FIG. 1, and paragraph [0021] wherein Yoo discloses a first interfacial layer 115 made of silicon oxide. In FIG. 1, and paragraph [0024], Yoo further discloses a second interfacial layers 125a, and states these layers may include titanium.
Regarding claim 31, see, for example, FIG. 1 wherein Yoo discloses the zirconium-containing dielectric layer 135a being in contact with second interfacial layer 125a.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo US 2018/0240804 A1 as applied to claims 15, 18, 20, and 31 above, and further in view of Heo et al. US 2024/0038890 A1. Yoo does not clearly disclose performing an annealing process at a temperature in a range from about 400 C to about 900 C after forming the gate electrode. However, Heo discloses (see, for example, FIG. 8F) performing an annealing after forming a gate electrode GA. In paragraph [0119], Heo further discloses annealing preformed at a temperature in a range of about 400 C to about 1200 C. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to perform an annealing process at a temperature in a range from about 400 C to about 900 C after forming the gate electrode in order to induce anti-ferroelectricity and reduce defects in the gate electrode, which thereby improve overall stability of the gate electrode. Further, it would have been obvious to one of ordinary skill in the art at the time of invention was made to use this value, since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
In view of the 112 rejection above, claim(s) 17, 19, and 25 thru 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo US 2018/0240804 A1 as applied to claims 15, 18, 20, and 31 above, and further in view of Koo et al. US 2023/0099330 A1. Yoo discloses (see, for example, paragraph [0024]) discloses doping with nitrogen; however, Yoo does not clearly disclose performing an implantation process to the zirconium-containing dielectric layer with nitrogen. However, Koo discloses (see, for example, FIG. 1, and paragraph [0060] and [0062]) performing an implantation process to a zirconium-containing dielectric layer 110 with nitrogen. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to perform an implantation process to the zirconium-containing dielectric layer with nitrogen in order to use a method that is well known in the art for superior control in depth, concentration, and position of a dopant according to the preferences of the user.
Regarding claim 19, see, for example, FIG. 1, and paragraph [0031] wherein Yoo discloses depositing a diffusion barrier layer 145, and its material including aluminum oxide.
Regarding claim 25, see, for example, FIG. 1, and paragraph [0021] wherein Yoo discloses a first interfacial layer 115 made of silicon oxide. In FIG. 1, Yoo further discloses second interfacial layers 125a, and further discloses (see, for example, paragraph [0024]) that these layers may include materials such as hafnium oxide, carbon, silicon, etc.
Regarding claim 26, see, for example, FIG. 1, and paragraph [0031] wherein Yoo discloses depositing a diffusion barrier layer 125c, and may include a same material.
Regarding claim 27, see, for example, FIG. 1, and paragraph [0031] wherein Yoo discloses depositing a diffusion barrier layer 145, and may include aluminum oxide.
Claim(s) 21 thru 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoo US 2018/0240804 A1 as applied to claims 15, 18, 20, and 31 above. Yoo does not clearly disclose a thickness of the interfacial layer being in a range from about 5 A to about 3 nm, and a range from about 1 A to about 50 nm. However, it would have been obvious to one of ordinary skill in the art to one of ordinary skill in the art, at a time prior to the effective filing date, to have a thickness of the interfacial layer being in a range from about 5 A to about 3 nm, and a range from about 1 A to about 50 nm in order to have a stable interface that suppresses interfacial defects between the gate structure and substrate according the preferences of the user, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 23, and 24, Yoo does not clearly disclose a thickness of the zirconium-containing dielectric layer being in a range from about 3 nm to about 7 nm, and a thickness of being a range from about 1 A to about 50 nm. However, it would have been obvious to one of ordinary skill in the art to one of ordinary skill in the art, at a time prior to the effective filing date, to have a thickness of the zirconium-containing dielectric layer being in a range from about 3 nm to about 7 nm, and a thickness of being a range from about 1 A to about 50 nm in order to minimize strain, and thereby reduce defects in the gate structure according the preferences of the user, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Allowable Subject Matter
Claims 28 thru 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The references of record, either singularly or in combination, do not teach or suggest at least a fabricating method of a semiconductor device, comprising: wherein the zirconium-containing dielectric layer has a top portion and a bottom portion opposing each other, and the bottom portion is in contact with the interfacial layer, wherein the implantation process is performed such a nitrogen atomic concentration at the top portion is higher than a nitrogen atomic concentration at the bottom portion.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Eugene Lee
March 8, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815