Prosecution Insights
Last updated: May 29, 2026
Application No. 18/493,293

INTERCONNECTION STRUCTURE

Final Rejection §102§103
Filed
Oct 24, 2023
Examiner
YI, CHANGHYUN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
94%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
1001 granted / 1067 resolved
+25.8% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 9m
Avg Prosecution
41 currently pending
Career history
1112
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
61.1%
+21.1% vs TC avg
§102
18.4%
-21.6% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1067 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Amendment filed on 4/17/26 has been entered. Response to Arguments Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection. Withdrawal of Allowability The previously indicated allowability of claims is withdrawn in view of the newly discovered reference(s) to Yang (US 20210398898) with regard to the amendment. Rejections based on the newly cited reference(s) follow. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-4, 15 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 20210398898). Regarding claim 1. Fig 1 of Yang discloses An interconnection structure, comprising: a substrate 102 that is formed with a first metal trench 106 [0016]; a boron nitride dielectric 116 [0018] that is disposed over the substrate; a second metal trench 112 [0016] that is formed in the boron nitride dielectric; and a metal via 110 ([0017]/[0034]/[0035]: made from 502, which is metal; refer to Fig 5 for 502) that is disposed to interconnect the first metal trench and the second metal trench, wherein the second metal trench has a width that gradually increases from top to bottom (Fig 1). Regarding claim 2. (Currently amended) Yang discloses The interconnection structure according to claim 1, wherein the metal via has a width that gradually increases from top to bottom (Fig 1). Regarding claim 3. (Original) Yang discloses The interconnection structure according to claim 1, further comprising a first metal protection film 114 that is disposed between the second metal trench and the boron nitride dielectric (Fig 1), and that has a thermal conductivity smaller than 1 W/(m-K) ([0040]: 114 is made of low-k SiOC, which inherently has less than 1 W/m-k thermal conductivity). Regarding claim 4. (Original) Yang discloses The interconnection structure according to claim 3, further comprising another dielectric 118 ([0041]: air spacer, which has function as an ultra-low-k dielectric layer) disposed between the substrate and the boron nitride dielectric (Fig 1), wherein the metal via is formed in the another dielectric (Fig 1: 110 is in between 118), and the first metal protection film is further disposed between the boron nitride dielectric and the another dielectric (Fig 1). Regarding claim 15. (Currently amended) Yang discloses A method for fabricating an interconnection structure, comprising steps of: forming a metal via 110 ([0017]/[0034]/[0035]: made from 502, which is metal; refer to Fig 5 for 502) over a first metal trench 106 that is formed in a substrate 108/102 (Fig 6); forming a trench feature (Fig 6: 112 is in formed in the trench between 112) over the metal via, the trench feature including a metal portion (112, which is metal [0023]) (Fig 6); and forming a first dielectric 116 after the trench feature is formed, the first dielectric including boron nitride [0018] and surrounding the trench feature (Fig 7). Regarding claim 21. (New) Yang discloses The method according to claim 15, wherein the trench feature has a width that gradually increases from top to bottom (Fig 7). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210398898) in view of Usami (US 20150228586). Regarding claim 4. (Original) Yang discloses The interconnection structure according to claim 3. But Yang does not disclose further comprising another dielectric disposed between the substrate and the boron nitride dielectric, wherein the metal via is formed in the another dielectric, and the first metal protection film is further disposed between the boron nitride dielectric and the another dielectric. However, Fig 13 of Usami discloses another dielectric (INS2) disposed between the substrate (INS1) and the boron nitride dielectric (INS3) ([0042]: ‘INS3 is made of a material similar to INS2’, and [0041]: INS2 is made of boron carbon nitride, thus incudes boron nitride), wherein the metal via (M1W) is formed in the another dielectric, and the first metal protection film (BR1) is further disposed between the boron nitride dielectric and the another dielectric. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Yang’s device structure to have the Usami’s structure for the purpose of providing reduced length of signal paths and lowering capacitance, stacked vias on low-k materials allow for higher signal frequencies. Regarding claim 5. (Original) Yang in view of Usami discloses The interconnection structure according to claim 4, Usami discloses wherein the another dielectric includes boron nitride ([0041]: INS2 is made of boron carbon nitride, thus incudes boron nitride). Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Usami (US 20150228586) in view of Yang (US 20210398898). Regarding claim 8. (Currently amended) Fig 13 of Usami discloses An interconnection structure, comprising: a substrate (INS1) that is formed with a first metal trench (M1V); a first dielectric (INS2) that is disposed over the substrate; a metal via (M1W, [0041]/[0048]) that is disposed in the first dielectric and that is connected to the first metal trench; a second dielectric (INS3), that is disposed over the first dielectric and that includes boron nitride ([0042]: ‘INS3 is made of a material similar to INS2’, and [0041]: INS2 is made of boron carbon nitride, thus incudes boron nitride); a second metal trench (M2W) that is disposed in the second dielectric and that is connected to the metal via (Fig 13); and a first metal protection film (BR1) that surrounds the second metal trench (BR1 surrounding the bottom portion of M2W); wherein the first metal protection film has a thermal conductivity smaller than 1 W/(m-K) ([0042]: the BR1 is made of low-k SiCN, which inherently has less than 1W/m-k thermal conductivity). But Usami does not explicitly disclose a first metal protection film that separates the second metal trench from the second dielectric. However, Fig 1 of Yang discloses a first metal protection film 116 that surrounds the second metal trench 112 and that separates the second metal trench from the second dielectric 114. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Usami’s interconnection structure to have the Yang’s structure for the purpose of providing improving electrical performance with tapered profiles (often referred to as sloped or chamfered vias), which is crucial for successful void-free metal filling in high-aspect-ratio structures. Regarding claim 9. (Original) Usami in view of Yang discloses The interconnection structure according to claim 8, Fig 1 of Yang discloses a bottom width of the second metal trench 112 is greater than a top width of the second metal trench (Fig 1); and a bottom width of the metal via 110 is greater than a top width of the metal via (Fig 1). Regarding claim 11. (Currently amended) Usami in view of Yang discloses The interconnection structure according to claim 8, Usami discloses wherein the first metal protection film is disposed over the first dielectric and under the second dielectric (Fig 13). Allowable Subject Matter Claims 6-7, 13-14 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 6. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a second metal protection film disposed between the metal via and the another dielectric, and the second metal protection film has a thermal conductivity smaller than 1 W/(m-K)”. Regarding claim 13. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a second metal protection film that surrounds the metal via and that separates the metal via from the first dielectric, wherein the second metal protection film has a thermal conductivity smaller than 1 W/(m-K)”. Regarding claim 16. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “between the step of forming the trench feature and the step of forming the first dielectric, a step of conformally forming a first metal protection film over the trench feature, wherein the first dielectric is formed over the first metal protection film; the method further comprising, after the step of forming the first dielectric, a step of performing thermal conversion on the first dielectric”. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Changhyun Yi/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Oct 24, 2023
Application Filed
Jan 20, 2026
Non-Final Rejection mailed — §102, §103
Apr 17, 2026
Response Filed
May 07, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.2%)
1y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1067 resolved cases by this examiner. Grant probability derived from career allowance rate.

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