DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending.
Claims 1-20 are original.
Claims 1-20 are rejected herein.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 17 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 13. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim 17 is also objected to because of the following informalities: in line 13, the claim recites “the power.” It appears that the foregoing should be “the power transistor.” For purposes herein, it will be examined as such. In any event, appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 6-10 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "the substrate contact layer" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the foregoing limitation shall be read as “a substrate contact layer.”
Claim 6 recites the limitation "the source terminal" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the foregoing limitation shall be read as “the source contact.”
Claims 7-10 depend from claim 6 and are accordingly rejected for at least the same reasons as claim 6.
Claim 8 recites the limitation "the transistor structure" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the foregoing limitation shall be read as “the power transistor.”
Claim 9 recites the limitation "the transistor structure" in line 2. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the foregoing limitation shall be read as “the power transistor.”
Claims 18-20 depend from claim 16 and the preambles of claims 18-20 recite an “integrated circuit package.” However, the preamble of claim 16 simply recites an “integrated circuit.” Moreover, claims 18-20 recite that the integrated circuit package is a “PSOP package,” a “TOLL package” and a “PQFN package,” respectively. However, claim 16 already requires the package to be a “PQFN package.” Accordingly, the dependence of claims 18-20 from claim 16 renders claims 18-20 unclear and/or indefinite. Rather, it appears that claims 18-20 should depend from claim 17, which likewise recites an “integrated circuit package” in its preamble, and for purposes herein, it shall be examined as if they depended from claim 17. In any event, appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 13 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hebert (US 20220254910 A1).
Regarding claim 1, Hebert discloses (see generally, e.g., FIG. 2):
An integrated circuit (FIG. 2) comprising:
a semiconductor substrate (10);
an epitaxial stack (12) epitaxially grown (paragraph [0016]) on the semiconductor substrate (10), the epitaxial stack (12) including a channel semiconductor layer (16) and a barrier semiconductor layer (18) epitaxially grown (paragraph [0016]) on the channel semiconductor layer (16); an interface between the channel semiconductor layer (16) and the barrier semiconductor layer (18) inducing a two-dimensional electron gas (2DEG) (paragraph [0016]) within the channel semiconductor layer (16);
a power transistor (54) using a portion of the epitaxial stack (12) including a portion of the channel semiconductor layer (16) and a portion of the barrier semiconductor layer (18); and
a biasing circuit (50, 52) comprising a plurality of circuit elements (50, 52), each of at least some of the plurality of circuit elements (50, 52) using a respective portion of the epitaxial stack (12) including a respective portion of the channel semiconductor layer (16) and a portion of the barrier semiconductor layer (18), the biasing circuit (50, 52) configured to bias (paragraph [0029]) a portion of the semiconductor substrate (10) beneath the power transistor (54).
Regarding claim 2, Hebert discloses:
The integrated circuit of claim 1, the semiconductor substrate (10) being a Silicon substrate (paragraph [0015]).
Regarding claim 3, Hebert discloses:
The integrated circuit of claim 1, the barrier semiconductor layer (18) being an AlGaN layer (paragraph [0016]), the channel semiconductor layer (16) being a GaN layer (paragraph [0016]).
Regarding claim 13, Hebert discloses:
The integrated circuit of claim 1, the integrated circuit being encompassed within a package (paragraph [0040]).
Regarding claim 17, Hebert discloses (see generally, e.g., FIG. 2):
An integrated circuit package (paragraph [0040]) comprising an integrated circuit (FIG. 2) that comprises:
a semiconductor substrate (10);
an epitaxial stack (12) epitaxially grown (paragraph [0016]) on the semiconductor substrate (10), the epitaxial stack (12) including a channel semiconductor layer (16) and a barrier semiconductor layer (18) epitaxially grown (paragraph [0016]) on the channel semiconductor layer (16); an interface between the channel semiconductor layer (16) and the barrier semiconductor layer (18) inducing a two-dimensional electron gas (2DEG) (paragraph [0016]) within the channel semiconductor layer (16);
a power transistor (54) using a portion of the epitaxial stack (12) including a portion of the channel semiconductor layer (16) and a portion of the barrier semiconductor layer (18); and
a biasing circuit (50, 52) comprising a plurality of circuit elements (50, 52), each of at least some of the plurality of circuit elements (50, 52) using a respective portion of the epitaxial stack (12) including a respective portion of the channel semiconductor layer (16) and a portion of the barrier semiconductor layer (18), the biasing circuit (50, 52) configured to bias (paragraph [0029]) a portion of the semiconductor substrate (10) beneath the power transistor (54).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hebert in view of Zhou (X. Zhou, J. Yang, Q. Zhang and Q. Zeng, "Implementation of Automotive Inverter Power Supply," 2016 International Conference on Industrial Informatics - Computing Technology, Intelligent Technology, Industrial Information Integration (ICIICII), Wuhan, China, 2016, pp. 154-157) and Morita (US 20120099357 A1).
Regarding claim 4, Hebert as applied to claim 1 discloses the integrated circuit of claim 1.
Hebert further disclose the biasing circuit (50, 52) comprising:
a transistor (50), a drain (34) of the transistor (50) being connected to a substrate contact layer (22) (see also, e.g., paragraph [0032]) and a gate (26) of the transistor (50) being coupled to an ac power supply (70 – see, e.g., FIG. 3).
Hebert does not explicitly disclose that the ac power supply (70) includes an inverter circuit.
However, in analogous art, Zhou disclose an ac power supply including an inverter circuit. See, e.g., FIG. 1.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the ac power supply of Zhou (i.e., including the inverter circuit) as the ac power supply (70) of Hebert according to known methods to yield predictable results, for example, so that the device is suitable for use in an automobile and/or automotive application. In this case, the gate (26) of the transistor (50) of Hebert is coupled to an inverter circuit (i.e., the inverter circuit disclosed by Zhou) as claimed.
While Hebert further discloses that the transistor (50) includes a source (36) (see also, e.g., paragraph [0032]), Hebert does not explicitly disclose the source of the transistor being connected to ground.
However, in analogous art, Morita discloses (see generally, e.g., FIG. 2) a transistor (10) having a drain (D) of the transistor (10) connected to a substrate contact layer (SUB – see also FIG. 1, element 20), a gate (G) of the transistor (10) couple to a gate drive circuit (137) and a source (S) of the transistor (10) connected to ground (paragraph [0042]).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have connected the source (36) of Hebert to ground as taught by Morita according to known methods to yield predictable results, for example, to achieve a desired potential difference between the source (36) and drain (34) of Herbert.
Claims 5-7 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hebert in view of Morita.
Regarding claim 5, Hebert as applied to claim 1 discloses the integrated circuit of claim 1.
Hebert further discloses:
a source contact (38) in conductive contact with the 2DEG (paragraph [0016]);
a drain contact (40) in conductive contact with the 2DEG (paragraph [0016]); and
a gate terminal (28, 30) that is proximate to the 2DEG (paragraph [0016]) such that voltages applied to the gate terminal (28, 30) control whether the 2DEG (paragraph [0016]) is continuous between the source contact (38) and the drain contact (40).
Hebert does not explicitly disclose a substrate contact layer disposed immediately beneath the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact; the biasing circuit configured to bias the portion of the semiconductor substrate beneath the power transistor by applying a substrate bias voltage to the substrate contact layer.
However, in analogous art, Morita discloses (see generally, e.g., FIG. 1) a substrate contact layer (20) disposed immediately beneath the semiconductor substrate (11), the substrate contact layer (20) being electrically disconnected from the source contact (16) to allow for a different voltage (see, e.g., paragraphs [0034] and [0036]) to be applied to the substrate contact layer (20) as compared to the source contact (16); the biasing circuit (22) configured to bias the portion of the semiconductor substrate (11) beneath the power transistor (10) by applying a substrate bias voltage (see, e.g., paragraph [0034]) to the substrate contact layer (20).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included, in the device of Hebert, a substrate contact layer disposed immediately beneath the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact, with the biasing circuit configured to bias the portion of the semiconductor substrate beneath the power transistor by applying a substrate bias voltage to the substrate contact layer, as taught by Morita according to known methods to yield predictable results, for example, to apply a uniform bias voltage across the semiconductor substrate independently of the voltage applied to the source contact.
Regarding claim 6, Hebert in view of Morita as applied to claim 5 discloses the integrated circuit of claim 5.
Morita further discloses the biasing circuit (22) being configured to bias the semiconductor substrate (11) by applying a positive bias voltage to the substrate contact layer (20), the positive bias voltage being positive relative to a source voltage applied to the source terminal (16). See, e.g., paragraph [0036].
Regarding claim 7, Hebert in view of Morita as applied to claim 6 discloses the integrated circuit of claim 6.
Morita further discloses the positive bias voltage being a fixed positive voltage relative to the source voltage. See, e.g., FIG. 1 and paragraph [0036].
Regarding claim 11, Hebert in view of Morita as applied to claim 5 discloses the integrated circuit of claim 5.
Morita further discloses the biasing circuit (22) further being configured to bias the substrate contact layer (20), the biasing circuit (22) being connected to the substrate contact layer (20) with a wire. See, e.g., FIG. 1 showing a line (i.e., wire) connecting the biasing circuit (22) to the substrate contact layer (20).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hebert in view of Morita as applied to claim 6 above, and further in view of Weiss (Weiss, Beatrix, et al.: "Substrate biasing effects in a high-voltage, monolithically-integrated half-bridge GaN-Chip", 2017 IEEE 5TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA), IEEE, 30 October 2017 (2017-10-30), pages 265-272, XP033265260, DOI: 10.1109/WIPDA.2017.8170558 [retrieved on 2017-12-07]).
Regarding claim 8, Hebert in view of Morita as applied to claim 6 discloses the integrated circuit of claim 6.
Hebert in view of Morita does not explicitly disclose the positive bias voltage being selectively applied depending on a state of the transistor structure.
However, in analogous art, Weiss discloses the positive bias voltage being selectively applied depending on a state of the transistor structure. See, e.g., FIGS. 14 and 15 showing the positive substrate biasing voltage V_SUB being selectively applied depending on a state of the transistor structure.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have selectively applied the positive bias voltage as taught by Weiss in the device of Hebert in view of Morita depending on a state of the transistor structure according to known methods to yield predictable results, for example, to suitably bias the substrate when desired (e.g., when the transistor structure is operative) and conserve power when biasing is not desired (e.g., when the transistor structure is not operative).
Regarding claim 9, Hebert in view of Morita as applied to claim 6 discloses the integrated circuit of claim 6.
Hebert in view of Morita does not explicitly disclose the positive bias voltage being selectively applied depending on a state of the transistor structure.
However, in analogous art, Weiss discloses the positive bias voltage changing depending on a state of the transistor structure. See, e.g., FIGS. 14 and 15 showing the substrate biasing voltage V_SUB changing depending on a state of the transistor structure.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have changed the positive bias voltage as taught by Weiss in the device of Hebert in view of Morita depending on a state of the transistor structure according to known methods to yield predictable results, for example, to suitably bias the substrate at a higher voltage when desired for a first state of the transistor structure and conserve power by biasing the substrate at a lower voltage when desired for a second state of the transistor structure.
Regarding claim 10, Hebert in view of Morita as applied to claim 6 discloses the integrated circuit of claim 6.
Hebert in view of Morita does not explicitly disclose the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 100 Volts to the semiconductor substrate.
However, in analogous art, Weiss discloses the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 100 Volts to the semiconductor substrate. See, e.g., FIGS. 14 and 15 showing the substrate biasing voltage V_SUB being more than 100 Volts.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made the biasing circuit configured such that the positive bias voltage has a maximum voltage of more than 100 Volts as taught by Weiss in the device of Hebert in view of Morita according to known methods to yield predictable results, for example, to suitably bias the substrate at a sufficiently high voltage which achieves a desired influence of the substrate bias.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Hebert in view of Morita as applied to claim 5 above, and further in view of Tsurumi (US 20110175142 A1).
Regarding claim 12, Hebert in view of Morita as applied to claim 5 discloses the integrated circuit of claim 5.
Morita further discloses the biasing circuit (22) further being configured to bias the substrate contact layer (20).
While Morita discloses the biasing circuit (22) being connected to the substrate contact layer (20) with a wire, Morita does not explicitly disclose the biasing circuit being connected to the substrate contact layer with a via through a die through the integrated circuit to the substrate contact layer.
However, in analogous art, Tsurumi (see generally, e.g., FIG. 1) discloses a biasing circuit (i.e., the pad 31 and the circuit applying the bias voltage to pad 31 – see, e.g., paragraphs [0037], [0039] and [0057]) being connected to the substrate contact layer (32) with a via (33A) through a die (FIG. 1) through the integrated circuit (FIG. 1) to the substrate contact layer (32).
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a via through a die (FIG. 1) through the integrated circuit as taught by Tsurumi to connect the biasing circuit (22) to the substrate contact layer (20) of Morita according to known methods to yield predictable results, for example, as a matter of simple substitution of one known type of electrical connection (i.e., a wire) with another known type of electrical connection (i.e., a via) that function the same to similarly provide an electrical path from a biasing circuit to a substrate contact layer. In particular, it is found that:
the prior art (i.e., Morita) contained a device which differed from the claimed device by the substitution of a wire for the via as claimed;
the substituted components (i.e., wire and via) and their functions (i.e., providing electrical connections) were known in the art (see, e.g., Morita and Tsurumi); and
one of ordinary skill in the art could have substituted one known element (e.g., a via) for another (e.g., a wire), and the results of the substitution would have been predictable.
See MPEP §2143(I)(B).
Claims 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Hebert as applied above to claims 13 and 17, respectively, in view of NPL1 (PSOP - Power Small Outline Package, EESemi.com, Comprehensive Reference on Semiconductor Manufacturing, Retrieved 12/27/2025 from https://www.eesemi.com/psop.htm, 2008).
Regarding claim 14, Hebert as applied to claim 13 discloses the integrated circuit of claim 13.
Hebert does not explicitly the package being a PSOP package.
However, in analogous art, NPL1 discloses a PSOP package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PSOP package as taught by NPL1 for the package of the device of Hebert according to known methods to yield predictable results, for example, thereby “increasing the chip’s ability to dissipate heat and thus handle more power.” NPL1, page 1, first paragraph.
Regarding claim 18, Hebert as applied to claim 17 discloses the integrated circuit package of claim 17.
Hebert does not explicitly the package being a PSOP package.
However, in analogous art, NPL1 discloses a PSOP package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PSOP package as taught by NPL1 for the package of the device of Hebert according to known methods to yield predictable results, for example, thereby “increasing the chip’s ability to dissipate heat and thus handle more power.” NPL1, page 1, first paragraph.
Claims 15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hebert as applied above to claims 13 and 17, respectively, in view of NPL2 (TOLL package Application Note, Toshiba Electronic Devices & Storage Corporation, 07/30/2021).
Regarding claim 15, Hebert as applied to claim 13 discloses the integrated circuit of claim 13.
Hebert does not explicitly the package being a TOLL package.
However, in analogous art, NPL2 discloses a TOLL package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a TOLL package as taught by NPL2 for the package of the device of Hebert according to known methods to yield predictable results, for example, to achieve a surface mounted package with high-efficiency. See, e.g., NPL2, page 3, 1. Introduction to TOLL package.
Regarding claim 19, Hebert as applied to claim 17 discloses the integrated circuit package of claim 17.
Hebert does not explicitly the package being a TOLL package.
However, in analogous art, NPL2 discloses a TOLL package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a TOLL package as taught by NPL2 for the package of the device of Hebert according to known methods to yield predictable results, for example, to achieve a surface mounted package with high-efficiency. See, e.g., NPL2, page 3, 1. Introduction to TOLL package.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Hebert as applied above to claims 13 and 17, respectively, in view of NPL3 (PQFN - Data Sheet, Amkor Technology, December 2019).
Regarding claim 16, Hebert as applied to claim 13 discloses the integrated circuit of claim 13.
Hebert does not explicitly the package being a PQFN package.
However, in analogous art, NPL3 discloses a PQFN package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PQFN package as taught by NPL3 for the package of the device of Hebert according to known methods to yield predictable results, for example, to have “a highly efficient space-saving package” which features “very-low parasitics and inductances” and/or “[o]utstanding EMI behavior” and/or “excellent thermal performance” and/or uses “[g]reen materials.” See, e.g., NPL3, page 1, first paragraph.
Regarding claim 20, Hebert as applied to claim 17 discloses the integrated circuit package of claim 17.
Hebert does not explicitly the package being a PQFN package.
However, in analogous art, NPL3 discloses a PQFN package.
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a PQFN package as taught by NPL3 for the package of the device of Hebert according to known methods to yield predictable results, for example, to have “a highly efficient space-saving package” which features “very-low parasitics and inductances” and/or “[o]utstanding EMI behavior” and/or “excellent thermal performance” and/or uses “[g]reen materials.” See, e.g., NPL3, page 1, first paragraph.
Conclusion
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812