Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-11 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites “…internal circuit unit is configured to provide a signal that is different from that of the first internal circuit unit…”. The claim does not specify what attribute makes the signal “different” (e.g., different types such as scan vs. emission vs. data, different voltage level, timing, waveform, etc. As written, “different” is a relative term without objective boundaries and leaves scope uncertain. For the purpose of examination, this limitation is interpreted as “different type such as scan vs. emission”.
Claim 15 introduces same indefiniteness issue as Claim 4 described above.
Claim 5 recites “…second internal circuits configured to provide a signal different from that of the first internal circuits”. The claim does not specify what attribute makes the signal “different” (e.g., different types such as scan vs. emission vs. data, different voltage level, timing, waveform, etc. As written, “different” is a relative term without objective boundaries and leaves scope uncertain. For the purpose of examination, this limitation is interpreted as “different type such as scan vs. emission”.
Claims 6-11 and claims 16-20 inherit the indefiniteness of claims 4 and claim 15 respectively which they depend on. Thus, claims 6-11 and 16-20 are also rejected under 35 U.S.C. 112(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Adachi (US 20060007075 A1).
Re: Independent Claim 1, Jeon discloses a display panel comprising:
a substrate comprising a display area and a peripheral area surrounding the display area (Jeon teaches, in Fig. 3 and ¶ [0044], substrate 10 that includes display area DA and non-display area NA surrounding the display area DA);
first signal lines on the substrate and extending in a first direction (Jeon teaches, in Fig. 3 and ¶ [0045], the display area DA includes gate lines G1 to Gm; Jeon states the gate lines G1 to Gm extend along a first direction DR1. Gate lines G1 to Gm correspond to the claimed first signal lines extending in the first direction);
data lines on the substrate and extending in a second direction crossing the first direction (Jeon teaches, in Fig. 3 and ¶ [0045], data lines D1 to Dn along second direction DR2 crossing the first direction DR1);
pixel circuits arranged in a matrix along the first direction and the second direction and display elements respectively connected to the pixel circuits, the pixel circuits and the display elements being in the display area (Jeon teaches, in Fig. 3 and ¶ [0045], the display area DA includes a plurality of pixels PX arranged at areas in a matrix form defined by the gate lines G1-Gm and the data lines D1-Dn, thus teaching pixel circuits arranged in a matrix along DR1 and DR2 in the display area. Jeon further teaches, in Fig. 4 and ¶¶ [0068] - [0069], that each pixel PX includes a thin film transistor TR (pixel circuits) and a pixel electrode PE (display elements), where the thin film transistor TR provides a data voltage and the pixel electrode PE is coupled/connected to TR);
a first internal circuit unit comprising first internal circuits arranged along the first direction in the peripheral area (Jeon teaches, in Fig. 3 and ¶¶ [0057] - [0060] gate driver 400 (first internal circuit unit) disposed in the non-display area NA, the gate 400 comprises first gate driver 410/second gate driver 420 (first internal circuits) arranged along first direction DR1); and
connection lines arranged in the peripheral area to connect each of the first internal circuits to each of the first signal lines (Jeon teaches, in Fig. 3 and ¶ [0059], connection lines L1 to L2m including main connection lines L1 to Lm and sub-connection lines Lm+1 to L2m are coupling the gate driver 400 to the gate lines G1-Gm; thus L1 to L2m are in the non-display area that connect internal circuits (gate driver 400) to the first signal lines (gate lines G1-Gm)).
Jeon further teaches
Wherein the first internal circuit unit comprises a 1-1st internal circuit unit and a 1-2nd internal circuit unit (Jeon, in Fig. 3 and ¶ [0060], teaches that gate driver 400 includes multiple internal driver circuits, such as first gate driver and second gate driver spaced from each other, evidencing that the first internal circuit unit can include multiple internal circuit portions, i.e., 410 (1-1st internal circuit unit) and 420 (1-2nd internal circuit unit)).
Although Jeon teaches gate driver 400 is configured to sequentially apply gate signals to gate lines G1-Gm to thereby drive pixel rows, Jeon is silent regarding driving different row-groups in opposite scan directions as claimed: wherein the first internal circuit unit comprises a 1-1st internal circuit unit in which the first internal circuits configured to provide signals to the pixel circuits arranged in the first to ith rows are arranged in a reverse direction to the first direction, and a 1-2nd internal circuit unit in which the first internal circuits configured to provide signals to the pixel circuits arranged in the i+1st to nth rows are arranged in the first direction, and i and n are natural numbers.
However, Adachi teaches wherein the first internal circuit unit comprises a 1-1st internal circuit unit in which the first internal circuits configured to provide signals to the pixel circuits arranged in the first to ith rows are arranged in a reverse direction to the first direction, and a 1-2nd internal circuit unit in which the first internal circuits configured to provide signals to the pixel circuits arranged in the i+1st to nth rows are arranged in the first direction, and i and n are natural numbers (Adachi, Fig. 10A-10C and ¶ [0073], teaches dividing the display area into an “upper half” and “lower half” and implementing scanning such that scan-selection directions are different - e.g., scanning the first through (n/2)th scan lines sequentially in one direction while scanning the (n/2+1)th through nth scan lines sequentially in the opposite direction (upper-half vs lower-half). Accordingly, this corresponds to providing row-driving signals to rows 1…i in a reverse order/direction and to rows i+1…n in a forward order/direction via respective internal-circuit portions (1-1st and 1-2nd internal circuit units) of the scan/gate driving circuitry. Adachi uses n scan lines and divides them into first through (n/2)th and (n/2+1)th through nth scan lines; thus i (e.g., n/2) and n are natural-number indicates of row/scan lines).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon’s gate-driver operation to implement dual-direction scanning technique of Adachi because Adachi teaches that using opposite scan directions for different halves/rows groups avoids simultaneous selection of adjacent boundary scan lines and thereby avoids a momentary bright line at the boundary and improves display quality – an expected result achieved by applying a known scan-driving technique to Jeon’s conventional gate-line/pixel-matrix architecture.
Re: Claim 2, Jeon and Adachi disclose all the limitations of claim 1 on which this claim depends.
Jeon further discloses,
wherein the connection lines comprise first connection lines between the first internal circuit unit and the display area (Jeon, Fig. 3, connection lines L1 to L2m comprise main connection lines L1 to Lm, and the main connection lines L1 to Lm are coupled to gate lines G1-Gm, since the gate lines G1-Gm are in the display area DA, the main connection lines L1-Lm correspond to the claimed first connection lines between the first internal circuit unit (gate driver400/first date driver 410) and the display area DA), and
second connection lines between the first internal circuit unit and an edge of the substrate (Jeon, Fig. 3, second connection lines Lm+1 to L2m extend along the second direction DR2 from the second gate driver 420, pass through the display DA, and are bent at the first non-display area NA1 outside of an m-th gate line Gm (e.g., the first non-display area NA1 opposite to the first non-display area NA1 at which the gate driver 400 is located) after passing through the display area DA, and then are coupled to (e.g., connected to) the gate lines G1 to Gm; thus the sub-connection lines Lm+1 to L2 (second connection lines) include routing that reaches the opposite peripheral/non-display region NA1 at the outer side/edge of the substrate before bending back toward the gate lines, corresponding to the claimed second connection lines between the first internal circuit unit and an edge of the substrate).
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Adachi (US 20060007075 A1) further in view of Lee (US 20180158895 A1).
Re: Claim 3, Jeon and Adachi disclose all the limitations of claim 1 on which this claim depends.
Jeon and Adachi are silent regarding
further comprising a common voltage power source line in the peripheral area and surrounding at least a portion of the display area, wherein at least some of the connection lines overlap the common voltage power source line.
However, Lee teaches a common voltage power source line in the peripheral area and surrounding at least a portion of the display area (Lee teaches, in Figs. 2-3 and ¶¶ [0056] – [0057], power line PL includes a second power line PL2 which applies a second power source ELVSS; and second power line PL2 may extend in the peripheral area PPA along the border of the pixel area PXA. This corresponds to the claimed common voltage power source line (e.g., PL2 supplying ELVSS as a common pixel voltage) in the peripheral area and surrounding at least a portion of the display area),
wherein at least some of the connection lines overlap the common voltage power source line (Lee teaches, in Fig. 3 and ¶ [0123], that connection line CL extend from the pixel area into the peripheral area and partially overlap the second power line PL2 in the second area SA).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee’s peripheral-area power line (e.g., second power line P2 supplying ELVSS) arranged along the border of the display area and Lee’s overlap routing relationship (connection line CL overlapping a part/area of the power line) into Jeon’s display panel wiring arrangement, because Lee expressly teaches that the structure reduces resistance and enables stable supply of power source (e.g., ELVSS) without delay (Lee, ¶ [0118]).
Claims 4-6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Adachi (US 20060007075 A1) further in view of Yu (US 20220123087 A1).
Re: Claim 4, Jeon and Adachi disclose all the limitations of claim 1 on which this claim depends.
Jeon further teaches
wherein the peripheral area comprises a first peripheral area outside a first side of the display area (non-display area NA includes a “first non-display area NA1” outer areas above/below the display area DA), a second peripheral area outside a second side of the display area (“second non-display area NA2” outer areas left/right of the display area DA), and a corner peripheral area outside a corner at which the first side and the second side meet (first and second peripheral regions NA1 and NA2 outside different sides of the display area, with a corner peripheral region inherently at the intersection of NA1 and NA2).
Jeon and Adachi are silent regarding
a corner internal circuit unit in the corner peripheral area, wherein the corner internal circuit unit is configured to provide a signal that is different from that of the first internal circuit unit to the pixel circuits.
However, Yu teaches a corner internal circuit unit in the corner peripheral area (Yu, in Figs. 2A-2B ¶¶ [0070] – [0071], teaches a gate driving circuit 21 located at least in the corner area 112B and also teaches a light emission control driving circuit 22 located at least in the corner area 112B), wherein the corner internal circuit unit is configured to provide a signal that is different from that of the first internal circuit unit to the pixel circuits (Yu, in Figs. 2A-2B and ¶ [0071], teaches the light emission control driving circuit 22 provides emission control signals to emission control lines 15, and the emission control lines 15 are electrically connected to the sub-pixels (pixel circuits) in the display area. Thus, the corner internal circuit unit (e.g., light emission control driving circuit 22 located at least in corner area 112B) provides an emission control signal that is different from Jeon’s gate driving signal to the pixel circuits/sub-pixels).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon’s display panel (as further modified by Adachi) to additionally include Yu’s corner area internal circuit placement (corner area 112B) and to provide a different control signal (e.g., emission control) from a corner internal circuit unit, because Yu teaches placing driving circuitry in the corner peripheral region and routing control signals (e.g., emission control signals) to the pixel circuits/sub-pixels, which is a predictable layout implementation for utilizing corner peripheral area and supporting display driving.
Re: Claim 5, Jeon, Adachi and Yu disclose all the limitations of claim 4 on which this claim depends.
Yu further teaches
wherein the corner internal circuit unit comprises second internal circuits configured to provide a signal different from that of the first internal circuits (As explained above in claim 1 above, in Jeon, the first internal circuits correspond to the circuitry of the date driver 400, which includes a first driver 410 and a second gate driver 420 and generates a gate signal that is applied to the gate lines. Yu (Figs. 2A-2B and ¶ [0071]) teaches, in the corner area 112B, a light emission control driving circuit 22 that includes a plurality of light emission control driving units 221 (i.e., second internal circuits) and the emitting control driving unit 211 is electrically connected to another light emitting control line 15 are configured to provide a light emitting control signal, which are different from the gate signals provided on gate lines of Jeon).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yu’s corner-area additional driving circuitry (light emission control driving circuit 22/units 221) into Jeon’s display panel so that the corner region can supply an additional, different class of control signal (emission control) while maintaining a compact peripheral region layout approach consistent with Jeon’s stated objective of driver placement in non-display areas.
Re: Claim 6, Jeon, Adachi and Yu disclose all the limitations of claim 5 on which this claim depends.
Yu further teaches
wherein the first internal circuits are emission control driving circuits (Yu teaches a light emission control driving circuit 22 that includes a plurality of light emission control driving units 221 and is electrically connected to light-emitting control lines 15, where the light-emitting control lines 15 are configured to provide emission control signals to the sub-pixels/pixel circuits), and
the second internal circuits are scan driving circuits (Yu teaches a gate driving circuit 21 that includes a plurality of gate driving units 211, and is electrically connected to gate lines 14, where the gate lines 14 are configured to provide gate signals (scan signals) to the sub-pixels/pixel circuits).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yu’s teaching of providing both (i) an emission control driving circuit and (ii) a gate/scan driving circuit (each implemented as plural driving units/shift-register type circuitry) into Jeon’s display panel driver arrangement, because both references address on-panel/peripheral driving-circuit placement and routing of different control signals to pixel circuits, and Yu expressly shows emission-control and gate/scan driving circuit as predictable, compactible driver blocks for supplying different signals to the pixel circuits.
Re: Claim 8, Jeon, Adachi and Yu disclose all the limitations of claim 5 on which this claim depends.
Yu further teaches
wherein some of the connection lines are between the second internal circuits (Yu teaches, in Figs. 2A-2B and ¶ [0071], a light emission control driving circuit 22 located at least in the corner area 112B and including a plurality of light emission control driving units 221, such as a plurality of second shift registers connected in cascade. Accordingly, if the second internal circuits are “connected in cascade”, then there necessarily exist signal connections (i.e., lines/conductors) between adjacent ones of the second internal circuits to pass signals stage-to-stage, which reads on “some of the connection lines are between the second internal circuits”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yu’s cascade connected implementation for the second internal circuit into the display panel of Jeon (as modified by Adachi) because Yu teaches implementing the corner-area driving circuits as plural shift units connected in cascade to supply row-related control signals, which is a predictable and commonly used interconnection arrangement for multi-stage driver circuits in a peripheral/corner region.
Re: Claim 9, Jeon, Adachi and Yu disclose all the limitations of claim 4 on which this claim depends.
Yu further teaches
wherein a scan driving circuit and an emission control driving circuit are arranged in a pair in the second peripheral area (Yu teaches, in ¶ [0070], a peripheral area including “other peripheral areas, such as a second peripheral area 112C…” and a gate driving circuit 21 (i.e., a scan driving circuit) is also located in the second peripheral area 112C. Yu further teaches, in ¶ [0071], a light emission control driving circuit 22 (i.e., an emission control driving circuit) that may also be located in the second peripheral area 112C. As taught in Fig. 2B of Yu, these two circuits 21 and 22 are placed together in the same peripheral region as a pair).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon’s display panel (as already modified by Adachi) to further include an emission control driving circuit arranged together with the scan driving circuit in the second peripheral area, as taught by Yu, to provide emission control signals in addition to scan signals while keeping the driver circuitry in peripheral regions and away from the display area (Yu, ¶ [0004]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Adachi (US 20060007075 A1) further in view of Yu (US 20220123087 A1) and further in view of Qin (US 20220231055 A1).
Re: Claim 7, Jeon, Adachi and Yu disclose all the limitations of claim 5 on which this claim depends.
Jeon, Adachi and Yu are silent regarding
wherein the second internal circuits are arranged radially according to a shape of the corner peripheral area.
However, Qin teaches
wherein the second internal circuits are arranged radially according to a shape of the corner peripheral area (Qin teaches, in Figs. 1-2 and ¶ [0026], a non-display region surrounding a display region, including a first sub-region NA1 extending in a first direction X, a second sub-region NA2 extending in a second direction Y, and a third sub-region NA3 connecting the first and second sub-regions, where the third sub-region extends in an arc shape. Qin further teaches, in Figs. 1-2 and ¶ [0037], that circuit modules positioned in the non-display region such that part of the circuit modules are arranged along the first direction, and another part of the circuit modules are arranged in an array in the arc-shaped third sub-region along the arc-shaped extending direction. Thus, Qin teaches arranging peripheral driver/circuit modules along an arc/corner region to conform to the corner geometry, which corresponds to the claimed concept of radially arranging circuits according to the corner peripheral shape).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange Yu’s second internal circuits in the corner peripheral area using the arch-shaped /rotated-angle (radial) layout taught by Qin because Qin expressly teaches that arranging circuits/modules along the arc-shaped corner region makes the layout more compact and reduces the bezel width in the radial direction, which is a predictable design goal in display panel peripheral/corner layouts (Qin, ¶ [0037]).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Adachi (US 20060007075 A1) further in view of Yu (US 20220123087 A1) and further in view of Park (US 20130033471 A1).
Re: Claim 10, Jeon, Adachi and Yu disclose all the limitations of claim 4 on which this claim depends.
Yu further teaches
wherein a second internal circuit unit is in the second peripheral area (Yu teaches that the gate driving circuit may also be located in the second peripheral region 112C, and likewise the light emission control driving circuit may also be located in the second peripheral area 112C. Thus, Yu teaches second internal circuit units is in the peripheral area).
Jeon, Adachi and Yu are silent regarding
a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit.
However, Park teaches exactly this type of connection
a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit (Park teaches, in Fig. 5 and ¶ [0074], a connection line CL1 disposed on the substrate that electrically connects the first gate driver 132 to the second gate driver 134, and further explains CL1 is connected between terminals of the first and second gate drivers to transmit the applied driving voltage. Accordingly, in the combined system (Jeon/Adachi/Yu), the first internal circuit and the added second internal circuit unit (now placed in the second peripheral area per Yu) would be connected by incorporating Park’s CL1-type inter-driver wiring, which reads on “a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Jeon/Adachi/Yu display panel to include Park’s inter-driver connection line CL1 because Park teaches such connection lines are used to distribute/transfer the driving voltage between multiple gate drivers so that driving voltages applied to multiple gate driving chips/drivers can be provided at same level and managed via controlled resistance paths- i.e., a predictable wiring modification to ensure consistent driving conditions when multiple internal circuit units are used in different peripheral regions (Park, ¶ [0088]).
Re: Claim 11, Jeon, Adachi, Yu and Park disclose all the limitations of claim 10 on which this claim depends.
Jeon in view of Yu and Park further teach
wherein a portion of the third connection line is between the first internal circuit unit and the display area (Jeon teaches, in Abstract, a thin film transistor substrate that includes a display area and a non-display area surrounding the display area, and teaches the gate driver is at a first non-display area outside the display area, with a connection that extends and couples the gate driver and the gate lines in the display area. Park teaches the connection line CL1 is disposed on the substrate and electrically connects the first gate driver to the second gate driver. Accordingly, when Park’s CL1 (as the third connection line of claim 10) is incorporated into Jeon’s display panel layout in which internal circuit units (gate drivers) are disposed outside the display area, a portion of CL1 is necessarily located in the non-display/peripheral region adjacent to the display area (i.e., between the first internal circuit unit and the display area) as a predictable result of routing an inter-driver connection line on the substrate in the peripheral region surrounding the display area), and
another portion is between the corner internal circuit unit and an edge of the substrate (Yu teaches, in Figs. 2A-2B and ¶¶ [0070] – [0071], peripheral area including a corner area 112B, and teaches a light emission control driving circuit 22 is located at least in the corner area 112B and is located on the side away from the display area 111 (i.e., toward the outer boundary/edge side of the substrate), and further teaches the circuit may also be in another peripheral region (e.g., second peripheral region 112C). Given Yu’s placement of the corner internal circuit unit, it would have been obvious to route Park’s inter-unit connection line (CL1, used as the “third connection line” of claim 10) through the peripheral/corner routing space such that another portion of the third connection line lies between the corner internal circuit unit and an edge of the substrate, because the “away from the display area” side is the predictable location where peripheral routing toward the substrate edge is provided/available.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon/Adachi/Yu to include Park’s inter-driver connection line and route it in the peripheral/corner region because Park expressly teaches inter-driver connection lines on the substrate to distribute driving voltage between drivers, while Yu teaches corner-area peripheral circuit placement away for the display area - together making it a predictable design choice to route portions of the inter-unit connection line through the peripheral area adjacent the display area and toward the substrate edge to implement the multi-driver architecture with manageable peripheral wiring.
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Lee (US 20180158895 A1).
Re: Independent Claim 12, Jeon discloses a display panel comprising:
a substrate comprising a display area and a peripheral area surrounding the display area (Jeon teaches, in Fig. 3 and ¶ [0044], substrate 10 that includes display area DA and non-display area NA surrounding the display area DA);
first signal lines on the substrate and extending in a first direction (Jeon teaches, in Fig. 3 and ¶ [0045], the display area DA includes gate lines G1 to Gm; Jeon states the gate lines G1 to Gm extend along a first direction DR1. Gate lines G1 to Gm correspond to the claimed first signal lines extending in the first direction);
data lines on the substrate and extending in a second direction crossing the first direction (Jeon teaches, in Fig. 3 and ¶ [0045], data lines D1 to Dn along second direction DR2 crossing the first direction DR1);
pixel circuits arranged in a matrix along the first direction and the second direction and display elements respectively connected to the pixel circuits, the pixel circuits and the display elements being arranged in the display area (Jeon teaches, in Fig. 3 and ¶ [0045], the display area DA includes a plurality of pixels PX arranged at areas in a matrix form defined by the gate lines G1-Gm and the data lines D1-Dn, thus teaching pixel circuits arranged in a matrix along DR1 and DR2 in the display area. Jeon further teaches, in Fig. 4 and ¶¶ [0068] - [0069], that each pixel PX includes a thin film transistor TR (pixel circuits) and a pixel electrode PE (display elements), where the thin film transistor TR provides a data voltage and the pixel electrode PE is coupled/connected to TR);
a first internal circuit unit comprising first internal circuits arranged along the first direction in the peripheral area (Jeon teaches, in Fig. 3 and ¶¶ [0057] - [0060] gate driver 400 (first internal circuit unit) disposed in the non-display area NA, the gate 400 comprises first gate driver 410/second gate driver 420 (first internal circuits) arranged along first direction DR1); and
connection lines in the peripheral area to connect each of the first internal circuits to each of the first signal lines (Jeon teaches, in Fig. 3 and ¶ [0059], connection lines L1 to L2m including main connection lines L1 to Lm and sub-connection lines Lm+1 to L2m are coupling the gate driver 400 to the gate lines G1-Gm; thus L1 to L2m are in the non-display area that connect internal circuits (gate driver 400) to the first signal lines (gate lines G1-Gm)).
Jeon is silent regarding
a common voltage supply line in the peripheral area between the first internal circuit unit and an edge of the substrate, wherein at least some of the connection lines overlap the common voltage supply line.
However, Lee teaches
a common voltage supply line in the peripheral area between the first internal circuit unit and an edge of the substrate (Lee teaches, in Figs. 2-3 and ¶¶ [0056] – [0057], power line PL in a peripheral area PPA that provides a driving voltage to pixels, and specifically teaches a second power line PL2 that is located at an outer peripheral side/external side of the driver circuitry (Lee describes PL2 being at the external side of an emission driver EDV in the peripheral area PPA) and that applies a common power source ELVSS. Since Jeon already teaches that the gate driver 400 (first internal circuit unit) is disposed in the first non-display area NA1 and is located between the display area DA and the flexible printed circuit board 200 (edge side hardware) i.e., Jeon provides a clear driver – outer edge layout direction in the peripheral area. Therefore, it would have been obvious to arrange Lee’s common voltage supply line (e.g., PL2 supplying ELVSS) in Jeon’s peripheral area on the outer peripheral/edge side of the first internal circuit unit (gate driver 400) i.e., between the first internal circuit unit and the substrate edge- because Lee expressly places the common supply line on the outer peripheral side relative to driver circuitry and uses it as a common supply distribution line),
wherein at least some of the connection lines overlap the common voltage supply line (Lee teaches, in Fig. 3 and ¶ [0123], that connection lines CL extend from the pixel area into the peripheral area and partially overlap the second power line PL2 in the second area SA).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lee’s peripheral-area power line (e.g., second power line P2 supplying ELVSS) arranged along the border of the display area and Lee’s overlap routing relationship (connection line CL overlapping a part/area of the power line) into Jeon’s display panel wiring arrangement, because Lee expressly teaches that the structure reduces resistance and enables stable supply of power source (e.g., ELVSS) without delay (Lee, ¶ [0118]).
Re: Claim 13, Jeon and Lee disclose all the limitations of claim 12 on which this claim depends.
Jeon further teaches
wherein the connection lines comprise first connection lines and second connection lines (Jeon, Fig. 3, connection lines L1 to L2m comprise main connection lines L1 to Lm (first connection lines) and second connection lines Lm+1 to L2m), the first connection lines and the second connection lines extending from the first internal circuit unit in different directions from each other (the main connection lines L1 to Lm are coupled to gate lines G1-Gm via a shortest distance between the first gate driver 410 and the gate lines along the second direction DR2 (i.e., they extend directly outward from the gate driver toward the gate lines. Jeon also teaches that the second connection lines Lm+1 to L2m extend along the second direction DR2 from the second gate driver 420, pass through the display DA, and are bent at the first non-display area NA1 outside of an m-th gate line Gm (i.e., at the opposite first non-display area), before being coupled to the gate lines. This describes a routing in which the second connection lines leave the gate-driver block in a different direction/path (across the display area and to the opposite non-display area, with a bend) than the first connection lines that take the shortest path).
Re: Claim 14, Jeon and Lee disclose all the limitations of claim 13 on which this claim depends.
Jeon further teaches
wherein the first connection lines are between the first internal circuit unit and the display area (Jeon, Fig. 3, main connection lines L1 to Lm (first connection lines) are coupled to gate lines G1-Gm, and since the gate lines G1-Gm are in the display area DA, the main connection lines L1-Lm are between the first internal circuit unit (gate driver400/first date driver 410) and the display area DA), and second connection lines are between the first internal circuit unit and the edge of the substrate (Jeon, Fig. 3, second connection lines Lm+1 to L2m extend along the second direction DR2 from the second gate driver 420, pass through the display DA, and are bent at the first non-display area NA1 outside of an m-th gate line Gm (e.g., the first non-display area NA1 opposite to the first non-display area NA1 at which the gate driver 400 is located) after passing through the display area DA, and then are coupled to (e.g., connected to) the gate lines G1 to Gm; thus the sub-connection lines Lm+1 to L2 (second connection lines) include routing that reaches the opposite peripheral/non-display region NA1 at the outer side/edge of the substrate before bending back toward the gate lines, corresponding to the claimed second connection lines between the first internal circuit unit and an edge of the substrate).
Claims 15-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Lee (US 20180158895 A1) further in view of Yu (US 20220123087 A1).
Re: Claim 15, Jeon and Lee disclose all the limitations of claim 12 on which this claim depends.
Jeon further teaches
wherein the peripheral area comprises a first peripheral area outside a first side of the display area (non-display area NA includes a “first non-display area NA1” outer areas above/below the display area DA), a second peripheral area outside a second side of the display area (“second non-display area NA2” outer areas left/right of the display area DA), and a corner peripheral area outside a corner at which the first side and the second side meet (first and second peripheral regions NA1 and NA2 outside different sides of the display area, with a corner peripheral region inherently at the intersection of NA1 and NA2).
Jeon and Lee are silent regarding
a corner internal circuit unit in the corner peripheral area, wherein the corner internal circuit unit is configured to provide a signal different from that of the first internal circuit unit to the pixel circuits.
However, Yu teaches a corner internal circuit unit in the corner peripheral area (Yu, in Figs. 2A-2B ¶¶ [0070] – [0071], teaches a gate driving circuit 21 located at least in the corner area 112B and also teaches a light emission control driving circuit 22 located at least in the corner area 112B), wherein the corner internal circuit unit is configured to provide a signal different from that of the first internal circuit unit to the pixel circuits (Yu, in Figs. 2A-2B and ¶ [0071], teaches the light emission control driving circuit 22 provides emission control signals to emission control lines 15, and the emission control lines 15 are electrically connected to the sub-pixels (pixel circuits) in the display area. Thus, the corner internal circuit unit (e.g., light emission control driving circuit 22 located at least in corner area 112B) provides an emission control signal that is different from Jeon’s gate driving signal to the pixel circuits/sub-pixels).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jeon’s display panel (as further modified by Lee) to additionally include Yu’s corner area internal circuit placement (corner area 112B) and to provide a different control signal (e.g., emission control) from a corner internal circuit unit, because Yu teaches placing driving circuitry in the corner peripheral region and routing control signals (e.g., emission control signals) to the pixel circuits/sub-pixels, which is a predictable layout implementation for utilizing corner peripheral area and supporting display driving.
Re: Claim 16, Jeon, Lee and Yu disclose all the limitations of claim 15 on which this claim depends.
Jeon further teaches
wherein the corner internal circuit unit comprises second internal circuits (As explained above in claim 15 above, in Jeon, the first internal circuits correspond to the circuitry of the date driver 400, which includes a second gate driver 420 (second internal circuits)).
Re: Claim 17, Jeon, Lee and Yu disclose all the limitations of claim 16 on which this claim depends.
Yu further teaches
wherein the first internal circuits are emission control driving circuits (Yu teaches, in Figs. 2A-2B ¶¶ [0070] – [0071], a light emission control driving circuit 22 that includes a plurality of light emission control driving units 221 and is electrically connected to light-emitting control lines 15, where the light-emitting control lines 15 are configured to provide emission control signals to the sub-pixels/pixel circuits), and
the second internal circuits are scan driving circuits (Yu teaches, in Figs. 2A-2B ¶¶ [0070] – [0071] a gate driving circuit 21 that includes a plurality of gate driving units 211, and is electrically connected to gate lines 14, where the gate lines 14 are configured to provide gate signals (scan signals) to the sub-pixels/pixel circuits).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yu’s teaching of providing both (i) an emission control driving circuit and (ii) a gate/scan driving circuit (each implemented as plural driving units/shift-register type circuitry) into Jeon’s display panel driver arrangement, because both references address on-panel/peripheral driving-circuit placement and routing of different control signals to pixel circuits, and Yu expressly shows emission-control and gate/scan driving circuit as predictable, compactible driver blocks for supplying different signals to the pixel circuits.
Re: Claim 19, Jeon, Lee and Yu disclose all the limitations of claim 16 on which this claim depends.
Yu further teaches
wherein some of the connection lines are between the second internal circuits (Yu teaches, in Figs. 2A-2B and ¶ [0071], a light emission control driving circuit 22 located at least in the corner area 112B and including a plurality of light emission control driving units 221, such as a plurality of second shift registers connected in cascade. Accordingly, if the second internal circuits are “connected in cascade”, then there necessarily exist signal connections (i.e., lines/conductors) between adjacent ones of the second internal circuits to pass signals stage-to-stage, which reads on “some of the connection lines are between the second internal circuits”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Yu’s cascade connected implementation for the second internal circuit into the display panel of Jeon (as modified by Lee) because Yu teaches implementing the corner-area driving circuits as plural shift units connected in cascade to supply row-related control signals, which is a predictable and commonly used interconnection arrangement for multi-stage driver circuits in a peripheral/corner region.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Lee (US 20180158895 A1) further in view of Yu (US 20220123087 A1) and further in view of Qin (US 20220231055 A1).
Re: Claim 18, Jeon, Lee and Yu disclose all the limitations of claim 16 on which this claim depends.
Jeon, Lee and Yu are silent regarding
wherein the second internal circuits are arranged radially according to a shape of the corner peripheral area.
However, Qin teaches
wherein the second internal circuits are arranged radially according to a shape of the corner peripheral area (Qin teaches, in Figs. 1-2 and ¶ [0026], a non-display region surrounding a display region, including a first sub-region NA1 extending in a first direction X, a second sub-region NA2 extending in a second direction Y, and a third sub-region NA3 connecting the first and second sub-regions, where the third sub-region extends in an arc shape. Qin further teaches, in Figs. 1-2 and ¶ [0037], that circuit modules positioned in the non-display region such that part of the circuit modules are arranged along the first direction, and another part of the circuit modules are arranged in an array in the arc-shaped third sub-region along the arc-shaped extending direction. Thus, Qin teaches arranging peripheral driver/circuit modules along an arc/corner region to conform to the corner geometry, which corresponds to the claimed concept of radially arranging circuits according to the corner peripheral shape).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange Yu’s second internal circuits in the corner peripheral area using the arch-shaped /rotated-angle (radial) layout taught by Qin because Qin expressly teaches that arranging circuits/modules along the arc-shaped corner region makes the layout more compact and reduces the bezel width in the radial direction, which is a predictable design goal in display panel peripheral/corner layouts (Qin, ¶ [0037]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon (US 20150115292 A1) in view of Lee (US 20180158895 A1) further in view of Yu (US 20220123087 A1) and further in view of Park (US 20130033471 A1).
Re: Claim 20, Jeon, Lee and Yu disclose all the limitations of claim 15 on which this claim depends.
Yu further teaches
wherein a second internal circuit unit is in the second peripheral area (Yu teaches that the gate driving circuit may also be located in the second peripheral region 112C, and likewise the light emission control driving circuit may also be located in the second peripheral area 112C. Thus, Yu teaches second internal circuit units is in the peripheral area).
Jeon, Lee and Yu are silent regarding
a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit.
However, Park teaches exactly this type of connection
a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit (Park teaches, in Fig. 5 and ¶ [0074], a connection line CL1 disposed on the substrate that electrically connects the first gate driver 132 to the second gate driver 134, and further explains CL1 is connected between terminals of the first and second gate drivers to transmit the applied driving voltage. Accordingly, in the combined system (Jeon/Lee/Yu), the first internal circuit and the added second internal circuit unit (now placed in the second peripheral area per Yu) would be connected by incorporating Park’s CL1-type inter-driver wiring, which reads on “a third connection line among the connection lines connects the first internal circuit unit and the second internal circuit unit”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the Jeon/Lee/Yu display panel to include Park’s inter-driver connection line CL1 because Park teaches such connection lines are used to distribute/transfer the driving voltage between multiple gate drivers so that driving voltages applied to multiple gate driving chips/drivers can be provided at same level and managed via controlled resistance paths- i.e., a predictable wiring modification to ensure consistent driving conditions when multiple internal circuit units are used in different peripheral regions (Park, ¶ [0088]).
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
Wu (US 20210225217 A1) and Yeo (US 20150116292 A1) disclose display device with driving circuits in the peripheral areas.
Conclusion
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/BIPANA ADHIKARI DAWADI/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898