Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al, US 20190393153 A1.
Wang discloses:
1. A semiconductor package, comprising: an interposer comprising:
a first redistribution structure (1001);
a first semiconductor die (854) electrically coupled to the first redistribution structure (1001) through conductive joints (403,405),
the first semiconductor die comprising:
a semiconductor substrate (101) comprising a first side facing (not labeled Figure 18b) the first redistribution structure and a second side (not labeled Figure 18b) opposite to the first side, wherein a conductive via (upper portion of 1012 shown figure 10)) of the first redistribution structure (1001) is tapered in a direction from the second side toward the first side;
a through substrate via (TSV) (201 Figure 18A) provided within the semiconductor substrate; and
a passive device (103) disposed between the second side of the semiconductor substrate and the conductive joints; and
a first encapsulant (901) disposed on the first redistribution structure and laterally covering the first semiconductor die.
2. The semiconductor package of claim 1, wherein the passive device (103) is a deep trench capacitor, and conductive contacts of the deep trench capacitor are disposed in proximity to the first side and distal from the second side of the semiconductor substrate. Para 14, Figure 18A and 18B
3. The semiconductor package of claim 1, wherein the conductive joints are solder joints. Para 31
6. The semiconductor package of claim 1, further comprising:
at least one second semiconductor die (801) stacked upon the interposer and electrically coupled to the first semiconductor die (854), wherein the interposer further comprises:
a first bonding structure (1403) disposed on the first semiconductor die and the first encapsulant (901), the first bonding structure comprising a first bonding dielectric layer (705) and first bonding features (1403),
wherein the at least one second semiconductor die comprises a second bonding structure (1403) comprising a second bonding dielectric layer (1405) and second bonding features (1403), the first bonding dielectric layer is fused to the second bonding dielectric layer, and the first bonding features are bonded to the second bonding features. (see figures 14, 18A and 18B)
7. The semiconductor package of claim 6, wherein the first bonding dielectric layer (705) is substantially leveled with the first bonding features (1403), and the second bonding dielectric layer (1405) is substantially leveled with the second bonding features (1403). (see figures 14, 18A and 18B)
8. The semiconductor package of claim 6, further comprising:
a second encapsulant (1417) covering the at least one second semiconductor die (140), wherein the first bonding dielectric layer (705) is interposed between the first encapsulant (901) and the second encapsulant. (1417) (Figure 14, 18A and 18B)
10. The semiconductor package of claim 1, wherein a surface of the first encapsulant is substantially leveled with the second side of the semiconductor substrate and a surface of the TSV. (Figure 14, 18A and 18B)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
Wang fails to teach:
9. (Currently amended) The semiconductor package of claim 1, wherein the
conductive via comprises a first end and a second end opposite to and wider than the first end, and one of the conductive joints is interfaced with the second end of the conductive via.
Wang show in figure 18B, wherein the conductive via (upper portion of 1012) comprises a first end and a second end opposite to and less wide than the first end, and one of the conductive joints (403,405) is interfaced with the second end of the conductive via.
Wang show that another via, not labeled as part of the external connectors (1403) in which wherein the conductive via comprises a first end and a second end opposite to and wider than the first end. (figure 14)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of wang, because the tapered shape is conventionally formed in the art by adjusting the etch characteristics.
Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of Yu et al, US 20210020574 A1.
Wang fails to teach:
4. The semiconductor package of claim 1, further comprising: at least one second semiconductor die stacked upon the interposer and electrically coupled to the first semiconductor die, wherein the interposer further comprises:
a second redistribution structure disposed on the first semiconductor die and the first encapsulant and disposed below the at least one second semiconductor die, wherein the at least one second semiconductor die is electrically coupled to the TSV of the first semiconductor die through the second redistribution structure.
5. The semiconductor package of claim 4, wherein the TSV of the first semiconductor die extends from the first side to the second side of the semiconductor substrate, and a conductive via of the second redistribution structure directly lands on the TSV of the first semiconductor die.
Wang teaches: at least one second semiconductor die (1400) stacked upon the interposer and electrically coupled to the first semiconductor die (854), wherein the interposer further Wang further discloses: (para 67) the second substrate (1411) may be, e.g., a packaging substrate comprising internal interconnects (e.g., metallization layers, through substrate vias, etc.) to connect the second semiconductor device 1413 and the third semiconductor device 1415 to the interconnect structures 850 and first semiconductor device 801 via the third external connectors 1403
Yu teaches: a second redistribution structure (42) disposed on the first semiconductor die (128) and the first encapsulant (38) and disposed below the at least one second semiconductor die (46,48), wherein the at least one second semiconductor die is electrically coupled to the TSV (134) of the first semiconductor die through the second redistribution structure (42).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to combine Wang with Yu, because for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. (para 58, Yu)
Claim(s) 11 and 12, and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang cited above, and further in view of Lin et al, US 9496233 B2.
Wang teaches:
11. A semiconductor package, comprising: an interposer comprising: a first redistribution structure (1001);
a first semiconductor die (854) comprising a first side, a second side opposite to the first side, a sidewall connected to the first side and the second side, and a capacitor (103) disposed between the first and second sides;
conductive joints (403.405) coupling the first side of the first semiconductor die to the first redistribution structure (1001);
a molding layer (901) extending along the sidewall of the first semiconductor die; and
at least one second semiconductor die (801) disposed over and electrically coupled second side of the first semiconductor die, (Figure 14, 18A and 18B)
Wang fails to teach:
wherein a bonding interface of the at least one second semiconductor die and the interposer is free of solder material..
12. (currently amended) The semiconductor package of claim 11, wherein the interposer further comprises:
a first bonding structure bonded to the at least one second semiconductor die, the first bonding structure comprising a first bonding dielectric layer and first bonding features laterally covered by the bonding dielectric layer.
Lin teaches:
(22) Referring now to FIG. 2, an embodiment chip-to-chip structure 40 is illustrated. The chip-to-chip structure 40 is similar to the BOT structure 10 of FIG. 1. However, the chip-to-chip structure 40 of FIG. 2 includes a second metal ladder bump 42 mounted on a second UBM feature 44 of a second integrated circuit 46 instead of the substrate trace 18 on the substrate 20. As shown, the second metal ladder bump 42 also has a tapering profile and is structurally and electrically coupled to the first metal ladder bump 16 through direct metal-to-metal bonding.
(23) In an embodiment, the second integrated circuit 46 includes a second passivation layer 48, a second insulating layer 50 (e.g., ELK dielectric), and a second contact element 52 (e.g., aluminum pad). Various layers and features of the second integrated circuit 46, including transistors, interconnect layers, post passivation interconnects, redistribution layers, and the like are omitted from the figures for the sake of clarity, as they are not necessary to an understanding of the present disclosure. In addition, the second metal ladder bump 16 may be formed in similar fashion and with similar dimensions relative to the metal ladder bump 16 of FIG. 1.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lin, with the primary reference of Wang, because by using alternative materials and methods avoids the formation intermetallic compounds (IMCs) between the metal-solder interface. The IMCs may cause higher electrical resistivity (contact resistance). The higher electrical resistivity leads to increased electromigration, which further increases the contact resistance. In addition, with a small area under bump metallurgy (UBM), the solder/metal electromigration issue may be of greater concern. Lin (para 2)
Wang further teaches:
14. The semiconductor package of claim 11, wherein the at least one second semiconductor die (1400) comprises a first die (1413) and a second die (1415), and the first semiconductor die (854) is directly below both of the first die and the second die and interconnects the first die and the second die. Figure 18B, para 64
15. The semiconductor package of claim 11, wherein the interposer further comprises:
conductive terminals (1012, 1014, 1016) landing on conductive vias (1003) of the first redistribution structure (1001), Figure 10
wherein the conductive joints and the conductive terminals are disposed at two opposing sides of the first redistribution structure. Figure 10
16. The semiconductor package of claim 11, wherein the capacitor (103) is a deep trench capacitor, and conductive contacts of the deep trench capacitor are disposed in proximity to the first side and distal from the second side of the first semiconductor die. Figure 14, 18A and B
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang and Lin as applied to claim 11 above, and further in view of Yu et al, US 20210020574 A1.
Wang fails to teach:
13. (currently amended) The semiconductor package of claim 11, further comprising:
an encapsulant covering the bonding interface and extending along a sidewall of the at least one second semiconductor die, wherein a sidewall of the encapsulant is substantially coplanar with a sidewall of the molding layer.
Yu teaches:
an encapsulant (52) covering the bonding interface (40) and extending along a sidewall of the at least one second semiconductor die (46A), wherein a sidewall of the encapsulant is substantially coplanar with a sidewall of the molding layer. See Figure 2
Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of Yu, with the primary references of Wang and Lin, because [by] [l]eaving some encapsulant 52 over package components 46A and 46B may keep the resulting package thick enough for the subsequent processes, and may keep the back surfaces of package components 46A and 46B protected in the processes shown in FIGS. 3 and 4. Yu, para 035.
Claim(s) 17, 18 and 20 is is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang.
17. A manufacturing method of a semiconductor package, comprising: forming an interposer comprising:
coupling a first semiconductor die (854) to a first redistribution structure (1001) through conductive joints (403, 405), wherein the first semiconductor die includes a first side to which the conductive joints are connected, a second side opposite to the first side, a through substrate via (TSV) (201) extending from the first side to the second sides, and wherein one of the conductive joints (403,405) is interfaced with the second end of the conductive via (upper portion 1012);
a capacitor (103) disposed between the first and second sides; and forming a molding layer (901) on the first redistribution structure (1001) to cover the first semiconductor die (854), wherein when forming the molding layer, a planarization process is performed on the second side of the first semiconductor die and the molding layer; and
coupling at least one second semiconductor die (801) to the interposer. Figures 14, 18A and 18B
Wang fails to teach:
wherein the conductive via comprises a first end and a second end opposite to and wider than the first end
Wang show in figure 18B, wherein the conductive via (upper portion of 1012) comprises a first end and a second end opposite to and less wide than the first end, and one of the conductive joints (403,405) is interfaced with the second end of the conductive via.
Wang show that another via, not labeled as part of the external connectors (1403) in which wherein the conductive via comprises a first end and a second end opposite to and wider than the first end. (figure 14)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of wang, because the tapered shape is conventionally formed in the art by adjusting the etch characteristics.
18. The manufacturing method of claim 17, wherein after the planarization process, the TSV (201) is exposed by a semiconductor substrate of the first semiconductor die, and
the capacitor (103) remains buried in the semiconductor substrate. Figures 14, 18A and 18B
20. The manufacturing method of claim 17, wherein: forming the interposer further comprises forming a first bonding structure (1403) on the molding layer (901) and the first semiconductor die, wherein the first bonding structure (1403) comprises a first bonding dielectric layer (705) and first bonding features (1403) laterally covered by the first bonding dielectric layer (705); and
coupling the at least one second semiconductor die (1400) to the interposer comprises bonding a second bonding dielectric layer (1405) of a second bonding structure (1403) of the at least one second semiconductor die (1400) to the first bonding dielectric layer (705) and bonding second bonding features (1403) of the second bonding structure (1403) of the at least one second semiconductor die (1400) to the first bonding features (1403). Figures 14, 18A and 18B
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 17 above, and further in view of Yu et al, US 20210020574 A1.
Wang fails to teach:
19. The manufacturing method of claim 17, wherein forming the interposer further comprises: forming a second redistribution structure on the molding layer and the first semiconductor die, wherein a conductive via of the second redistribution structure directly land on the TSV.
Wang teaches: at least one second semiconductor die (1400) stacked upon the interposer and electrically coupled to the first semiconductor die (854), wherein the interposer further Wang further discloses: (para 67) the second substrate (1411) may be, e.g., a packaging substrate comprising internal interconnects (e.g., metallization layers, through substrate vias, etc.) to connect the second semiconductor device 1413 and the third semiconductor device 1415 to the interconnect structures 850 and first semiconductor device 801 via the third external connectors 1403
Yu teaches: a second redistribution structure (42) disposed on the first semiconductor die (128) and the first encapsulant (38) and disposed below the at least one second semiconductor die (46,48), wherein the at least one second semiconductor die is electrically coupled to the TSV (134) of the first semiconductor die through the second redistribution structure (42).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to combine Wang with Yu, because for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. (para 58, Yu)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al, US 20160338202 A1 teaches that a conductive via (143), as part of the redistribution structure (140) conventionally formed in the art has a tapered via shape. Please See figure 3. Furthermore Paragraph 103 states “In addition, the redistribution part vias 143 and 153 may have all of the shapes known in the related art, such as a tapered shape in which a diameter of the via becomes smaller toward a lower surface, a reverse tapered shape in which a diameter of the via becomes larger toward a lower surface, a cylindrical shape, and the like.”
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893
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