Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/24/2023 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-11, 13- 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al, US 20190393153 A1.
Wang discloses:
1. A semiconductor package, comprising:
an interposer comprising:
a first redistribution structure (1001);
a first semiconductor die (854) electrically coupled to the first redistribution structure (1001) through conductive joints (403,405),
the first semiconductor die comprising:
a semiconductor substrate (101) comprising a first side (not labeled Figure 18B) facing the first redistribution structure and a second side (not labeled Figure 18B) opposite to the first side;
a through substrate via (TSV) (201) Figure 18a) provided within the semiconductor substrate;
and
a passive device (103) disposed between the second side of the semiconductor
substrate (101) and the conductive joints (403,405); and
a first encapsulant (901) disposed on the first redistribution structure (1001) and laterally covering the first semiconductor die. Please see Figures 18A and 18B
2. The semiconductor package of claim 1, wherein the passive device (103) is a deep trench capacitor, and conductive contacts of the deep trench capacitor are disposed in proximity to the first side and distal from the second side of the semiconductor substrate. Para 14, Figure 18A and 18B
3. The semiconductor package of claim 1, wherein the conductive joints are solder joints. Para 31
6. The semiconductor package of claim 1, further comprising:
at least one second semiconductor die (801) stacked upon the interposer and electrically coupled to the first semiconductor die (854), wherein the interposer further comprises:
a first bonding structure (1403) disposed on the first semiconductor die and the first encapsulant (901), the first bonding structure comprising a first bonding dielectric layer (705) and first bonding features (1403),
wherein the at least one second semiconductor die comprises a
second bonding structure (1403) comprising a second bonding dielectric layer (1405) and second bonding features (1403), the first bonding dielectric layer is fused to the second bonding dielectric layer, and the first bonding features are bonded to the second bonding features. (see figures 14, 18A and 18B)
7. The semiconductor package of claim 6, wherein the first bonding dielectric layer (705) is substantially leveled with the first bonding features (1403), and the second bonding dielectric layer (1405) is substantially leveled with the second bonding features (1403). (see figures 14, 18A and 18B)
8. The semiconductor package of claim 6, further comprising:
a second encapsulant (1417) covering the at least one second semiconductor die (140), wherein the first bonding dielectric layer (705) is interposed between the first encapsulant (901) and the second encapsulant. (1417) (Figure 14, 18A and 18B)
9. The semiconductor package of claim 1, wherein the first encapsulant (901) is a molding layer directly and laterally covering the conductive joints. Para 49, (Figure 14, 18A and 18B)
10. The semiconductor package of claim 1, wherein a surface of the first encapsulant is substantially leveled with the second side of the semiconductor substrate and a surface of the TSV. (Figure 14, 18A and 18B)
11. A semiconductor package, comprising:
an interposer comprising:
a first redistribution structure (1001);
a first semiconductor die (854) comprising a first side, a second side opposite to the first side, a sidewall connected to the first side and the second side, and a capacitor (103) disposed between the first and second sides;
conductive joints (403,405) coupling the first side of the first semiconductor die to the first redistribution structure (1001);
a molding layer (901) extending along the sidewall of the first semiconductor die; and
at least one second semiconductor die (801) disposed over and electrically coupled to the interposer. (Figure 14, 18A and 18B)
13. The semiconductor package of claim 11, wherein a bonding interface of the at least one second semiconductor die (801) and the interposer is free of solder material. (Figure 14, 18A and 18B)
14. The semiconductor package of claim 11, wherein the at least one second
semiconductor die (1400) comprises a first die (1413) and a second die (1415), and the first semiconductor die (854) is directly below both of the first die and the second die and interconnects the first die and the second die. Figure 18B, para 64
15. The semiconductor package of claim 11, wherein the interposer further comprises:
conductive terminals (1012, 1014, 1016) landing on conductive vias (1003) of the first redistribution structure (1001), Figure 10
wherein the conductive joints and the conductive terminals are disposed at two opposing sides of the first redistribution structure. Figure 10
16. The semiconductor package of claim 11, wherein the capacitor (103) is a deep trench capacitor, and conductive contacts of the deep trench capacitor are disposed in proximity to the first side and distal from the second side of the first semiconductor die. Figure 14, 18A and B
17. A manufacturing method of a semiconductor package, comprising:
forming an interposer comprising:
coupling a first semiconductor die (854) to a first redistribution structure (1001) through conductive joints (403, 405), wherein the first semiconductor die includes a first side to which the conductive joints are connected, a second side opposite to the first side, a through substrate via (TSV) (201) extending from the first side to the second side, and
a capacitor (103) disposed between the first and second sides; and
forming a molding layer (901) on the first redistribution structure (1001) to cover the first semiconductor die (854), wherein when forming the molding layer, a planarization process is performed on the second side of the first semiconductor die and the molding layer; and
coupling at least one second semiconductor die (801) to the interposer. Figures 14, 18A and 18B
18. The manufacturing method of claim 17, wherein after the planarization process, the TSV (201) is exposed by a semiconductor substrate of the first semiconductor die, and
the capacitor (103) remains buried in the semiconductor substrate. Figures 14, 18A and 18B
20. The manufacturing method of claim 17, wherein:
forming the interposer further comprises forming a first bonding structure (1403) on the molding layer (901) and the first semiconductor die, wherein the first bonding structure (1403) comprises a first bonding dielectric layer (705) and first bonding features (1403) laterally covered by the first bonding dielectric layer (705); and
coupling the at least one second semiconductor die (1400) to the interposer comprises bonding a second bonding dielectric layer (1405) of a second bonding structure (1403) of the at least one second semiconductor die (1400) to the first bonding dielectric layer (705) and bonding second bonding features (1403) of the second bonding structure (1403) of the at least one second semiconductor die (1400) to the first bonding features (1403). Figures 14, 18A and 18B
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 12,13, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1, 11 and 17 above, and further in view of Yu et al, US 20210020574 A1.
Wang fails to teach:
4. The semiconductor package of claim 1, further comprising:
at least one second semiconductor die stacked upon the interposer and electrically coupled to the first semiconductor die, wherein the interposer further comprises:
a second redistribution structure disposed on the first semiconductor die and the first encapsulant and disposed below the at least one second semiconductor die, wherein the at least one second semiconductor die is electrically coupled to the TSV of the first semiconductor die through the second redistribution structure.
5. The semiconductor package of claim 4, wherein the TSV of the first semiconductor die extends from the first side to the second side of the semiconductor substrate, and a conductive via of the second redistribution structure directly lands on the TSV of the first semiconductor die.
12. The semiconductor package of claim 11, wherein the interposer further comprises:
a second redistribution structure disposed on the second side of the first
semiconductor die and the first encapsulant, wherein conductive vias of the second redistribution structure directly land on through substrate vias of the first semiconductor die at the second side of the first semiconductor die.
13. The semiconductor package of claim 11, wherein a bonding interface of the at least one second semiconductor die and the interposer is free of solder material.
19. The manufacturing method of claim 17, wherein forming the interposer further
comprises:
forming a second redistribution structure on the molding layer and the first
semiconductor die, wherein a conductive via of the second redistribution structure directly land on the TSV.
Wang teaches:
at least one second semiconductor die (1400) stacked upon the interposer and electrically coupled to the first semiconductor die (854), wherein the interposer further
Wang further discloses: (para 67)
the second substrate (1411) may be, e.g., a packaging substrate comprising internal interconnects (e.g., metallization layers, through substrate vias, etc.) to connect the second semiconductor device 1413 and the third semiconductor device 1415 to the interconnect structures 850 and first semiconductor device 801 via the third external connectors 1403
Yu teaches:
a second redistribution structure (42) disposed on the first semiconductor die (128) and the first encapsulant (38) and disposed below the at least one second semiconductor die (46,48), wherein the at least one second semiconductor die is electrically coupled to the TSV (134) of the first semiconductor die through the second redistribution structure (42).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention, to combine Wang with Yu, because for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs. (para 58, Yu)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/ Primary Examiner, Art Unit 2893