DETAILED ACTION
This Office action responds to the application filed on 10/25/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Pending Claims
Applicant’s preliminary amendment, filed on 01/13/2025, is acknowledged. Applicant cancelled Claims 5-8, 10, 17, 20-25, 32, 33, 37 & 39-48. Claims 1-4, 9, 11-16, 18, 19, 26-31, 34-36, & 38 will be examined in this Office action.
Claim Objections
Claim 26 is objected to because of the following informalities:
Incorrect spelling of “apparat” in line 3.
Appropriate correction is required.
Claim Rejections – 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12 & 34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "the support shield" in line 4. There is insufficient antecedent basis for this limitation in the claim.
A portion of Claim 12 is construed as follows in order to further examination: “wherein a support shield…”
Claim 34 recites the limitation "the second conductivity type" in line 10. There is insufficient antecedent basis for this limitation in the claim.
A portion of Claim 34 is construed as follows in order to further examination: “a first support shield having a second conductivity type”
Examiner reminds Applicant that Claim 35, line 2, has “a second conductivity type” and needs to be considered when correcting the lack of antecedent basis in Claim 34.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 3, 9, 11, 14, 15, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295).
Regarding Claim 1, Moore (see, e.g., fig. 7) shows a semiconductor device, comprising:
a semiconductor layer structure that comprises
a drift region 32 (see, e.g., para.0009) having a first conductivity type (n-type)
and an implanted region 14 (see, e.g., para.0009) having a second conductivity type (p-type) on the drift region;
a first gate trench section 12 & 22 (left gate, see, e.g., annotated figure 7, para.0007) in the semiconductor layer structure;
and a second gate trench section 12 & 22 (right gate, see, e.g., annotated figure 7, para.0007) in the semiconductor layer structure;
wherein a first maximum depth into the semiconductor layer structure of a first portion of the implanted region (depth of 54, see, e.g., annotated figure 7) that is between the first gate trench section and the second gate trench section is different than a second maximum depth into the semiconductor layer structure of a second portion of the implanted region (depth of 52, see, e.g., annotated figure 7) that extends downwardly underneath the first gate trench section.
Moore, however, fails to show
a silicon carbide based semiconductor layer
Ngwendson (see, e.g., fig. 1, para.00002), in a similar device to Moore, teaches that silicon carbide as a semiconductor layer would be a suitable and obvious material for the semiconductor layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the silicon carbide of Ngwendson in the device of Moore as a suitable and obvious material for the semiconductor layer.
Regarding Claim 2, Moore (see, e.g., annotated figure 7), in view of Ngwendson, shows the semiconductor device of Claim 1,
wherein the first maximum depth is greater than the second maximum depth (see, e.g., annotated figure 7).
Regarding Claim 3, Moore (see, e.g., annotated figure 7), in view of Ngwendson, shows the semiconductor device of Claim 2,
wherein the implanted region comprises
a first trench shielding region (52 under first gate trench, see, e.g., annotated figure 7) that is below the first gate trench section,
a second trench shielding region (52 under second gate trench, see, e.g., annotated figure 7) that is below the second gate trench section
and a support shield (54, see, e.g., annotated figure 7, para.0045-0047) that is at least partially in between the first gate trench section and the second gate trench section.
Regarding Claim 9, Moore (see, e.g., fig. 7), in view of Ngwendson (see, e.g., fig. 1, annotated figure 1, para.0068), shows the semiconductor device of Claim 1, further comprising
a first gate dielectric layer 22 (pertaining to first gate trench section, see, e.g., para.0007) in the first gate trench section
and a second gate dielectric layer 22 (pertaining to second gate trench section, see, e.g., para.0007) in the second gate trench section,
wherein a lateral thickness of a first portion of the first gate dielectric layer that is on a first sidewall of the first gate trench section that faces the second gate trench section is greater than a lateral thickness of a second portion of the first gate dielectric layer that is on a second sidewall of the first gate trench section (see, e.g., annotated figure 1),
and wherein a lateral thickness of a first portion of the second gate dielectric layer that is on a first sidewall of the second gate trench section that faces the first gate trench section is greater than a lateral thickness of a second portion of the second gate dielectric layer that is on a second sidewall of the second gate trench section (see, e.g., annotated figure 1).
Regarding the lateral thicknesses of the first and second portions of the first and second gate dielectric layers, Ngwendson (see, e.g., fig. 1, annotated figure 1, para.0068) teaches a configuration wherein the claimed relationships between lateral thicknesses of first and second gate dielectric layers 120 is shown. Ngwendson states the asymmetric lateral thicknesses of gate dielectric layers can reduce gate to drain capacitance and improve switching speed.
Regarding Claim 11, Moore (see, e.g., fig. 7), in view of Ngwendson, shows the semiconductor device of Claim 1,
wherein the first gate trench section is part of a first gate trench (12 & 22, left gate),
the second gate trench section is part of a second gate trench (12 & 22, right gate),
where the second gate trench is spaced apart from the first gate trench and extends in parallel to the first gate trench.
Regarding Claim 14, Moore (see, e.g., fig. 7, fig. 8), in view of Ngwendson, shows the semiconductor device of Claim 1,
wherein the first gate trench section 12 & 22 (left gate) and the second gate trench section 12 & 22 (right gate) are both part of a first gate trench.
Regarding Claim 15, Moore (see, e.g., fig. 4, annotated figure 4), in view of Ngwendson, shows the semiconductor device of Claim 14,
wherein the first gate trench has a closed ring shape when viewed from above.
Under broadest reasonable interpretation “ring shape” can be defined by a closed shape such as the rectangular shape of the first gate trench shown in fig. 4.
Regarding Claim 16, Moore (see, e.g., fig. 6, annotated figure 6), in view of Ngwendson, shows the semiconductor device of Claim 1,
wherein the first maximum depth (depth of 54) is less than the second maximum depth (depth of 52) (see, e.g., annotated figure 6).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295) and further in view of Suzuki (US 20090114969).
Regarding Claim 4, Moore (see, e.g., para.0045), in view of Ngwendson, shows the semiconductor device of Claim 3,
wherein the semiconductor layer structure further comprises
a well region 42 (see, e.g., para.0045) having the second conductivity type on the drift region,
Moore, in view of Ngwendson, however, fails to show
an upper portion of the drift region 126 comprises a JFET region 126 that has a higher concentration of first conductivity type dopants than a lower portion of the drift region (120 layer above 110 substrate),
and the support shield extends downwardly through the JFET region into the lower portion of the drift region,
wherein the first trench shielding region and the second trench shielding region do not extend through the JFET region 126 into the lower portion of the drift region.
Suzuki (see, e.g., fig. 9, para.0087-0089), in a similar device to Moore, in view of Ngwendson, teaches
an upper portion of the drift region (combined 50 & 2) comprises a JFET region 50 that has a higher concentration of first conductivity type dopants than a lower portion of the drift region 2 (n+ higher than n-),
and the support shield extends downwardly through the JFET region into the lower portion of the drift region,
wherein the first trench shielding region (40) and the second trench shielding region (40) do not extend through the JFET region 50 into the lower portion of the drift region (40 does not extend into lower portion of the drift region 2).
Suzuki teaches said configuration would lower on resistance.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Suzuki in the device of Moore, in view of Ngwendson, to lower on resistance.
Claims 12 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295) and further in view of Kinoshita (US 20240097025).
Regarding Claim 12, Moore (see, e.g., fig. 10, annotated figure 10a), in view of Ngwendson, shows the semiconductor device of Claim 11, further comprising:
a third gate trench (12 & 22 middle gate, see, e.g., annotated figure 10a) extending into the semiconductor layer structure,
where the first and third gate trenches are the closest gate trenches to the second gate trench,
wherein a support shield is a first support shield (54 portion of 14, see, e.g., para.0045-0047)
Moore, in view of Ngwendson, however, fails to show
and the semiconductor layer structure further comprises
a second support shield having the second conductivity type in between the second gate trench and the third gate trench.
Kinoshita (see, e.g., fig. 1, fig. 4, para.0034), in a similar device to Moore, in view of Ngwendson, teaches that support shields 22 having a second conductivity type (p-type) between gate trenches (7, 8, & 9 in fig. 4 top view) would mitigate electric fields between gate trenches.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the support shields having a second conductivity type between gate trenches of Kinoshita in the device of Moore, in view of Ngwendson, to mitigate electric fields between gate trenches.
Regarding Claim 13, Moore (see, e.g., annotated figure 10a), in view of Ngwendson and further in view of Kinoshita, shows the semiconductor device of Claim 12,
wherein a minimum distance between the second gate trench and the second support shield is greater than a minimum distance between the second gate trench and the first support shield.
Additionally, it would have been obvious to one of ordinary skill in the art to vary the minimum distances between the second gate trench and the second support shield and between second gate trench and the first support shield by routine optimization in order to mitigate the electric field between gate trenches, see MPEP 2144.05 (II).
Claims 18, 19, 26, 29, 30, & 31 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295).
Regarding Claim 18, Moore (see, e.g., fig. 7) shows a semiconductor device, comprising:
a semiconductor layer structure that comprises
a drift region 32 (see, e.g., para.0009) having a first conductivity type (n-type),
a first trench shielding region (52 under first gate trench, see, e.g., annotated figure 7) having a second conductivity type (p-type) in the drift region,
a second trench shielding region (52 under second gate trench, see, e.g., annotated figure 7) having the second conductivity type in the drift region,
and a support shield (54, see, e.g., annotated figure 7, para.0045-0047) having the second conductivity type;
a first gate trench section 12 & 22 (left gate, see, e.g., annotated figure 7, para.0007) in the semiconductor layer structure;
and a second gate trench section 12 & 22 (right gate, see, e.g., annotated figure 7, para.0007) in the semiconductor layer structure;
wherein the support shield vertically overlaps both the first gate trench section and the second gate trench section,
and a maximum depth of the support shield (depth of 54, see, e.g., annotated figure 7) into the semiconductor layer structure differs from a maximum depth of the first trench shielding region (depth of 52, see, e.g., annotated figure 7) into the semiconductor layer structure .
Moore, however, fails to show
a silicon carbide based semiconductor layer
Ngwendson (see, e.g., fig. 1, para.00002), in a similar device to Moore, teaches that silicon carbide as a semiconductor layer would be a suitable and obvious material for the semiconductor layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the silicon carbide of Ngwendson in the device of Moore as a suitable and obvious material for the semiconductor layer.
Regarding Claim 19, Moore (see, e.g., annotated figure 7), in view of Ngwendson, shows the semiconductor device of Claim 18,
wherein the maximum depth of the support shield into the semiconductor layer structure is greater than the maximum depth of the first trench shielding region into the semiconductor layer structure (see, e.g., annotated figure 7).
Regarding Claim 26, Moore (see, e.g., fig. 7), in view of Ngwendson, shows the semiconductor device of Claim 18,
wherein the first gate trench section is part of a first gate trench (12 & 22, left gate),
the second gate trench section is part of a second gate trench (12 & 22, right gate),
where the second gate trench is spaced apparat from the first gate trench and extends in parallel to the first gate trench.
Regarding Claim 29, Moore (see, e.g., fig. 7), in view of Ngwendson (see, e.g., fig. 1, annotated figure 1, para.0068) shows the semiconductor device of Claim 18, further comprising
a first gate dielectric layer 22 (pertaining to first gate trench section, see, e.g., para.0007) in the first gate trench section
and a second gate dielectric layer 22 (pertaining to second gate trench section, see, e.g., para.0007) in the second gate trench section,
wherein a lateral thickness of a first portion of the first gate dielectric layer that is on a first sidewall of the first gate trench section that faces the second gate trench section is greater than a lateral thickness of a second portion of the first gate dielectric layer that is on a second sidewall of the first gate trench section (see, e.g., annotated figure 1),
and wherein a lateral thickness of a first portion of the second gate dielectric layer that is on a first sidewall of the second gate trench section that faces the first gate trench section is greater than a lateral thickness of a second portion of the second gate dielectric layer that is on a second sidewall of the second gate trench section (see, e.g., annotated figure 1).
Regarding the lateral thicknesses of the first and second portions of the first and second gate dielectric layers, Ngwendson (see, e.g., fig. 1, annotated figure 1, para.0068) teaches a configuration wherein the claimed relationships between lateral thicknesses of first and second gate dielectric layers 120 is shown. Ngwendson states the asymmetric lateral thicknesses of gate dielectric layers can reduce gate to drain capacitance and improve switching speed.
Regarding Claim 30, Moore in view of Ngwendson (see, e.g., annotated figure 1), shows the semiconductor device of Claim 29,
wherein a thickness of a bottom portion of the first gate dielectric layer 120 (left trench) is greater than a thickness of the first portion of the first gate dielectric layer,
and wherein a thickness of a bottom portion of the second gate dielectric layer 120 (right trench) is greater than a thickness of the first portion of the second gate dielectric layer.
Regarding Claim 31, Moore (see, e.g., fig. 7), in view of Ngwendson, shows the semiconductor device of Claim 18,
wherein the first gate trench section and the second gate trench section are both part of a first gate trench (combined 12 & 22 left and right gates).
Claims 27 & 28 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295) and further in view of Kinoshita (US 20240097025).
Regarding Claim 27, Moore (see, e.g., fig. 16, annotated figure 16), in view of Ngwendson, shows the semiconductor device of Claim 26, further comprising:
a third gate trench (12 & 22 middle gate, see, e.g., annotated figure 10a) extending into the semiconductor layer structure,
where the first and third gate trenches are the closest gate trenches to the second gate trench,
wherein the support shield comprises a first support shield (54 portion of 14, see, e.g., para.0045-0047)
Moore, in view of Ngwendson, however, fails to show
and the semiconductor layer structure further comprises
a second support shield having the second conductivity type in between the second gate trench and the third gate trench.
Kinoshita (see, e.g., fig. 1, fig. 4, para.0034), in a similar device to Moore, in view of Ngwendson, teaches that support shields 22 having a second conductivity type (p-type) between gate trenches (7, 8, & 9 in fig. 4 top view) would mitigate electric fields between gate trenches.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the support shields having a second conductivity type between gate trenches of Kinoshita in the device of Moore, in view of Ngwendson, to mitigate electric fields between gate trenches.
Regarding Claim 28, Moore (see, e.g., annotated figure 10a), in view of Ngwendson and further in view of Kinoshita, shows the semiconductor device of Claim 27,
wherein a minimum distance between the second gate trench and the second support shield is greater than a minimum distance between the second gate trench and the first support shield.
Additionally, it would have been obvious to one of ordinary skill in the art to vary the minimum distances between the second gate trench and the second support shield and between second gate trench and the first support shield by routine optimization in order to mitigate the electric field between gate trenches, see MPEP 2144.05 (II).
Claims 34, 35, 36, & 38 are rejected under 35 U.S.C. 103 as being unpatentable over Moore (US 20230032610) in view of Ngwendson (US 20220320295).
Regarding Claim 34, Moore (see, e.g., fig. 7, fig. 10, annotated figure 10b) shows a semiconductor device, comprising:
a semiconductor layer structure that comprises
a drift region 32 (see, e.g., para.0009) having a first conductivity type (n-type);
a first gate trench and a second gate trench in the semiconductor layer structure that form a first pair of gate trenches (12 &22 leftmost gates, see, e.g., annotated figure 10b),
where the first gate trench is adjacent the second gate trench;
a third gate trench and a fourth gate trench in the semiconductor layer structure that form a second pair of gate trenches (12 &22 rightmost gates, see, e.g., annotated figure 10b),
the second pair of gate trenches adjacent the first pair of gate trenches,
where the third gate trench is adjacent the fourth gate trench;
a first support shield 54 (of first pair of gate trenches, para.0045-0047) having a second conductivity type in the semiconductor layer structure,
an upper portion of the first support shield 42 (of first pair of gate trenches, see, e.g., para.0045) in between the first gate trench and the second gate trench;
a second support shield 54 (of second pair of gate trenches, para.0045-0047) having the second conductivity type in the semiconductor layer structure,
an upper portion of the second support shield 42 (of second pair of gate trenches, para.0045) in between the third gate trench and the fourth gate trench;
and a third support shield 52 (between middle gate trench) having the second conductivity type in the semiconductor layer structure in between the first pair of gate trenches and the second pair of gate trenches,
wherein a distance between the third support shield and closest one of the first through fourth gate trenches exceeds a distance between the first support shield and the first gate trench (see, e.g., annotated figure 10b).
Moore, however, fails to show
a silicon carbide based semiconductor layer
Ngwendson (see, e.g., fig. 1, para.00002), in a similar device to Moore, teaches that silicon carbide as a semiconductor layer would be a suitable and obvious material for the semiconductor layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the silicon carbide of Ngwendson in the device of Moore as a suitable and obvious material for the semiconductor layer.
Regarding Claim 35, Moore (see, e.g., fig. 10, annotated figure 10b), in view of Ngwendson, shows the semiconductor device of Claim 34,
wherein the semiconductor layer structure further comprises
a first trench shielding region (52 under first gate trench) having a second conductivity type underneath the first gate trench
and a second trench shielding region having the second conductivity type underneath the second gate trench (52 under second gate trench),
and the first support shield merges into the first and second trench shielding regions (see, e.g., annotated figure 10b).
Regarding Claim 36, Moore (see, e.g., fig. 7, fig. 10), in view of Ngwendson, shows the semiconductor device of Claim 35,
wherein a maximum depth of the first support shield 54 (of first pair of gate electrodes) exceeds a maximum depth of the first trench shielding region (52 under first gate trench, see, e.g., fig. 7, para.0045)
Regarding Claim 38, Moore (see, e.g., fig. 10), in view of Ngwendson, shows the semiconductor device of Claim 34,
wherein the first support shield forms a first sidewall of the first gate trench (right sidewall of first gate trench) and a first sidewall of the second gate trench (left sidewall of second gate trench).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814