DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 05/27/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 05/27/2026 in reply to the non-final rejection mailed on 03/04/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 26-31 are canceled. Claims 49 & 50 are added. Accordingly, pending in this Office action are claim(s) 1-4, 9, 11-16, 18-19, 34-36, 38, & 49-50.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 9, 11-16, 49, & 50 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the second conductivity type" in line 3. Line 5 of Claim 1 states “having a second conductivity type on the drift region” but the antecedent basis for the limitation is established after the limitation of line 3 and is therefore insufficient.
Claim 1 recites the limitation "the source metallization" in line 15. There is insufficient antecedent basis for this limitation in the claim. Line 8 of Claim 1 establishes “a source metallization layer” and it is unclear whether the line 15 limitation intends to make reference to the line 8 limitation.
Claims 2-4, 9, 11-16, 49, & 50 are rejected as being dependent on Claim 1.
Claim 4 recites the limitation “wherein the first trench shielding region and the second trench shielding region do not extend through the JFET region into the lower portion of the drift region” in lines 6-7. Claim 4 is rejected as the limitation does not distinctly claim the subject matter of the Application’s drawings as figures 2, 3d-e, 4f, 6a-c, 7, 8a-b, 9a-b, 10b, 11b, 12b, & 13 which all show the first and second trench shielding regions 54 /154 extending through the JFET regions 26/126.
Claim 14 recites the limitation “the third gate trench section” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitations “wherein the first gate trench section and the second gate trench section are both part of a first gate trench, and the third gate trench section is part of a second gate trench…” Claim 11 (which Claim 14 depends on Claim 12 which depends on Claim 11) recites the limitations “the first gate trench section is part of a first gate trench, the second gate trench section is part of a second gate trench.” It is unclear whether Applicant intends to establish a new element in Claim 14 or to reference the first gate trench and the second gate trench previously established in Claim 11.
Claim 35 recites the limitations “the first gate trench” and “the second gate trench” in lines 3-4. There is insufficient antecedent basis for these limitations in the claim.
Claim 36 recites the limitations “the first gate trench” and “the second gate trench” in line 2. There is insufficient antecedent basis for these limitations in the claim.
Claim 50 recites the limitation "the source metallization" in line 1. There is insufficient antecedent basis for this limitation in the claim. Line 8 of Claim 1 establishes “a source metallization layer” and it is unclear whether the line 1 limitation intends to make reference to the line 8 limitation of Claim 1.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9, 16, & 49 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998).
Regarding Claim 1, Kim (see, e.g., fig. 11) shows a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 650, 620, 632, 642, 686 (all elements are made of silicon carbide, see, e.g., para.0280-0282) that comprises
a drift region 620 having a first conductivity type (n-type, see, e.g., para.0280),
a well region 632 having the second conductivity type (p-type, see, e.g., para.0280) on the drift region 620,
a source region 642 having the first conductivity type (n-type, see, e.g., para.0280) on the well region 632,
and an implanted region 686 & 670 having a second conductivity type (p-type, see, e.g., para.0281-0282) on the drift region 620;
a first gate trench section 668-1 (hereinafter “668-1L”) in the semiconductor layer structure (see, e.g., annotated figure 1);
a second gate trench section (hereinafter “668-1R”) in the semiconductor layer structure (see, e.g., annotated figure 1);
a source 680 (see, e.g., para.0281) layer on the semiconductor layer structure;
and wherein a first maximum depth (hereinafter “D1”) into the semiconductor layer structure of a first portion 686 (region of 686) of the implanted region 686 & 670 that is between the first gate trench section and the second gate trench section is different than a second maximum depth (hereinafter “D2”) into the semiconductor layer structure of a second portion 670 of the implanted region 686 & 670 that extends downwardly underneath the first gate trench section (see, e.g., annotated figure 2);
wherein the source region 642 includes one or more openings (hereinafter “642O”, see, e.g., annotated figure 1)
and at least one of the well region 632 and the source 680 extends into the one or more openings 642O to directly contact both sidewalls of the source region (632 contacts the sidewalls of the source region, at least two sidewalls are contacted and satisfies “both sidewalls” even though the limitation “or more openings” would also imply more than 2 sidewalls, see, e.g., annotated figure 1),
and wherein a depth of the well region 632 into the semiconductor layer structure is less than a depth of the first gate trench section 668-1L (see, e.g., annotated figure 1).
PNG
media_image1.png
661
1164
media_image1.png
Greyscale
PNG
media_image2.png
661
1164
media_image2.png
Greyscale
Kim, in the embodiment of fig. 11, however fails to state source layer 680 is a source metallization layer. Kim (see, e.g., fig. 2e, para.0232), in the embodiment of figs. 2a-2f, states the source layer 180 can be made of metal. The metal of the source layer 180 of the embodiment of figs. 2a-2f is incorporated into the source layer 680 of the embodiment of fig. 11.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the metal of the source layer 180 of the embodiment of figs. 2a-2f of Kim in the source layer 680 of the embodiment of fig. 11 of Kim because the combination is a simple substitution of a known material for another to obtain predictable results – simple substitution of one metal source layer material for another source layer.
Regarding Claim 9, Kim shows the semiconductor device of Claim 1, further comprising
a first gate dielectric layer 662 & 663 (hereinafter “662L & 663L”) in the first gate trench section 668-1L
and a second gate dielectric layer (hereinafter “662R & 663R”)in the second gate trench section 668-1R,
wherein a lateral thickness of a first portion 663L (“defining the inner sidewall”, see, e.g., para.0283) of the first gate dielectric layer 662L & 663L that is on a first sidewall (inner sidewall in contact with 686, see, e.g., annotated figure 3) of the first gate trench section that faces the second gate trench section is greater than a lateral thickness of a second portion 662L (“defining the outer sidewall”, see, e.g., para.0283) of the first gate dielectric layer 662L & 663L that is on a second sidewall (outer sidewall, see, e.g., annotated figure 3) of the first gate trench section 668-1L,
and wherein a lateral thickness of a first portion 663R (“defining the inner sidewall”, see, e.g., para.0283) of the second gate dielectric layer 662R & 663R that is on a first sidewall (inner sidewall in contact with 686, see, e.g., annotated figure 3) of the second gate trench section that faces the first gate trench section is greater than a lateral thickness of a second portion 662R (“defining the outer sidewall”, see, e.g., para.0283) of the second gate dielectric layer 662R & 663R that is on a second sidewall (outer sidewall, see, e.g., annotated figure 3) of the second gate trench section 668-1R.
PNG
media_image3.png
793
1515
media_image3.png
Greyscale
Regarding Claim 16, Kim shows the semiconductor device of Claim 1,
wherein the first maximum depth D1 is less than the second maximum depth D2 (see, e.g., annotated figure 2).
Regarding Claim 49, Kim shows the semiconductor device of Claim 1,
wherein the well region 632 directly contacts both sidewalls of the source region 642 (through openings 642O see, e.g., annotated figure 1).
Claims 2, 3, & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998) in view of Moore (US 20230032610).
Regarding Claim 2, Kim shows the semiconductor device of Claim 1,
Kim, however, fails to show
wherein the first maximum depth D1 is greater than the second maximum depth D2.
Moore (see, e.g., fig. 7, para.0045-0047), in a similar device to Kim, teaches
a first maximum depth (hereinafter “D3”) into the semiconductor layer structure of a first portion 42 & 54 of the implanted region 42, 52, & 54 that is between the first gate trench section 12 (left gate) and the second gate trench section 12 (right gate) is different than a second maximum depth (hereinafter “D4”) into the semiconductor layer structure of a second portion 52 (under 12 left side) of the implanted region 42, 52, & 54 that extends downwardly underneath the first gate trench section 12 (left side)
wherein the first maximum depth D3 is greater than the second maximum depth D4 (see, e.g., annotated figure 4).
Moore (see, e.g., para.0046-0047) states the configuration of the first maximum depth D3 greater than the second maximum depth D4 would provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
The configuration of Moore, the first maximum depth is greater than the second maximum depth, is incorporated into the device of Kim (see, e.g., annotated figure 4).
PNG
media_image4.png
795
1888
media_image4.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Moore in the device of Kim to provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
Regarding Claim 3, Kim, in view of Moore, shows the semiconductor device of Claim 2,
wherein the implanted region 686 & 670 comprises
a first trench shielding region 670 (left portion of second portion 670) that is below the first gate trench section 668-1L,
a second trench shielding region 670 (right portion of second portion 670) that is below the second gate trench section 668-1R
and a support shield 686 (first portion 686 becomes the support shield) that is at least partially in between the first gate trench section 668-1L and the second gate trench section 668-1R (see, e.g., annotated figure 5).
PNG
media_image5.png
795
1261
media_image5.png
Greyscale
Regarding Claim 11, Kim (see, e.g., fig. 11), in view of Moore, shows the semiconductor device of Claim 3,
wherein the first gate trench section 668-1L is part of a first gate trench (668-1L is now considered a first gate trench, hereinafter “1G”),
the second gate trench section 668-1R is part of a second gate trench (668-1R is now considered a second gate trench, hereinafter “2G”,
where the second gate trench 2G is spaced apart from the first gate trench 1G and extends in parallel to the first gate trench (all gates 668-1 extend parallel to each other in a vertical direction, therefore the gate trenches 2G and 1G extend in parallel, see, e.g., fig. 11).
Claims 4, 12 & 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998) in view of Moore (US 20230032610) and further in view of Suzuki (US 20090114969).
Regarding Claim 4, Kim, in view of Moore, shows the semiconductor device of Claim 3,
Kim, in view of Moore, however, fails to show
wherein an upper portion of the drift region comprises
a JFET region that has a higher concentration of first conductivity type dopants than a lower portion of the drift region,
and the support shield extends downwardly through the JFET region into the lower portion of the drift region,
wherein the first trench shielding region and the second trench shielding region do not extend through the JFET region into the lower portion of the drift region.
Suzuki (see, e.g., fig. 9, para.0087-0089), in a similar device to Kim, in view of Moore, teaches
wherein an upper portion 50 of the drift region 50 & 2 comprises
a JFET region 50 that has a higher concentration of first conductivity type dopants (n+ type, see, e.g., para.0087) than a lower portion 2 of the drift region (n- type, see, e.g., para.0088),
Suzuki teaches the JFET region 50 surrounding the gate trench would lower on resistance of the semiconductor device.
The configuration of the drift region 50 & 2 including the JFET region of Suzuki is incorporated into the device of Kim, in view of Moore. Kim, in view of Moore and further in view of Suzuki teaches
wherein an upper portion of the drift region 620 & 50 comprises
a JFET region 50 that has a higher concentration of first conductivity type dopants than a lower portion 620 of the drift region,
and the support shield 686 extends downwardly through the JFET region 50 into the lower portion 620 of the drift region,
wherein the first trench shielding region 670 (left portion of 670) and the second trench shielding region 670 (right portion of 670) do not extend through the JFET region into the lower portion of the drift region (see, e.g., annotated figure 6).
PNG
media_image6.png
924
1590
media_image6.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the JFET region of Suzuki in the device of Kim, in view of Moore, to lower on resistance of the semiconductor device.
Regarding Claim 12, Kim, in view of Moore, shows the semiconductor device of Claim 11, further comprising:
a third gate trench (formed of another gate trench 668-1, hereinafter “3G”) extending into the semiconductor layer structure,
where the first and third gate trenches 1G & 3G are the closest gate trenches to the second gate trench 2G (see, e.g., annotated figure 7),
wherein the support shield 686 is a first support shield (support shield 686 is now considered a first support shield, hereinafter “686A”)
PNG
media_image7.png
795
1253
media_image7.png
Greyscale
Kim, in view of Moore, however, fails to show
and the semiconductor layer structure further comprises a second support shield having the second conductivity type in between the second gate trench and the third gate trench.
Suzuki (see, e.g., fig. 7, para.0082-0083), in a similar device to Kim, in view of Moore, teaches a configuration wherein a plurality of support shields 40 underneath gate trench 6 & 7 and underneath well region 8 & 9. Suzuki states the configuration of support shields 40 would further reduce electric fields beneath the gate trench and alleviate electric fields of the depletion regions.
The configuration of the plurality of support shields underneath gate trenches and well regions of Suzuki is incorporated into the device of Kim, in view of Moore. Kim, in view of Moore and further in view of Suzuki teaches
and the semiconductor layer structure further comprises a second support shield 670 (now formed underneath well region 632 as modified by Suzuki, hereinafter “670B”) having the second conductivity type (p-type, see, e.g., para.0282) in between the second gate trench 2G and the third gate trench 3G (see, e.g., annotated figure 8).
PNG
media_image8.png
792
1590
media_image8.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Suzuki in the device of Kim, in view of Moore, to further reduce electric fields beneath the gate trenches and alleviate electric fields of the depletion regions.
Regarding Claim 13, Kim, in view of Moore and further in view of Suzuki, shows the semiconductor device of Claim 12,
wherein a minimum distance between the second gate trench 2G and the second support shield 670B is greater than a minimum distance between the second gate trench 2G and the first support shield 686a (see, e.g., annotated figure 9).
PNG
media_image9.png
792
1590
media_image9.png
Greyscale
Claim 50 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998) in view of Ngwendson (US 20220320295).
Regarding Claim 50, Kim shows the semiconductor device of Claim 1,
Kim, however, fails to show
wherein the source metallization directly contacts both sidewalls of the source region.
Ngwendson (see, e.g., fig. 1, para.0064, para.0072), in a similar device to Kim, shows
wherein the source metallization 112 directly contacts sidewalls of the source region 110.
The configuration of Ngwendson is incorporated into the device of Kim, because the combination is a simple substitution of one known configuration of a source metallization and source region of a semiconductor device for another. Kim, in view of Ngwendson teaches
wherein the source metallization 680 directly contacts both sidewalls of the source region 642 (see, e.g., annotated figure 10).
PNG
media_image10.png
790
1508
media_image10.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of the source metallization and source region of Ngwendson in the device of Kim because the combination is a simple substitution of one known configuration for another to obtain predictable results – simple substitution of one known configuration of a source metallization and source region of a semiconductor device for another.
Claim 18 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 20220130998).
Regarding Claim 18, Kim (see, e.g., fig. 11) shows a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 650, 620, 632, 642, 686 (all elements are made of silicon carbide, see, e.g., para.0280-0282) that comprises
a drift region 620 having a first conductivity type (n-type, see, e.g., para.0280),
a well region 632 having a second conductivity type (p-type, see, e.g., para.0280) on the drift region,
a source region 642 having the first conductivity type (n-type, see, e.g., para.0280) on the well region,
and a plurality of support shield shields 686 & 670 having the second conductivity type (p-type, see, e.g., para.0281-282, see, e.g., fig. 11);
and a plurality of gate trenches 668-1 (see, e.g., para.0281) in the semiconductor layer structure,
where an inner sidewall 663 (sidewall of the dielectric layer 663 of the gate trench 668-1, see, e.g., para.0283) of every gate trench in the semiconductor device surrounds an upper portion 686 (upper portion of 686 near contact with source 680) of a respective one of the support shields 686 & 670,
wherein each support shield 686 & 670 extends deeper into the semiconductor layer structure than does the well region 632 (see, e.g., fig. 11).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998) in view of Moore (US 20230032610).
Regarding Claim 19, Kim shows the semiconductor device of Claim 18,
wherein the silicon carbide semiconductor layer structure further comprises
a first trench shielding region 670 having a second conductivity type (p-type see, e.g., para.0281) in the drift region,
Kim, however fails to show
and wherein a maximum depth of the support shield into the semiconductor layer structure is greater than a maximum depth of the first trench shielding region into the semiconductor layer structure.
Moore (see, e.g., fig. 7, para.0045-0047), in a similar device to Kim, teaches
and wherein a maximum depth (hereinafter “D3”) of the support shield 52 into the semiconductor layer structure is greater than a maximum depth (hereinafter “D4”) of the first trench shielding region 52 (under left gate 12) into the semiconductor layer structure (see, e.g., annotated figure 11)
Moore (see, e.g., para.0046-0047) states the configuration of the maximum depth D3 greater than the maximum depth D4 would provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
The configuration of Moore, the maximum depth D3 greater than the maximum depth D4, is incorporated into the device of Kim (see, e.g., annotated figure 11).
PNG
media_image11.png
787
1869
media_image11.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Moore in the device of Kim to provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
Claims 34, 35, & 38 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 20220130998).
Regarding Claim 34, Kim (see, e.g., fig. 11) shows a semiconductor device, comprising:
a silicon carbide based semiconductor layer structure 650, 620, 632, 642, 686 (all elements are made of silicon carbide, see, e.g., para.0280-0282) that comprises
a drift region 620 having a first conductivity type (n-type, see, e.g., para.0280),
a well region 632 having a second conductivity type (p-type, see, e.g., para.0280) on the drift region 620,
and a source region 642 having the first conductivity type (n-type, see, e.g., para.0280) on the well region 632;
a first gate trench section 668-1 (hereinafter “668-1A”, see, e.g., para.0281) and a second gate trench section 668-1 (hereinafter “668-1B”) in the semiconductor layer structure that form a first pair of gate trench sections (hereinafter “668-1AB”, see, e.g., annotated figure 12,
where the first gate trench section is adjacent the second gate trench section;
a third gate trench section 668-1 (hereinafter “668-1C”) and a fourth gate trench section 668-1 (hereinafter “668-1D”) in the semiconductor layer structure that form a second pair of gate trench sections (hereinafter “668-1CD”, see, e.g., annotated figure 12,
the second pair of gate trench sections adjacent the first pair of gate trench sections,
where the third gate trench section is adjacent the fourth gate trench section;
wherein the semiconductor layer structure further comprises
a first support shield 686 (in the middle of the 668-1AB, hereinafter “1S”, see, e.g., para.0282) having the second conductivity type (p-type, see, e.g., para.0281-0282) in the semiconductor layer structure,
an upper portion (upper portion of 686 near source 680) of the first support shield in between the first gate trench section 668-1A and the second gate trench section 668-1B,
a second support shield 686 (in the middle of the 668-1CD, hereinafter “2S”) having the second conductivity type (p-type, see, e.g., para.0281-0282) in the semiconductor layer structure,
an upper portion (upper portion of 686 near source 680) of the second support shield in between the third gate trench section 668-1C and the fourth gate trench section 668-1D,
and a third support shield 686 & 670 (hereinafter “3S”, see, e.g., para.0282) having the second conductivity type (p-type, see, e.g., para.0281-0282) in the semiconductor layer structure in between the first pair of gate trench sections 668-1AB and the second pair of gate trench sections 668-1CD,
each of the first through third support shields extending deeper into the semiconductor layer structure than the well region 632 (see, e.g., fig. 11),
wherein an upper surface of the third support shield (top surface of 670 of third support shield 3S) is above a lower portion of the well region 632 (the limitation “upper surface” does not limit the surface to a “topmost” surface and therefore the top surface of 670 is still considered an upper surface of the third support shield, see, e.g., annotated figure 12).
PNG
media_image12.png
921
1678
media_image12.png
Greyscale
Regarding Claim 35, Kim (see, e.g., fig. 11) shows the semiconductor device of Claim 34,
wherein the semiconductor layer structure further comprises
a first trench shielding region 670 (left half of 670, see, e.g., para.0281) having the second conductivity type underneath the first gate trench 668-1A
and a second trench shielding region 670 (right half of 670, see, e.g., para.0281) having the second conductivity type underneath the second gate trench 668-1B,
and the first support shield 1S (686) merges into the first and second trench shielding regions (direct physical contact between all elements is interpreted to merge into one element, see, e.g., fig. 11).
Regarding Claim 38, Kim shows the semiconductor device of Claim 34,
wherein the first support shield 1S (686 in the middle of 668-1AB) forms a first sidewall (right sidewall of 668-1A) of the first gate trench and a first sidewall (left sidewall of 668-1B) of the second gate trench (the first support shield forms first sidewalls of 668-1A & 668-1B by being in the middle of the two trench sections, see, e.g., annotated figure 12).
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 20220130998) in view of Moore (US 20230032610).
Regarding Claim 36, Kim shows the semiconductor device of Claim 35,
Kim, however, fails to show
wherein a maximum depth of the first support shield exceeds a maximum depth of the first trench shielding region.
Moore (see, e.g., fig. 7, para.0045-0047), in a similar device to Kim, teaches
and wherein a maximum depth (hereinafter “D3”) of the support shield 52 into the semiconductor layer structure is greater than a maximum depth (hereinafter “D4”) of the first trench shielding region 52 (under left gate 12) into the semiconductor layer structure (see, e.g., annotated figure 11)
Moore (see, e.g., para.0046-0047) states the configuration of the maximum depth D3 greater than the maximum depth D4 would provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
The configuration of Moore, the maximum depth D3 greater than the maximum depth D4, is incorporated into the device of Kim (see, e.g., annotated figure 13).
PNG
media_image13.png
921
2039
media_image13.png
Greyscale
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Moore in the device of Kim to provide uniform implanted p-type charge between the bottom of the gate trench regions and the p-n junction, provide consistent performance, and prevent the depletion region from spreading to unwanted portions of the semiconductor device.
Response to Arguments
Applicant’s arguments, see page 7, filed 05/27/2026, with respect to the objection to Claim 26 and the rejections of Claims 12 & 34 under 35 U.S.C. 112 have been fully considered and are persuasive. The objection to Claim 26 and the rejections of Claims 12 & 34 under 35 U.S.C. 112 have been withdrawn.
Applicant’s arguments with respect to claim(s) 1-4, 9, 11-16, 18-19, 26-31, 34-36, & 38 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/F.R.D./ Examiner, Art Unit 2818
Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights