Prosecution Insights
Last updated: August 18, 2026
Application No. 18/493,949

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH CONDUCTIVE CONTACT

Final Rejection §103
Filed
Oct 25, 2023
Examiner
SABUR, ALIA
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
443 granted / 596 resolved
+6.3% vs TC avg
Moderate +6% lift
Without
With
+6.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
48 currently pending
Career history
633
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
61.4%
+21.4% vs TC avg
§102
13.4%
-26.6% vs TC avg
§112
18.8%
-21.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 596 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 11-13 and 15 rejected under 35 U.S.C. 103 as being unpatentable over Hsieh (U.S. PGPub 2018/0158727) in view of Kim 738 (U.S. PGPub 2022/0246738). Regarding claim 11, Hsieh teaches a method for forming a semiconductor device structure, comprising: forming an epitaxial structure beside a channel structure (Fig. 3E, 320, [0033], 310, [0017]); forming a dielectric layer surrounding and covering the epitaxial structure (Fig. 3F, 340, [0037]); partially removing the dielectric layer to form a contact opening exposing the epitaxial structure (Fig. 3K, 353, [0040]); forming a protective structure over sidewalls of the contact opening, wherein the protective structure has an inner portion and an outer portion, the inner portion is between the outer portion and the dielectric layer, and the outer portion has a higher atomic concentration of nitrogen than that of the inner portion (Fig. 3K-3L, 360/370, [0041]-[0042], same materials as 160/170; [0027] 160 may be silicon oxide, [0028] 170 may be silicon nitride); forming a metal-semiconductor compound feature on the epitaxial structure after the protective structure is formed (Fig. 3P, 380, [0044]), and forming a conductive contact filling the contact opening (Fig. 3P, 390, [0045]). Hsieh does not explicitly teach wherein an interface between the conductive contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure. Kim 738 teaches a protective structure comprising a first protective layer and second protective layer on a contact opening to an epitaxial source/drain region (Fig. 2C, 160, [0062], [0034]), and forming a metal-semiconductor compound feature on the epitaxial source/drain region after the protective structure is formed (Figs. 11I-11J, 152, [0037]), wherein an interface between the contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure (Fig. 2C). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim 738 with Hsieh such that an interface between the conductive contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A. Regarding claim 12, the combination of Hsieh and Kim 738 teaches wherein the metal-semiconductor compound feature is between the conductive contact and the epitaxial structure (Hsieh, Fig. 3P; Kim 738, Fig. 2). Regarding claim 13, the combination of Hsieh and Kim 738 teaches wherein the metal-semiconductor compound feature is formed before the conductive contact is formed (Hsieh, Fig. 3O-3P, 380, [0044]). Regarding claim 15, the combination of Hsieh and Kim 738 teaches wherein the inner portion of the protective structure has a lower dielectric constant than that of the outer portion of the protective structure (Hsieh, [0041]-[0042], same materials as 160/170; [0027] 160 may be silicon oxide, [0028] 170 may be silicon nitride; silicon oxide has lower dielectric constant). Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2022/0028994) in view of Hsieh (U.S. PGPub 2018/0158727) and Kim 738 (U.S. PGPub 2022/0246738). Regarding claim 1, Chen teaches a method for forming a semiconductor device structure, comprising: forming a metal gate stack wrapped around a plurality of semiconductor nanostructures, wherein the semiconductor nanostructures are adjacent to an epitaxial structure (Fig. 21C, 54/55, [0043]; 102, [0078]; 92, [0066]); forming a dielectric layer over the metal gate stack and the epitaxial structure (106, [0084]); partially removing the dielectric layer to form a contact opening exposing the epitaxial structure (Fig. 22B, [0085]); forming a metal-semiconductor compound feature on the epitaxial structure after the second protective layer is formed (Fig. 23C, [0086]-[0087]) and forming a conductive contact over the epitaxial layer to fill the contact opening (Fig. 23B, 112, [0087]). Chen does not explicitly teach forming a first protective layer over sidewalls of the contact opening; forming a second protective layer over the first protective layer, wherein the first protective layer has a lower dielectric constant than that of the second protective layer; and forming the conductive contact over the second protective layer. Hsieh teaches a method for forming a semiconductor device structure, comprising a metal gate stack over a semiconductor structure adjacent to an epitaxial structure (Fig. 3I, 322, 320, [0033], [0035]); forming a dielectric layer over the metal gate stack and the epitaxial structure (352, [0039]), partially removing the dielectric layer to form a contact opening exposing the epitaxial structure (Fig. 3J, 353, [0040]), forming a first protective layer over sidewalls of the contact opening (Fig. 3K, 360, [0041]), forming a second protective layer over the first protective layer (Fig. 3L, 370, [0042]), wherein the first protective layer has a lower dielectric constant than that of the second protective layer ([0041]-[0042], 360/370 same materials as 160/170; [0027] 160 may be silicon oxide, [0028] 170 may be silicon nitride; SiN has higher dielectric constant); forming a metal-semiconductor compound feature on the epitaxial structure after the protective structure is formed (Fig. 3P, 380, [0044]); and forming a conductive contact over the second protective layer and the epitaxial layer to fill the contact opening (390, [0045]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Hsieh with Chen such that the method comprises forming a first protective layer over sidewalls of the contact opening; forming a second protective layer over the first protective layer, wherein the first protective layer has a lower dielectric constant than that of the second protective layer; and forming the conductive contact over the second protective layer for the purpose of protecting the metal gate during cleaning (Hsieh, [0043]). Chen does not explicitly teach wherein an interface between the conductive contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure. Kim 738 teaches a protective structure comprising a first protective layer and second protective layer on a contact opening to an epitaxial source/drain region (Fig. 2C, 160, [0062], [0034]), and forming a metal-semiconductor compound feature on the epitaxial source/drain region after the protective structure is formed (Figs. 11I-11J, 152, [0037]), wherein an interface between the contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure (Fig. 2C). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Kim 738 with Chen such that an interface between the conductive contact and the inner portion of the protective structure is positioned above a topmost surface of the epitaxial structure because the prior art teaches every element, a person of ordinary skill could have combined them as claimed and in combination each element performs the same function as it does separately, and the combination would have yielded predictable results to one of ordinary skill in the art before the time of the invention. See MPEP 2143(I)A. Regarding claim 2, the combination of Chen, Hsieh, and Kim 738 teaches wherein the metal-semiconductor compound feature is between the conductive contact and the epitaxial structure (Chen, Fig. 23C, [0086]-[0087]; Hsieh, Fig. 3P, 380, [0044]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Regarding claim 3, the combination of Chen, Hsieh, and Kim 738 teaches cleaning an exposed surface of the epitaxial structure after the second protective layer is formed and before the metal-semiconductor compound feature is formed (Hsieh, Fig. 3M, [[0043]).It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Regarding claim 4, the combination of Chen, Hsieh, and Kim 738 teaches wherein the second protective layer is at least partially consumed during the cleaning of the exposed surface of the epitaxial structure (Hsieh, Fig. 3M, [[0043]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Regarding claim 5, the combination of Chen, Hsieh, and Kim 738 teaches wherein the second protective layer has a higher atomic concentration of nitrogen than that of the first protective layer (Hsieh, [0027]-[0028], silicon oxide/silicon nitride). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Regarding claim 7, the combination of Chen, Hsieh, and Kim 738 teaches forming a gate spacer over a sidewall of a dummy gate stack; and replacing the dummy gate stack with the metal gate stack, wherein the first protective layer is in direct contact with the gate spacer and the dielectric layer (Chen, Fig. 15E, 76, 81, [0055], [0071]; Figs. 18C-20C, [0076]-[0078]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Regarding claim 8, the combination of Chen, Hsieh, and Kim 738 teaches forming a second dielectric layer over the metal gate stack and the conductive contact; and forming a conductive via penetrating through the second dielectric layer and electrically connected to the conductive contact (Chen, Fig. 24C, 120, [0091]-[0094]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, and Kim 738 for the reasons set forth in the rejection of claim 1. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2022/0028994) in view of Hsieh (U.S. PGPub 2018/0158727), Kim 738 (U.S. PGPub 2022/0246738), and Wu (U.S. PGPub 2022/0262792). Regarding claim 6, the combination of Chen, Hsieh, and Kim 738 teaches wherein the first protective layer is 1.8 nm (Hsieh, [0027]) and is silent on the thickness of the second protective layer. Wu teaches wherein a silicon nitride protective layer in a contact opening for an epitaxial source/drain feature is 1-3 nm in thickness ([0058], Fig. 16B). In the case where the claimed ranges overlap or lie inside ranges disclosed by the prior art a prima facie case of obviousness exists. See MPEP 2144.05. Therefore it would have been obvious to a person having ordinary skill in the art to combine the teachings of Wu with Chen, Hsieh, and Kim 738 such that the first protective layer is thicker than the second protective layer for the purpose of choosing an appropriate known thickness for each layer from the pertinent art. Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (U.S. PGPub 2022/0028994) in view of Hsieh (U.S. PGPub 2018/0158727), Kim 738 (U.S. PGPub 2022/0246738), and Chen 468 (U.S. PGPub 2021/0098468). Regarding claim 9, the combination of Chen, Hsieh, and Kim 738does not explicitly teach forming a second dielectric layer over the metal gate stack and the dielectric layer; and partially removing the second dielectric layer and the first dielectric layer to form the contact opening. Chen 468 teaches a method for forming a semiconductor device structure, comprising a metal gate stack over a semiconductor structure adjacent to an epitaxial structure (Fig. 5, 222, 400, 212, [0049]-[0051]); forming a dielectric layer over the metal gate stack and the epitaxial structure (450, [0053]), forming a second dielectric layer over the metal stack and the dielectric layer (280, [0053]), and partially removing the dielectric layer and second dielectric layer to form a contact opening exposing the epitaxial structure (Fig. 8, 520). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Chen with Chen, Hsieh, and Kim 738such that the method comprises forming a second dielectric layer over the metal gate stack and the dielectric layer; and partially removing the second dielectric layer and the first dielectric layer to form the contact opening for the purpose of protecting the gate structures (Chen 468, [0053]). Regarding claim 10, the combination of Chen, Hsieh, Kim 738, and Chen 468 teaches forming a third dielectric layer over the second dielectric layer and the conductive contact; and forming a conductive via penetrating through the third dielectric layer and electrically connected to the conductive contact (Chen, Fig. 24C, 120, [0091]-[0094]). It would have been obvious to a person having ordinary skill in the art to further combine the teachings of Chen, Hsieh, Kim 738, and Chen 468 for the reasons set forth in the rejection of claim 9. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh (U.S. PGPub 2018/0158727) in view of Kim 738 (U.S. PGPub 2022/0246738) and Kim (U.S. PGPub 2016/0043197). Regarding claim 14, Hsieh teaches cleaning the epitaxial structure before the metal-semiconductor compound feature is formed (Fig. 3M, [0043]) but does not explicitly teach wherein the protective structure becomes thinner after the cleaning of the epitaxial structure. Wei teaches wherein a cleaning process on a silicon nitride barrier layer in a source/drain contact opening reduces the thickness of the barrier layer (Figs. 18-19, [0106]). Therefore it would have been obvious to a person having ordinary skill in the art before the time of the effective filing date to combine the teachings of Wei with Hsieh and Kim 738 such that the protective structure becomes thinner after the cleaning of the epitaxial structure for the purpose of increasing the size of the contact hole (Wei, [0106]). Allowable Subject Matter Claims 16 and 18-21 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claim 16, the prior art, alone or in combination, does not teach or suggest the limitation “wherein the first protective layer is spaced apart from the metal-semiconductor compound feature by the conductive contact” in combination with the rest of the claim limitations. The most relevant prior art has been cited in the rejections of independent claims 1 and 11. Claims 18-21 depend from and further limit claim 16 and are therefore correspondingly allowable. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALIA SABUR whose telephone number is (571)270-7219. The examiner can normally be reached M-F 9:30-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALIA SABUR/Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Oct 25, 2023
Application Filed
Feb 12, 2026
Non-Final Rejection mailed — §103
May 11, 2026
Response Filed
Jun 23, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
81%
With Interview (+6.5%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 596 resolved cases by this examiner. Grant probability derived from career allowance rate.

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