DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11-13, 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chiu et al. (US 2021/0343332 A1 hereinafter referred to as “Chiu”).
With respect to claim 1, Chiu discloses, in Figs.1-14, a memory cell, comprising: first and second active regions (308/756) each extending lengthwise along a first direction/(X-direction); first and second gate structures (310) each extending lengthwise along a second direction/(Y-direction) perpendicular to the first direction/(X-direction), wherein the first gate structure (310) engages the first active region (308) in forming a first transistor (PD-1 or PU-1), the second gate structure (310) engages the second active region (308) in forming a second transistor (PD-2 or PU-2), and the first and second transistors have a same conductivity type/(N-type or P-type) (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1); a second epitaxial feature (406) disposed on a source region of the second transistor (see Par.[0032] wherein the various FinFETs are formed by a process including depositing a dielectric material layer on the semiconductor substrate, etching the dielectric material layer to form openings thereof, selective epitaxy growing a semiconductor material (such as silicon) on the semiconductor substrate within the openings to form fin active regions and STI features; see Par.[0035] wherein sources and drains (S/D) 406 are formed on the active regions 308, and a gate 310 is formed on the active region 308 and disposed between the corresponding source and drain 406); a first frontside contact (742) directly above and in electrical coupling with the first epitaxial feature; a second frontside contact directly above and in electrical coupling with the second epitaxial feature (406) (see Par.[0053] wherein the frontside contact features 740 may further include silicide features 742 formed on the source/drain features 406 to reduce contact resistance); and a first backside via (750) directly under and in electrical coupling with one of the first and second epitaxial features (406), wherein another one of the first and second epitaxial features (406) is free of a backside via directly thereunder and in electrical coupling therewith (see Par.[0054]-[0055] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310); see Fig.10A, wherein certain S/D features are free of via).
With respect to claim 2, Chiu discloses, in Figs.1-14, the memory cell, wherein the first transistor is a first pull-down transistor (PD-1) of the memory cell, and the second transistor is a second pull-down transistor (PD-2) of the memory cell (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1).
With respect to claim 3, Chiu discloses, in Figs.1-14, the memory cell, wherein the first and second transistors (PD-1, PD-2) are p-type transistors, the third transistor (PD-1) is an n-type transistor, the first backside via (750) electrically couples to a power supply of the memory cell, and the second backside via electrically couples to an electrical ground (VSS) of the memory cell (see Par.[0042]-[0043] wherein the sources of the PU-1 and PU-2 are connected to a first power line Vdd with a higher voltage; the sources of the PD-1 and PD-2 are connected to a second power line Vss with a lower voltage (e.g., a grounding line)).
With respect to claim 4, Chiu discloses, in Figs.1-14, the memory cell, wherein the first transistor (PU-1) is a first pull-up transistor of the memory cell, and the second transistor (PU-2) is a second pull-up transistor of the memory cell (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104).
With respect to claim 5, Chiu discloses, in Figs.1-14, the memory cell, wherein the first backside via electrically couples to a power supply of the memory cell (see Par.[0042]-[0043] wherein the sources of the PU-1 and PU-2 are connected to a first power line Vdd with a higher voltage; the sources of the PD-1 and PD-2 are connected to a second power line Vss with a lower voltage (e.g., a grounding line); the drains of the PG-1 and PG-2 are connected to a bit-line (BL) and a complimentary bit-line (BLB), respectively).
With respect to claim 6, Chiu discloses, in Figs.1-14, the memory cell, further comprising: a third active region (308) extending lengthwise along the first direction/(X-direction), wherein the first gate structure (310) engages the third active region in forming a third transistor (PG-1), and the third transistor has a different conductivity type from the first and second transistors; a third epitaxial feature disposed on a source region of the third transistor; and a second backside via directly under and in electrical coupling with the third epitaxial feature.
With respect to claim 7, Chiu discloses, in Figs.1-14, the memory cell, wherein the first and second transistors are n-type transistors, the third transistor is a p-type transistor, the first backside via electrically couples to an electrical ground of the memory cell, and the second backside via electrically couples to a power supply of the memory cell (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1); see Par.[0042]-[0043] wherein the sources of the PU-1 and PU-2 are connected to a first power line Vdd with a higher voltage; the sources of the PD-1 and PD-2 are connected to a second power line Vss with a lower voltage (e.g., a grounding line); the drains of the PG-1 and PG-2 are connected to a bit-line (BL) and a complimentary bit-line (BLB), respectively).
With respect to claim 8, Chiu discloses, in Figs.1-14, the memory cell, wherein the first and second transistors are p-type transistors, the third transistor is an n-type transistor, the first backside via electrically couples to a power supply of the memory cell, and the second backside via electrically couples to an electrical ground of the memory cell (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1); see Par.[0042]-[0043] wherein the sources of the PU-1 and PU-2 are connected to a first power line Vdd with a higher voltage; the sources of the PD-1 and PD-2 are connected to a second power line Vss with a lower voltage (e.g., a grounding line); the drains of the PG-1 and PG-2 are connected to a bit-line (BL) and a complimentary bit-line (BLB), respectively).
With respect to claim 9, Chiu discloses, in Figs.1-14, the memory cell, further comprising: first and second frontside metal lines (704/744) each extending lengthwise along the first direction/(X-direction); a first frontside contact via (740) disposed vertically between the first frontside contact and the first frontside metal line and electrically connecting the first frontside contact to the first frontside metal line; a second frontside contact via disposed vertically between the second frontside contact and the second frontside metal line and electrically connecting the second frontside contact to the second frontside metal line; and a first backside metal line extending lengthwise along the first direction and in physical contact with the first backside via (see Par.[0053] wherein the frontside interconnect structure 704 includes frontside contact features 740 formed on the frontside ILD layer 744, vias and metal lines disposed the frontside and configured to connect gate stacks 310 and some source/drain features 406).
With respect to claim 11, Chiu discloses, in Figs.1-14, a semiconductor structure, comprising: first and second active regions (308/756) extending lengthwise along a first direction/(x-direction); a gate stack (310) extending lengthwise along a second direction/(y-direction) perpendicular to the first direction (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1); a dielectric feature (758) extending lengthwise along the first direction and disposed between the first and second active regions (308), wherein the dielectric feature divides the gate stack into a first segment over the first active region and a second segment over the second active region (see Par.[0054] wherein the integrated circuit structure 100 may include other features, such as a dielectric layer 758 for isolation); a first epitaxial feature (406) disposed on the first active region; a second epitaxial feature (406) disposed on the second active region, wherein the first and second epitaxial features are disposed on two opposing sides of the dielectric feature; a frontside conductive feature directly above and in physical contact with top surfaces of the first and second epitaxial features (see Par.[0032] wherein the various FinFETs are formed by a process including depositing a dielectric material layer on the semiconductor substrate, etching the dielectric material layer to form openings thereof, selective epitaxy growing a semiconductor material (such as silicon) on the semiconductor substrate within the openings to form fin active regions and STI features; see Par.[0035] wherein sources and drains (S/D) 406 are formed on the active regions 308, and a gate 310 is formed on the active region 308 and disposed between the corresponding source and drain 406); a backside conductive feature (750) directly under and in physical contact with a bottom surface of the first epitaxial feature (406) (see Par.[0054]-[0055] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310); see Fig.10A, wherein certain S/D features are free of via); and a semiconductor base (702) directly under and in physical contact with a bottom surface of the second epitaxial feature (see Par.[0045] wherein the integrated circuit structure 100 further includes a frontside interconnect structure 704 formed on the frontside of the substrate 702 and a backside interconnect structure 706 formed on the backside of the substrate 702).
With respect to claim 12, Chiu discloses, in Figs.1-14, the semiconductor structure, wherein each of the frontside conductive feature (740) and the backside conductive feature (750) electrically couples to an electrical ground (VSS) of the semiconductor structure (see Par.[0042]-[0043] wherein the sources of the PU-1 and PU-2 are connected to a first power line Vdd with a higher voltage; the sources of the PD-1 and PD-2 are connected to a second power line Vss with a lower voltage (e.g., a grounding line)).
With respect to claim 13, Chiu discloses, in Figs.1-14, the semiconductor structure, further comprising: a frontside via (712A) landing on the frontside conductive feature; a frontside metal line (714A) directly above and in physical contact with the frontside via; and a backside metal line (722) directly under and in physical contact with the backside conductive feature (see Par.[0049] wherein the second cell 104B includes metal lines (722A2 and 722B2) and corresponding contact features for the BLB and Vss (associated with PG-1) and the metal lines 714B2, 714A2 and 714C2 and corresponding contact features for the BL, Vss (associated with PG-2), and Vdd).
With respect to claim 15, Chiu discloses, in Figs.1-14, the semiconductor structure, wherein the first segment of the gate stack and the first active region form a pull-down transistor of a first memory cell, and the second segment of the gate stack and the second active region form a pull-down transistor of a second memory cell abutting the first memory cell (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first epitaxial feature (406) disposed on a source region of the first transistor (PU-1).
With respect to claim 16, Chiu discloses, in Figs.1-14, a memory array, comprising: a first memory cell and a second memory cell abutting the first memory cell, wherein the first memory cell includes a first pull-up transistor (PU-1) and a first pull-down transistor (PD-1), and the second memory cell includes a second pull-up transistor (PU-2) and a second pull-down transistor (PD-2); a third memory cell and a fourth memory cell abutting the third memory cell, wherein the third memory cell abuts the first memory cell, the fourth memory cell abuts the second memory cell, the third memory cell includes a third pull-up transistor (PU-1) and a third pull-down transistor (PD-1), and the fourth memory cell includes a fourth pull-up transistor and a fourth pull-down transistor (see Par.[0033] wherein the gates 310 of the FETs are formed on the active regions 308 and oriented along the Y direction; especially, some active regions 308 extend from the n-well 302 to the adjacent p-well (such as 304 or 306) such that corresponding FETs (such as PU-1 and PD-1, or PU-2 and PD-2) share a common gate; the gate 310 over both n-well 302 and p-well 304 is associated with a pFET for the first pull-up device (PU-1) in the n-well 302 and an nFET for the first pull-down device (PD-1) in the p-well 304; the gate 310 over both n-well 302 and p-well 306 is associated with a pFET for the second pull-up device (PU-2) in the n-well 302 and a nFET for the second pull-down device (PD-2) in the p-well 306; see Par.[0053] wherein the integrated circuit structure 100 includes a substrate 702 with various devices formed thereon, a frontside interconnect structure 704, and a backside interconnect structure 706; the substrate 702 includes an active region 736, source/drain features 406, and gate stacks 310 configured to form various FETs, such as pull-up devices, pull-down devices, and pass-gate devices of the SRAM bit cells 104); a first common source region (406) of the first and second pull-up transistors; a second common source region (406) of the first and second pull-down transistors; a third common source region (406) of the third and fourth pull-down transistors; a fourth common source region of the third and fourth pull-up transistors (see Par.[0032] wherein the various FinFETs are formed by a process including depositing a dielectric material layer on the semiconductor substrate, etching the dielectric material layer to form openings thereof, selective epitaxy growing a semiconductor material (such as silicon) on the semiconductor substrate within the openings to form fin active regions and STI features; see Par.[0035] wherein sources and drains (S/D) 406 are formed on the active regions 308, and a gate 310 is formed on the active region 308 and disposed between the corresponding source and drain 406); a backside conductive feature (750) directly under and in physical contact with a bottom surface of the first epitaxial feature (406) (see Par.[0054]-[0055] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310); see Fig.10A, wherein certain S/D features are free of via); and a plurality of source region backside vias (750), wherein each of the source region backside vias is directly under one of the first, second, third, and fourth common source regions, and at least one of the first, second, third, and fourth common source regions is free of a source region backside via disposed directly thereunder (see Par.[0045] wherein the integrated circuit structure 100 further includes a frontside interconnect structure 704 formed on the frontside of the substrate 702 and a backside interconnect structure 706 formed on the backside of the substrate 702; see Par.[0054]-[0055] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310); see Fig.10A, wherein certain S/D features are free of via; see Par.[0033] wherein the n-well 302 may have an elongated shape oriented in the X direction and may extend along the X direction over multiple SRAM bit cells; the integrated circuit 100 includes a first p-type doped well (p-well) 304 and a second p-well 306 formed in sides of the n-well 302, each with elongated shape oriented in the X direction; the p-wells 304 and 306 may extends along the X direction over multiple SRAM bit cells as well).
With respect to claim 17, Chiu discloses, in Figs.1-14, the memory array, wherein the plurality of source region backside vias (750) are directly under the second and third common source regions, and each of the first and fourth common source regions is free of a source region backside vias disposed directly thereunder (see Par.[0054] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310)).
With respect to claim 18, Chiu discloses, in Figs.1-14, the memory array, wherein the plurality of source region backside vias are directly under the first and fourth common source regions, and each of the second and third common source regions is free of a source region backside via disposed directly thereunder (see Par.[0054] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310)).
With respect to claim 19, Chiu discloses, in Figs.1-14, the memory array, wherein the plurality of source region backside vias are directly under the first, second, and fourth common source regions, and the third common source region is free of a source region backside via disposed directly thereunder (see Par.[0054] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310)).
With respect to claim 20, Chiu discloses, in Figs.1-14, the memory array, wherein the plurality of source region backside vias are directly under the first, second, and third common source regions, and the fourth common source region is free of a source region backside via disposed directly thereunder (see Par.[0054] wherein the backside interconnect structure 706 includes backside contact features 750 formed on the backside ILD layer 754, metal lines 756, and vias (may further include metal lines on other metal layers) disposed the backside and configured to connect some source/drain features 406 (and may include some gate stacks 310)).
Claims 1, 9-11, 13-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2021/0028112 A1 hereinafter referred to as “Kim”).
With respect to claim 1, Kim discloses, in Figs.1-13C, a memory cell, comprising: first and second active regions (102/105) each extending lengthwise along a first direction/(Y-direction) (see Par.[0033] wherein the active region 102 adjacent to the plurality of active fins 105; the trench ST may be disposed between the plurality of active fins 105, and may extend in the first direction (e.g., the y direction), similar to the active fin 105 (See FIG. 1)); first and second gate structures (145) each extending lengthwise along a second direction/(X-direction) perpendicular to the first direction/(Y-direction), wherein the first gate structure (145) engages the first active region in forming a first transistor, the second gate structure engages the second active region in forming a second transistor, and the first and second transistors have a same conductivity type (see Par.[0026]-[0027] wherein the active region 102 may be an n-type well for a PMOS transistor or a p-type well for an NMOS transistor; see Par.[0058] wherein the gate structure GS used in this embodiment may include gate spacers 141, a gate dielectric film 142 and a gate electrode 145 sequentially arranged between the gate spacers 141, and a gate capping layer 147 disposed on the gate electrode 145); a first epitaxial feature (110) disposed on a source region of the first transistor; a second epitaxial feature disposed on a source region of the second transistor; a first frontside contact (185) directly above and in electrical coupling with the first epitaxial feature (110); a second frontside contact (185) directly above and in electrical coupling with the second epitaxial feature (see Par.[0027]-[0028] wherein the source/drain region 110 may form a recess in a portion of the active fin 105, and may perform a selective epitaxial growth (SEG) process on the recess, to have an upper surface higher than an upper surface of the active fin 105; this source/drain region 110 may be also referred to as a raised source/drain (RSD)); and a first backside via (125, 250) directly under and in electrical coupling with one of the first and second epitaxial features (110), wherein another one of the first and second epitaxial features (110) is free of a backside via directly thereunder and in electrical coupling therewith (see Par.[0055]-[0056] wherein the conductive material 125, 185, and 255 in the buried conductive wiring 120, the contact structure 180, and the conductive through structure 250 may include Cu, Co, Mo, Ru, W, or alloys thereof).
With respect to claim 9, Kim discloses, in Figs.1-13C, the memory cell, further comprising: first and second frontside metal lines (M1) each extending lengthwise along the first direction; a first frontside contact via (V1) disposed vertically between the first frontside contact (185) and the first frontside metal line (M1) and electrically connecting the first frontside contact (110) to the first frontside metal line (M1); a second frontside contact via (V1) disposed vertically between the second frontside contact (110) and the second frontside metal line (M1) and electrically connecting the second frontside contact to the second frontside metal line; and a first backside metal line (M2) extending lengthwise along the first direction and in physical contact with the first backside via (125, 250) (see Par.[0089] wherein a plurality of metal wirings M1, and a plurality of metal vias V1; see Par.[0051] wherein the first metal wiring M2 may be formed to be connected to the conductive through structure 250).
With respect to claim 10, Kim discloses, in Figs.1-13C, the memory cell, wherein the first backside metal line (M2) is wider than the first frontside metal line and the second frontside metal line (M1) (see Fig.2, wherein wider M2 and narrower M1 are shown).
With respect to claim 11, Kim discloses, in Figs.1-13C, a semiconductor structure, comprising: first and second active regions (105) extending lengthwise along a first direction/(y-direction) (see Par.[0033] wherein the active region 102 adjacent to the plurality of active fins 105; the trench ST may be disposed between the plurality of active fins 105, and may extend in the first direction (e.g., the y direction), similar to the active fin 105 (See FIG. 1)); a gate stack (145) extending lengthwise along a second direction/(x-direction) perpendicular to the first direction (see Par.[0026]-[0027] wherein the active region 102 may be an n-type well for a PMOS transistor or a p-type well for an NMOS transistor; see Par.[0058] wherein the gate structure GS used in this embodiment may include gate spacers 141, a gate dielectric film 142 and a gate electrode 145 sequentially arranged between the gate spacers 141, and a gate capping layer 147 disposed on the gate electrode 145); a dielectric feature (162a) extending lengthwise along the first direction and disposed between the first and second active regions, wherein the dielectric feature divides the gate stack (GS/145) into a first segment over the first active region and a second segment over the second active region (see Par.[0075] wherein the device isolation layer 162 may include a first isolation region 162a defining the active region 102, and a second isolation region 162b defining the active fin 105; the second isolation region 162b may be disposed on the upper surface of the active region 102; the active fin 105 may penetrate the second isolation region 162b, and a portion of the active fin 105 may protrude from the second isolation region 162b); a first epitaxial feature (110) disposed on the first active region (105); a second epitaxial feature (110) disposed on the second active region, wherein the first and second epitaxial features are disposed on two opposing sides of the dielectric feature (see Par.[0027]-[0028] wherein the source/drain region 110 may form a recess in a portion of the active fin 105, and may perform a selective epitaxial growth (SEG) process on the recess, to have an upper surface higher than an upper surface of the active fin 105; this source/drain region 110 may be also referred to as a raised source/drain (RSD)); a frontside conductive feature (185) directly above and in physical contact with top surfaces of the first and second epitaxial features (110) (see Par.[0055]-[0056] wherein the conductive material 125, 185, and 255 in the buried conductive wiring 120, the contact structure 180, and the conductive through structure 250 may include Cu, Co, Mo, Ru, W, or alloys thereof); a backside conductive feature (125, 250) directly under and in physical contact with a bottom surface of the first epitaxial feature (185); and a semiconductor base (101) directly under and in physical contact with a bottom surface of the second epitaxial feature (110) (see Par.[0025]-[0026] wherein the substrate 101 may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP; in another example, the substrate 101 may have a silicon-on-insulator (SOI) structure).
With respect to claim 13, Kim discloses, in Figs.1-13C, the semiconductor structure, further comprising: a frontside via (V1) landing on the frontside conductive feature (185); a frontside metal line (M1) directly above and in physical contact with the frontside via (V1); and a backside metal line (M2) directly under and in physical contact with the backside conductive feature (125, 250) (see Par.[0089] wherein a plurality of metal wirings M1, and a plurality of metal vias V1; see Par.[0051] wherein the first metal wiring M2 may be formed to be connected to the conductive through structure 250).
With respect to claim 14, Kim discloses, in Figs.1-13C, the semiconductor structure, wherein the backside metal line (M2) is wider than the frontside metal line (M1) (see Fig.2, wherein wider M2 and narrower M1 are shown).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818