DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I encompassing claims 1-12 in the reply filed on 04/01/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2019/0109045 A1 hereinafter referred to as “Xie”).
With respect to claim 1, Xie discloses, in Figs.3-12, a semiconductor structure, comprising: a first fin (103) extending in an X-direction/(horizontal direction) and a second fin (103) parallel to the first fin and distanced from the first fin in a Y-direction/(vertical direction) perpendicular to the X-direction, wherein each fin is formed with a first device area and a second device area aligned in the X-direction (see Fig.12, wherein isolation area between parallel aligned pair of pluralities of fins are shown; see Par.[0021] wherein a plurality of fins 103 have been formed in the substrate 102 using traditional manufacturing techniques, and the gates 106 have been formed across the fins 103; see Par.[0019]-[0025] wherein still referencing FIG. 3, prior to the formation of the final gate structures 108, epi semiconductor material 116 was formed on the exposed portions of the active regions 103 (or fins in the case of a FinFET device), i.e., in the source/drain regions of the devices, by performing an epitaxial growth process); an isolation region (121-122) disposed between the first fin (103) and the second fin (103) (see Par.[0026]-[0028] wherein a CMP process was performed to remove excess conductive materials using the gate caps 110 and the layer of insulating material 121 as a polish stop layer; another layer of insulating material 122 (e.g., silicon dioxide) was blanket deposited across the product 10 insulating material 122 (e.g., silicon dioxide) was blanket deposited across the product 100; an optional CMP process may be performed on the upper surface of the layer of insulating material 122 if desired); an isolation structure (142) disposed between the first device area and the second device area in each fin (103) (see Par.[0020], [0031]-[0034] wherein the present application specifically discusses only two illustrative examples of the novel gate contact etching structure 180 disclosed herein: a single diffusion break (SDB) isolation structure 142 and a gate contact etching post 143); and an isolation layer (104) disposed under the first fin (103) and the second fin (103), wherein the isolation region (121-122) contacts the isolation layer (104), the isolation structure (142) contacts the isolation layer (104), and the isolation region (121-122) contacts the isolation structure (142) to isolate the first fin (103) from the second fin (103) and to isolate the first device area from the second device area in each fin (see Par.[0022] wherein the CB gate contact structures 132 are positioned vertically above isolation material 104; see Fig.12 in its cross-sectional Y-Y wherein contact between isolation layer 104 with isolation region 121-122 and isolation structure 142 are shown).
With respect to claim 2, Xie discloses, in Figs.3-12, the semiconductor structure, wherein each device area comprises: a source feature (120) and a drain feature (120) over the respective fin (103)/(1-6); an active region (103) between the source feature (120) and the drain feature (120); and a gate structure (108) over the active region (103) (see Par.[0021] wherein the product 100 generally comprises a plurality of gates 106 (numbered 1-6 for ease of reference) for various transistor devices that are formed in and above a semiconductor substrate 102; Also depicted in the plan view are illustrative source/drain contact structures 120 (e.g., trench silicide structures) that are conductively coupled to the source/drain regions of the transistor devices. As will be described more fully below, a single diffusion break (SDB) will be formed through gate number 3; see Par.[0025] wherein still referencing FIG. 3, prior to the formation of the final gate structures 108, epi semiconductor material 116 was formed on the exposed portions of the active regions 103 (or fins in the case of a FinFET device), i.e., in the source/drain regions of the devices, by performing an epitaxial growth process).
Claims 1-10, 21-28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liaw (US 2023/0378190 A1) .
The applied reference has a common Assignee (i.e.; Taiwan Semiconductor Manufacturing Company, Ltd) with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to claim 1, Liaw discloses, in Figs.1A-7C, a semiconductor structure, comprising: a first fin (120) extending in an X-direction and a second fin (120) parallel to the first fin and distanced from the first fin in a Y-direction perpendicular to the X-direction, wherein each fin is formed with a first device area (410) and a second device area (420) aligned in the X-direction (see Par.[0030]-[0033] wherein the transistors may be planar transistors, fin field-effect transistor (FinFET) transistors, gate-all-around (GAA) transistors, nano-wire transistors, nano-sheet transistors, or a combination thereof; the GAA transistor 10 also includes one or more nanostructures 120 (dash lines) extending in an X-direction and vertically arranged (or stacked) in a Z-direction; more specifically, the nanostructures 120 are spaced from each other in the Z-direction; the nanostructures 120 may also be referred to as channels, channel layers, nanosheets, or nanowires); an isolation region (117) disposed between the first fin and the second fin (see Par.[0050]-[0052] wherein the STD cells may include logic devices, including but not limited to logic circuits such as inverters, NANDs, NORs, flip-flops, SACNs or a combination thereof; for the sake of providing an example, FIG. 5A shows the two logic cells 410 and 420 arranged in a row of the cell array, and the logic cell 410 is a NAND and the logic cell 420 an inverter; the isolation structures 117a and 117b are arranged in the boundary of the logic cell 410, and the isolation structures 117b and 117c are arranged in the boundary of the logic cell 420); an isolation structure (135, 104) disposed between the first device area (410) and the second device area (420) in each fin (see Par.[0061]-[0064] wherein the inter-layer dielectric (ILD) 135, and IMD 210, which are over (or at the front-side of) the P-type transistors P1 through P3 and the N-type transistors N1 through N3; see Par.[0040]-[0043] wherein isolation feature 104 is over the substrate 101 and under the gate dielectric layer 112, the gate electrode 110, and the gate spacers 114; the isolation feature 104 is used for isolating the GAA transistor 10 from other devices); and an isolation layer (305) disposed under the first fin and the second fin, wherein the isolation region (117) contacts the isolation layer (305), the isolation structure (135, 104) contacts the isolation layer (305), and the isolation region (117) contacts the isolation structure (135, 104) to isolate the first fin from the second fin and to isolate the first device area from the second device area in each fin (see Figs.6A-6D, Par.[0068]-[0070] wherein the dielectric 305 (shown in FIGS. 6A-6E), and the IMD 310 (shown in FIGS. 6A-6E), which are under (or at the back-side of) the P-type transistors P1 through P3 and the N-type transistors N1 through N3).
With respect to claim 2, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein each device area comprises: a source feature (118) and a drain feature (118) over the respective fin (see Par.[0039], [0061]-[0062] wherein the nanostructures 120 (dash lines) extends in an X-direction to connect two epitaxially-grown materials 118. Such the nanostructures 120 and the epitaxially-grown materials 118 connected continuously with each other may be collectively referred to as an active area; each source/drain feature 118 is shared by two adjacent gate structures; the source/drain features 118 may be also referred to as common source/drain features); an active region (105) between the source feature and the drain feature; and a gate structure (115) over the active region (105) (see Par.[0051]-[0057] wherein the semiconductor device 400 includes the active areas 105a and 105b; the active areas 105a and 105b extend in the X-direction and have a continuous rectangular shape in the top view; the semiconductor device 400 further includes the gate structures 115a through 115c and the isolation structures 117a through 117c extending in the Y-direction; the gate structures 115a through 115c engage the active area 105a to form the N-type transistors N1 and N2 of the logic cell 410 and the N-type transistor N3 of the logic cell 420).
With respect to claim 3, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising: an active backside via (B_V0, B_V1) in contact with the source feature (118) in each device area; and a backside interconnect structure (300/310) disposed under each fin and adjacent to the isolation layer (305), wherein each active backside via (B_V) contacts the backside interconnect structure (300) (see Par.[0041]-[0043] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 4, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising: a frontside interconnect structure (200) disposed over the source feature (118), the drain feature (118), and the gate structure of each device area (see Par.[0041]-[0043] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 5, Liaw discloses, in Figs.1A-7C, a semiconductor structure, comprising: a first device area (410) and a second device area (420) adjacent to the first device area, wherein each device area comprises: a semiconductor substrate (101) (see Par.[0031] wherein referring to FIG. 3, a perspective view of an exemplary GAA transistor 10 is illustrated; the GAA transistor 10 includes a substrate 101; see Par.[0046] wherein the formation of the back-side interconnect structure 300 may include removing the substrate (if present) in a CMP process, forming a back-side dielectric layer (not shown) under the device region 100, and forming back-side contacts (not shown) connected to the source features in the device region 100 in the back-side dielectric layer); a source feature (118) and a drain feature (118) over the semiconductor substrate (101); an active region between the source feature (118) and the drain feature (118) (see Par.[0039] wherein the nanostructures 120 and the epitaxially-grown materials 118 connected continuously with each other may be collectively referred to as an active area); and a gate structure (115) over the active region (see Par.[0040] wherein isolation feature 104 is over the substrate 101 and under the gate dielectric layer 112, the gate electrode 110, and the gate spacers 114); an isolation structure (117, 303, 315, 320, 325, 330) disposed between the semiconductor substrate in the first device area (410) and the semiconductor substrate in the second device area (420); wherein each semiconductor substrate terminates at a backside, and wherein the isolation structure extends to the backside (see Par.[0051]-[0052] wherein the isolation structures 117a and 117b are arranged in the boundary of the logic cell 410, and the isolation structures 117b and 117c are arranged in the boundary of the logic cell 420; see Par.[0069]-[0071] wherein the back-side interconnect structure is under the device region or at the back side of the device region; referring to FIG. 5B, the back-side interconnect structure of the semiconductor device 400 includes the source/drain contacts 303a through 303e, the vias 315a through 315e, the metal lines 320a and 320b, the vias 325a and 325b, the metal line 330a and 330b, the dielectric 305 (shown in FIGS. 6A-6E), and the IMD 310 (shown in FIGS. 6A-6E), which are under (or at the back-side of) the P-type transistors P1 through P3 and the N-type transistors N1 through N3).
With respect to claim 6, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein the isolation structure is a dummy backside via (B_V) comprising a conductive core surrounded by a dielectric layer (310) (see Par.[0043]).
With respect to claim 7, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising: an isolation layer (305, 104) disposed under the backside of each semiconductor substrate, wherein the isolation structure (117) contacts the isolation layer (305) (see Par.[0061]-[0064] wherein the inter-layer dielectric (ILD) 135, and IMD 210, which are over (or at the front-side of) the P-type transistors P1 through P3 and the N-type transistors N1 through N3; see Par.[0040]-[0043] wherein isolation feature 104 is over the substrate 101 and under the gate dielectric layer 112, the gate electrode 110, and the gate spacers 114; the isolation feature 104 is used for isolating the GAA transistor 10 from other devices).
With respect to claim 8, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising: an active backside via (B_V) in contact with the source feature (118) in the first device area; and a backside interconnect structure (300/310) disposed under the backside of the semiconductor substrate (101) in the first device area and adjacent to the isolation layer (135, 104), wherein the active backside via contacts the backside interconnect structure (see Fig.6A).
With respect to claim 9, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein: each device area comprises a terminal active region (205); the semiconductor structure further comprises a dummy feature (207) disposed between the terminal active regions; and the isolation structure contacts the dummy feature (see Fig.5A, Par.[0063]-[0065] wherein the source/drain contacts 205a through 205d, the vias 215a through 215c and 225a through 225f, the gate vias 207a through 207c, the metal lines 220a through 220h and 230a through 230e, the ILD 135, and IMD 210 may also be referred to as the front-side drain contacts, the front-side vias, the front-side gate vias, the front-side metal lines, the front-side ILD, and the front-side IMD, respectively).
With respect to claim 10, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising: a frontside interconnect structure (210) disposed over the source feature, the drain feature, and the gate structure of each device area (see Par.[0042]-[0042] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD, the back-side vias, and the back-side metal lines, respectively; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 21, Liaw discloses, in Figs.1A-7C, a semiconductor structure, comprising: a first device area (410) and a second device area (420), wherein each device area comprises a semiconductor substrate (110), a source feature (118) over the semiconductor substrate, a drain feature (118) over the semiconductor substrate, an active region (105) between the source feature (118) and the drain feature (118), and a gate structure (115) over the active region (see Par.[0050]-[0052] wherein FIG. 5A shows the two logic cells 410 and 420 arranged in a row of the cell array, and the logic cell 410 is a NAND and the logic cell 420 an inverter; it should be understood that the logic cell 410 (including the NAND) and the logic cell 420 (including the inverter) are merely examples; see Par.[0038] wherein the epitaxially-grown materials 118 serve as the source/drain features of the GAA transistor 10; therefore, the epitaxially-grown materials 118 may also be referred to as source/drain, source/drain features, or source/drain nodes; see Par.[0051] wherein the semiconductor device 400 includes the active areas 105a and 105b; the active areas 105a and 105b extend in the X-direction and have a continuous rectangular shape in the top view); an isolation structure (117, 303, 315, 320, 325, 330) disposed between the semiconductor substrate in the first device area and the semiconductor substrate in the second device area, wherein each semiconductor substrate terminates at a backside and the isolation structure extends to the backside (see Par.[0051]-[0052] wherein the isolation structures 117a and 117b are arranged in the boundary of the logic cell 410, and the isolation structures 117b and 117c are arranged in the boundary of the logic cell 420; see Par.[0069]-[0071] wherein the back-side interconnect structure is under the device region or at the back side of the device region; referring to FIG. 5B, the back-side interconnect structure of the semiconductor device 400 includes the source/drain contacts 303a through 303e, the vias 315a through 315e, the metal lines 320a and 320b, the vias 325a and 325b, the metal line 330a and 330b, the dielectric 305 (shown in FIGS. 6A-6E), and the IMD 310 (shown in FIGS. 6A-6E), which are under (or at the back-side of) the P-type transistors P1 through P3 and the N-type transistors N1 through N3); an isolation layer (104, 305) disposed under the backside of each semiconductor substrate and contacting the isolation structure; a backside interconnect structure (310) disposed under the isolation layer (305, 104); and an active backside via (B_V) extending through the semiconductor substrate in the first device area and through the isolation layer to electrically connect the source feature in the first device area to the backside interconnect structure (see Par.[0041]-[0043] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 22, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein the isolation structure comprises a conductive core surrounded by a dielectric layer (310) (see Fig.6D).
With respect to claim 23, Liaw discloses, in Figs.1A-7C, the semiconductor structure, further comprising an outer isolation layer (104) disposed directly under the isolation layer (135) at a location of the isolation structure, wherein the dielectric layer of the isolation structure contacts the outer isolation layer and the outer isolation layer is disposed directly under the conductive core (see Fig.6D).
With respect to claim 24, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein a bottom surface of the active backside via, a bottom surface of the isolation structure, and a bottom surface of the isolation layer are coplanar/(at least in same cross-sectional plane) (see Par.[0041]-[0043] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 25, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein: the semiconductor substrate of the first device area comprises a first fin and the semiconductor substrate of the second device area comprises a second fin parallel to the first fin; no semiconductor material extends continuously between the first fin and the second fin; and the source feature in the first device area comprises P-doped epitaxial material and the source feature in the second device area comprises N-doped epitaxial material (see Par.[0038]-[0039] wherein the epitaxially-grown materials 118 may also be referred to as source/drain, source/drain features, or source/drain nodes. In some embodiments, for an N-type GAA transistor, the epitaxially-grown materials 118 may include SiP, SiC, SiPC, SiAs, Si, or a combination thereof. Furthermore, the Phosphorus (or Arsenic, or both) doping concentration of the source/drain features of the N-type GAA transistor about 2e19/cm.sup.−3 to about 3e21/cm.sup.−3. In some embodiments, for a P-type GAA transistor, the epitaxially-grown materials 118 may include SiGe, SiGeC, Ge, Si, a boron-doped SiGe, boron and carbon doped SiGe, or a combination thereof).
With respect to claim 26, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein: each device area comprises a terminal active region adjacent to the other device area; the semiconductor structure further comprises a dummy source/drain feature disposed between the terminal active regions; and the isolation structure contacts the dummy source/drain feature (see Fig.6D).
With respect to claim 27, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein the source feature comprises a highly doped region and the active backside via contacts the highly doped region (see Par.[0041]-[0043] wherein the back-side interconnect structure 300 is at the back side 104 of the device region 100, the IMD 310, the vias B_V0, B_V1, and the metal lines B_M1, B_M2 may also be referred to as the back-side IMD; the front-side interconnect structure 200 is at the front side 102 of the device region 100, the IMD 210, the vias F_VG, V0, V1, V2, and the metal lines M1, M2, M3 may also be referred to as the front-side IMD, the front-side vias, and the front-side metal lines, respectively).
With respect to claim 28, Liaw discloses, in Figs.1A-7C, the semiconductor structure, wherein the source feature further comprises a bottom structure disposed between the highly doped region and the semiconductor substrate (see Par.[0075] wherein for the exposed source/drain features 118 of the N-type transistors N1 through N3, extra doping is used to form the source/drain features 118, such as P31 or As, or Ge, or combination species doping; moreover, for the exposed source/drain features 118 of the P-type transistors P1 through P3, extra doping is used to form the source/drain features 118, such as B11, or BF2, or Ge, or combination species doping. In some embodiments, the extra doping species includes Ge implant for the source/drain features 118 of the P-type and N-type transistors).
Claims 5, 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2017/0358584 A1 hereinafter referred to as “Wang”).
With respect to claim 5, Wang discloses, in Figs.1-4B, a semiconductor structure, comprising: a first device area (220A) and a second device area (220B) adjacent to the first device area (320A), wherein each device area comprises: a semiconductor substrate (202) (see Par.[0016] wherein substrate 202 is a silicon on insulating layer (SOI) substrate, or a silicon on sapphire (SOS) substrate; substrate 202 includes a suitable elemental semiconductor, such as germanium or diamond; a suitable compound semiconductor, such as silicon carbide, gallium nitride, gallium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium, silicon tin, aluminum gallium arsenide, or gallium arsenide phosphide); a source feature (217) and a drain feature (218) over the semiconductor substrate (202) (see Par.[0027]-[0028] wherein dummy gate structure 210A is a gate terminal of a first transistor 220A; and conductive features 217A and 218A are source/drain terminals of the first transistor 220A); an active region (206A, 206B) between the source feature (217) and the drain feature (218) (see Par.[0017]-[0018] wherein active region 206 includes a first well region 206A and a second well region 206B); and a gate structure (226) over the active region (206) (see Par.[0034] wherein upper portion 230A is similar to openings 224 of gate structures 226A, 228A, 226B, and 228B); an isolation structure (232) disposed between the semiconductor substrate (202) in the first device area (220A) and the semiconductor substrate in the second device area (220B) (see Par.[0036] wherein trench 230 is filled with dielectric material 232. In some embodiments, dielectric material 232 is silicon nitride, or silicon dioxide. In some embodiments, a top surface of dielectric material 232 is substantially co-planar with a top surface of gate structure 226A, 228A, 226B, or 228B); wherein each semiconductor substrate terminates at a backside, and wherein the isolation structure (232) extends to the backside (see Fig.2H, wherein isolation structure 232 extends pass upper surface of substrate to opposing surface).
With respect to claim 11, Wang discloses, in Figs.1-4B, the semiconductor structure, wherein the isolation structure (232) is formed by a continuous poly on diffusion edge (CPODE) process (see Par.[0037] wherein a CPODE layer to form an insulating layer of a capacitor, capacitor 234 includes a greater capacitance with a thin and uniform dielectric material 232. Because dielectric material 232 occupies a small area, capacitor 234 is able to achieve a high capacitance per unit area. In additional, capacitor 234 is able to be coupled to a transistor in an IC layout arrangement without added considerations directed to the priority of capacitors and preserving additional areas to achieve sufficient capacitance).
With respect to claim 12, Wang discloses, in Figs.1-4B, the semiconductor structure, wherein: each device area comprises a terminal source/drain region; and the isolation structure is disposed between the terminal source/drain regions (see Par.[0027] wherein FIG. 2C is a cross-sectional view of semiconductor device 200 following operation 120 in accordance with one or more embodiments. Conductive features 217A, 218A, 217B, and 218B are in recesses 216. In some embodiments, an epi process is performed to form conductive features 217A, 218A, 217B, and 218B).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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