Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 2/23/2026 is acknowledged.
Claims 16-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/23/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/25/2023, 5/23/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the via layer". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2021/0249491; hereinafter Kim).
Regarding claim 1, Fig 5 of Kim discloses a display device comprising:
a pixel circuit layer (VIA/T6/T7; Fig 5; ¶ [0072]) comprising a first transistor (T6; Fig 5; ¶ [0072]) and a conductive pattern (ACT7; Fig 5; ¶ [0094]); and
a display element layer (PDL-191; Fig 5; ¶ [0070]) on the pixel circuit layer, and comprising a light emitting element (EL; Fig 5; ¶ [0070]),
wherein the display element layer further comprises:
a first pixel electrode (CAT; Fig 5; ¶ [0070]) electrically connected to a first end of the light emitting element (EL; Fig 5; ¶ [0070]); and
a second pixel electrode (ANO; Fig 5; ¶ [0070]) electrically connected to a second end of the light emitting element,
wherein the first transistor (T6; Fig 5; ¶ [0072]) comprises:
a semiconductor pattern (ACT6; Fig 5; ¶ [0094]);
a first gate insulating layer (GI (middle portion); Fig 5; ¶ [0106]) on the semiconductor pattern (ACT6; Fig 5; ¶ [0094]);
a gate electrode (172; Fig 5; ¶ [0164]) on the first gate insulating layer; and
a first transistor electrode (182; Fig 5; ¶ [0177]) and a second transistor electrode (162 Fig 5; ¶ [0158]) connected to the semiconductor pattern,
wherein the conductive pattern (ACT7; Fig 5; ¶ [0094]) is at a same layer (Fig 5) as the semiconductor pattern (ACT6; Fig 5; ¶ [0094]), and
wherein the first transistor electrode (182; Fig 5; ¶ [0177]) is connected to the second pixel electrode (ANO; Fig 5; ¶ [0070]) by the conductive pattern (ACT7; Fig 5; ¶ [0094]).
Regarding claim 2, Fig 5 of Kim discloses each of the semiconductor pattern and the conductive pattern comprises an indium gallium zinc oxide (IGZO) (¶ [0170]).
Regarding claim 3, Fig 5 of Kim discloses the semiconductor pattern (ACT6; Fig 5; ¶ [0094]) is physically separated from the conductive pattern (ACT7; Fig 5; ¶ [0094]).
Regarding claim 4, Fig 5 of Kim discloses the conductive pattern (ACT7; Fig 5; ¶ [0094]) is doped with semiconductor material (¶ [0170]).
Regarding claim 5, Fig 5 of Kim discloses the semiconductor pattern (ACT6; Fig 5; ¶ [0094]) and the conductive pattern (ACT7; Fig 5; ¶ [0094]) are doped with a same dopant (¶ [0170]).
Regarding claim 6, Fig 5 of Kim discloses the pixel circuit layer (VIA/T6/T7; Fig 5; ¶ [0072]) further comprises:
a second gate insulating layer (G13; right portion; Fig 5) covering a portion of a first doping area (SD62; Fig 5) of the semiconductor pattern; and
a third gate insulating layer (G13; left portion; Fig 5) covering one area of a second doping area (SD61; Fig 5) of the semiconductor pattern,
wherein the first transistor electrode (182; Fig 5; ¶ [0177]) is on the second gate insulating layer (G13; right portion; Fig 5) and wherein the second transistor electrode (162 Fig 5; ¶ [0158]) is on the third gate insulating layer (G13; left portion; Fig 5).
Regarding claim 7, Fig 5 of Kim discloses the first transistor electrode (182; Fig 5; ¶ [0177]), the second transistor electrode (162 Fig 5; ¶ [0158]) and the gate electrode comprises a same material (Fig 5).
Regarding claim 8, Fig 5 of Kim discloses an overall surface of the conductive pattern (ACT7; Fig 5; ¶ [0094]) is exposed from the first gate insulating layer, the second gate insulating layer and the third gate insulating layer. (Fig 5)
Second Interpretation
Regarding claim 1, Fig 5 of Kim discloses a display device comprising:
a pixel circuit layer (VIA/T6/T7; Fig 5; ¶ [0072]) comprising a first transistor (T6; Fig 5; ¶ [0072]) and a conductive pattern (ACT7; Fig 5; ¶ [0094]); and
a display element layer (PDL-191; Fig 5; ¶ [0070]) on the pixel circuit layer, and comprising a light emitting element (EL; Fig 5; ¶ [0070]),
wherein the display element layer further comprises:
a first pixel electrode (CAT; Fig 5; ¶ [0070]) electrically connected to a first end of the light emitting element (EL; Fig 5; ¶ [0070]); and
a second pixel electrode (ANO; Fig 5; ¶ [0070]) electrically connected to a second end of the light emitting element,
wherein the first transistor (T6; Fig 5; ¶ [0072]) comprises:
a semiconductor pattern (ACT6; Fig 5; ¶ [0094]);
a first gate insulating layer (GI (middle portion); Fig 5; ¶ [0106]) on the semiconductor pattern (ACT6; Fig 5; ¶ [0094]);
a gate electrode (172; Fig 5; ¶ [0164]) on the first gate insulating layer; and
a first transistor electrode (162; Fig 5; ¶ [0177]) and a second transistor electrode (182 Fig 5; ¶ [0158]) connected to the semiconductor pattern,
wherein the conductive pattern (ACT7; Fig 5; ¶ [0094]) is at a same layer (Fig 5) as the semiconductor pattern (ACT6; Fig 5; ¶ [0094]), and
wherein the first transistor electrode (162; Fig 5; ¶ [0177]) is connected to the second pixel electrode (ANO; Fig 5; ¶ [0070]) by the conductive pattern (ACT7; Fig 5; ¶ [0094]).
Regarding claim 9, Fig 5 of Kim discloses the display element layer comprises:
a first alignment electrode (CAT; Fig 5; ¶ [0070]) under the first pixel electrode (CAT; Fig 5; ¶ [0070]); (¶ [0107] discloses that the cathode electrode may include multiple films. Therefore first layer of the cathode layer can be used to read on the first alignment electrode) and
a second alignment electrode (ANO; Fig 5; ¶ [0070]) under the second pixel electrode (ANO; Fig 5; ¶ [0070]), (¶ [0107] discloses that the anode electrode may include multiple films. Therefore first layer of the anode layer can be used to read on the second alignment electrode)
wherein the second alignment electrode (ANO; Fig 5; ¶ [0070]) is directly connected to the second transistor electrode (182 Fig 5; ¶ [0158]).
Regarding claim 13, Fig 5 of Kim discloses the display element layer further comprises an insulating layer (191; Fig 5) covering the first alignment electrode (CAT; Fig 5; ¶ [0070]; (¶ [0107] discloses that the cathode electrode may include multiple films. Therefore first layer of the cathode layer can be used to read on the first alignment electrode)),
wherein the first pixel electrode (CAT; Fig 5; ¶ [0070]) overlaps the first alignment electrode on the insulating layer, and
wherein the second pixel electrode (ANO; Fig 5; ¶ [0070]) overlaps the second alignment electrode on the insulating layer.
Regarding claim 15, Fig 5 of Kim discloses the light emitting element comprises a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer. (¶ [0070])
Allowable Subject Matter
Claims 10-12 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a bottom metal layer on the substrate and overlapping a channel area of the semiconductor pattern; and a buffer layer covering the bottom metal layer, wherein the first transistor is on the buffer layer, and wherein the second transistor electrode is electrically connected to the bottom metal layer through a contact hole”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kim et al (US 2021/0143137)
Moon et al (US 2021/0111197)
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/RATISHA MEHTA/ Primary Examiner, Art Unit 2817