DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 6/22/2026 have been considered but are moot considering new grounds of rejection made below.
For the afore-mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9, 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2018/0069190; hereinafter Kim).
Regarding claim 1, Fig 3 of Kim discloses a display device comprising:
a pixel circuit layer (30/T1/T2; Fig 3; ¶ [0083]) comprising a first transistor (T1; Fig 3; ¶ [0062]) and a conductive pattern (OSP6; Fig 3; ¶ [0093]); and
a display element layer (OLED; Fig 3; ¶ [0058]) on the pixel circuit layer (30/T1/T2; Fig 5; ¶ [0083]) and comprising a light emitting element (OLED; Fig 3; ¶ [0058]),
wherein the display element layer (OLED; Fig 3; ¶ [0058]) further comprises:
a first pixel electrode (CE; Fig 3; ¶ [0109]) electrically connected to a first end of the light emitting element (OLED; Fig 3; ¶ [0058]); and
a second pixel electrode (AE; Fig 3; ¶ [0109]) electrically connected to a second end of the light emitting element (OLED; Fig 3; ¶ [0058]),
wherein the first transistor comprises (T1; Fig 3; ¶ [0062]):
a semiconductor pattern (OSP1; Fig 3; ¶ [0088]);
a first gate insulating layer (20; Fig 3; ¶ [0099]) on the semiconductor pattern (OSP1; Fig 3; ¶ [0088]);
a gate electrode (GE1; Fig 3; ¶ [0098]) on the first gate insulating layer (20; Fig 3; ¶ [0099]); and
a first transistor electrode (DE1; Fig 3; ¶ [0086]) and a second transistor electrode (SE1; Fig 3; ¶ [0086]) located at a same layer (Fig 3) and connected to the semiconductor pattern (OSP1; Fig 3; ¶ [0088]),
wherein the conductive pattern (OSP6; Fig 3; ¶ [0093]) is at a same layer (Fig 5) as the semiconductor pattern (OSP1; Fig 5; ¶ [0088]), and
wherein the first transistor electrode (DE1; Fig 3; ¶ [0086]) is connected to the second pixel electrode (AE; Fig 5; ¶ [0109]) by the conductive pattern (OSP6; Fig 3; ¶ [0093]).
Regarding claim 2, Fig 3 of Kim discloses each of the semiconductor pattern (OSP1; Fig 3; ¶ [0088]) and the conductive pattern (OSP6; Fig 3; ¶ [0093]) comprises an indium gallium zinc oxide (IGZO). (¶ [0093])
Regarding claim 3, Fig 3 of Kim discloses the semiconductor pattern (OSP1; Fig 3; ¶ [0088]) is physically separated from the conductive pattern (OSP6; Fig 3; ¶ [0093]).
Regarding claim 4, Fig 3 of Kim discloses the conductive pattern (OSP6; Fig 3; ¶ [0093]) is doped with semiconductor material (¶ [0088]).
Regarding claim 5, Fig 3 of Kim discloses the semiconductor pattern (OSP1; Fig 3; ¶ [0088]) and the conductive pattern (OSP6; Fig 3; ¶ [0093]) are doped with the same dopant (Fig 3).
Regarding claim 6, Fig 3 of Kim discloses the display element layer further comprises:
a second gate insulating layer (20; left portion; Fig 3) covering a portion of a first doping area (Fig 3) of the semiconductor pattern; and
a third gate insulating layer (20; right portion; Fig 3) covering one area of a second doping area (Fig 3) of the semiconductor pattern,
wherein the first transistor electrode (DE1; Fig 3; ¶ [0086]) is on the second gate insulating layer (20; left portion; Fig 3); and
wherein the second transistor electrode (SE1; Fig 3; ¶ [0086]) is on the third gate insulating layer (20; right portion; Fig 3).
Regarding claim 7, Fig 3 of Kim discloses the first transistor electrode (DE1; Fig 3; ¶ [0086]), the second transistor electrode (SE1; Fig 3; ¶ [0086]) and the gate electrode (GE1; Fig 3; ¶ [0098]) comprise a same material. (Fig 3)
Regarding claim 8, Fig 3 of Kim discloses an overall surface of the conductive pattern is exposed from the first gate insulating layer, the second gate insulating layer and the third gate insulating layer (Fig 3).
Regarding claim 9, Fig 3 of Kim discloses the display element layer comprises:
a first alignment electrode (DE6; Fig 3; ¶ [0102]) under the first pixel electrode (CE; Fig 3; ¶ [0109]); and
a second alignment electrode (SE6; Fig 3; ¶ [0102]) under the second pixel electrode (AE; Fig 3; ¶ [0109]),
wherein the first alignment electrode (DE6; Fig 3; ¶ [0102]) or the second alignment electrode is directly connected (Fig 3) to the second transistor electrode (SE1; Fig 3; ¶ [0086]).
Regarding claim 13, Fig 3 of Kim discloses the display element layer further comprises an insulating layer (30 (comprising multiple layers; ¶ [0099])/PDL; Fig 3) covering the first alignment electrode (DE6; Fig 3; ¶ [0102]) and the second alignment electrode (SE6; Fig 3; ¶ [0102]),
wherein the first pixel electrode (CE; Fig 3; ¶ [0109]) overlaps the first alignment electrode (DE6; Fig 3; ¶ [0102]) on the insulating layer (30; Fig 3), and
wherein the second pixel electrode (AE; Fig 3; ¶ [0109]) overlaps the second alignment electrode (SE6; Fig 3; ¶ [0102]) on the insulating layer.
Regarding claim 14, Fig 3 of Kim discloses the second pixel electrode (AE; Fig 3; ¶ [0109]) is directly connected to the conductive pattern (OSP6; Fig 3; ¶ [0093]) through a second contact hole (CH6; Fig 3; ¶ [0102]) passing through the insulating layer (30 (comprising multiple layers; ¶ [0099])/PDL; Fig 3), a via layer (CH6; Fig 3), and a passivation layer (second layer of 30; Fig 3; ¶ [0099]) covering the first transistor (T1; Fig 3; ¶ [0062]).
Regarding claim 15, Fig 3 of Kim discloses the light emitting element (OLED; Fig 3; ¶ [0058]) comprises a first semiconductor layer (HCL; Fig 3; ¶ [0107]), a second semiconductor layer (ECL; Fig 3; ¶ [0107]), and an active layer (EML; Fig 3; ¶ [0109]) between the first semiconductor layer and the second semiconductor layer.
Allowable Subject Matter
Claims 10-12 are allowed.
Regarding claim 10, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a substrate;
a bottom metal layer on the substrate and overlapping a channel area of the semiconductor pattern; and
a buffer layer covering the bottom metal layer;
wherein the first metal transistor is on the buffer layer; and
wherein the second transistor electrode is electrically connected to the bottom metal layer through a contact hole”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
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