Prosecution Insights
Last updated: April 19, 2026
Application No. 18/494,747

MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §112
Filed
Oct 25, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
537 granted / 635 resolved
+16.6% vs TC avg
Moderate +14% lift
Without
With
+14.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
43 currently pending
Career history
678
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
38.5%
-1.5% vs TC avg
§102
32.3%
-7.7% vs TC avg
§112
25.8%
-14.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 635 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/25/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the first isolation structure” (singular form) in line 4 of the claim, which is indefinite and unclear, because the claim previously only introduces “first isolation structures” (plural form) in line 3 of the claim, and thereby it is unclear which specific first isolation structure is being referenced in the limitation “the first isolation structure” in line 4 of the claim. Claim 1 recites the limitation “the second isolation structure” (singular form) in line 6 of the claim, which is indefinite and unclear, because the claim previously only introduces “second isolation structures” (plural form) in line 5 of the claim, and thereby it is unclear which specific second isolation structure is being referenced in the limitation “the second isolation structure” in line 6 of the claim. Claim 1 recites the limitation “the first active area” (singular form) in line 8 of the claim, which is indefinite and unclear, because the claim previously introduces “first active areas” (plural form) in line 3 of the claim, and thereby it is unclear which specific first active area is being referenced in the limitation “the first active area” in line 8 of the claim. Claim 1 recites the limitation “the second active area” (singular form) in lines 8-9 of the claim, which is indefinite and unclear, because the claim previously introduces “second active areas” (plural form) in lines 5-6 of the claim, and thereby it is unclear which specific second active area is being referenced in the limitation “the second active area” in lines 8-9 of the claim. Claim 7 recites the limitation “the first isolation structure” (singular form) in line 4 of the claim, which is indefinite and unclear, because the claim previously only introduces “first isolation structures” (plural form) in line 3 of the claim, and thereby it is unclear which specific first isolation structure is being referenced in the limitation “the first isolation structure” in line 4 of the claim. Claim 7 recites the limitation “the second isolation structure” (singular form) in line 6 of the claim, which is indefinite and unclear, because the claim previously only introduces “second isolation structures” (plural form) in line 5 of the claim, and thereby it is unclear which specific second isolation structure is being referenced in the limitation “the second isolation structure” in line 6 of the claim. Claim 7 recites the limitation “the first active area” (singular form) in line 8 of the claim, which is indefinite and unclear, because the claim previously introduces “first active areas” (plural form) in line 3 of the claim, and thereby it is unclear which specific first active area is being referenced in the limitation “the first active area” in line 8 of the claim. Claim 7 recites the limitation “the second active area” (singular form) in lines 8-9 of the claim, which is indefinite and unclear, because the claim previously introduces “second active areas” (plural form) in lines 5-6 of the claim, and thereby it is unclear which specific second active area is being referenced in the limitation “the second active area” in lines 8-9 of the claim. Claim 15 recites the limitation “the planning process” in lien 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. Note the dependent claims 2-6 and 8-20 necessarily inherit the indefiniteness of the claims on which they depend. Allowable Subject Matter Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Regarding independent claim 1, Figures 2A-2C of Huang et al. (US 2020/0075614 A1, hereinafter “Huang”) disclose a memory structure, comprising: a substrate 102 (“substrate”- ¶0025), having a first region 201b (“logic region”- ¶0025) and a second region 201a (“memory region”- ¶0025); first isolation structures 234 (“isolation structures”- ¶0031), disposed in the substrate 102 in the first region 201b to define first active areas, wherein a top surface of the first isolation structure 234 is higher than a top surface of the substrate 102; second isolation structures 126 (“isolation structures”- ¶0031; see Figs. 1B and 3 for notation), disposed in the substrate 102 in the second region 201a to define second active areas, wherein a top surface of the second isolation structure 126 is lower than the top surface of the substrate 102; a charge storage layer 112a (“gate… store charges”- ¶0017), disposed on the substrate 102 in the second active area 201a; a first gate 218 (“gate electrode”- ¶0028), disposed in the first active area 201b; a second gate 114a (“control gate”- ¶0017), disposed on the charge storage layer 112a in the second active area 201a; and doped regions 104, 106a, 222a, 222b (“source region”, “drain region”- ¶¶0016, 0028) disposed in the substrate 102 at two sides of the first gate 218 and at two sides of the second gate 114a. Huang does not expressly disclose wherein the charge storage layer is disposed on the substrate in the first active area and the first gate is disposed on the charge storage layer in the first active area. Thus, regarding independent claim 1 (which claims 2-6 depend from), the prior art of record including Huang, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “a charge storage layer, disposed on the substrate in the first active area and the second active area” and “a first gate, disposed on the charge storage layer in the first active area”. Regarding independent claim 7, Figures 2A-2C of Huang disclose a manufacturing method of a memory structure, comprising: providing a substrate 102 (“substrate”- ¶0025), having a first region 201b (“logic region”- ¶0025) and a second region 201a (“memory region”- ¶0025) (see Figs. 2A-2C and 4); forming first isolation structures 234 (“isolation structures”- ¶0031) in the substrate 102 in the first region 201b to define first active areas, wherein a top surface of the first isolation structure 234 is higher than a top surface of the substrate 102 (see Figs. 2A-2C and 5-15); forming second isolation structures 126 (“isolation structures”- ¶0031; see Figs. 1B and 3 for notation) in the substrate 102 in the second region 201a to define second active areas, wherein a top surface of the second isolation structure 126 is lower than the top surface of the substrate 102 (see Figs. 2A-2C and 5-15); forming a charge storage layer 112a (“gate… store charges”- ¶0017) on the substrate 102 in the second active area 201a (see Figs. 2A-2C and 15-16B); forming a first gate 218 (“gate electrode”- ¶0028) in the first active area 201b (see Figs. 2A-2C and 17-18); forming a second gate 114a (“control gate”- ¶0017) on the charge storage layer 112a in the second active area 201a (see Figs. 2A-2C and 15-16B); and forming doped regions 104, 106a, 222a, 222b (“source region”, “drain region”- ¶¶0016, 0028) in the substrate 102 at two sides of the first gate 218 and at two sides of the second gate 114a (see Figs. 2A-2C). Huang does not expressly disclose forming the charge storage layer on the substrate in the first active area and forming the first gate on the charge storage layer in the first active area. Thus, regarding independent claim 7 (which claims 8-20 depend from), the prior art of record including Huang, either singularly or in combination, does not disclose or suggest the combination of limitations including, but not limited to, “forming a charge storage layer on the substrate in the first active area and the second active area” and “forming a first gate on the charge storage layer in the first active area”. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Kawashima et al. (US 2018/0315702 A1), which discloses a memory structure comprising isolation structures disposed in a substrate and located at different heights. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Oct 25, 2023
Application Filed
Jan 05, 2026
Non-Final Rejection — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.5%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 635 resolved cases by this examiner. Grant probability derived from career allow rate.

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