DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 4/8/2026 is acknowledged.
Applicant amended claims 1, 4, 10, 17-21, and 24; and cancelled claim 3.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 6-12, 14-16, and 21-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2021/0201960) (hereafter Lu).
Regarding claim 1, Lu discloses a semiconductor device structure comprising:
a semiconductor substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27);
an active region (upper portion of 202 in Fig. 27) within the semiconductor substrate 202 (Fig. 27), wherein the active region (upper portion of 202 in Fig. 27) comprises
a transistor (AQ1 in Fig. 27, paragraph 0141), the transistor (AQ1 in Fig. 27) comprises a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131) with a bottom surface (bottom surface of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15)) under the original surface (top surface of 202 in Fig. 27), a first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23, paragraph 0145), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139), wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) respectively, and a top surface of the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) is lower than a bottom surface of the second conductive region (Drain-1 and Source-1 in Fig. 27);
a STI region (“CVD-STI-Oxide2” in Fig. 27) surrounding the active region (upper portion of 202 in Fig. 27); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) extended beyond the transistor (AQ1 in Fig. 27) and electrically coupled (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) of the transistor (AQ1 in Fig. 27) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15).
Regarding claim 2, Lu further discloses the semiconductor device structure of claim 1, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is disposed within the STI region (“CVD-STI-Oxide2” in Fig. 27) and under the original surface (top surface of 202 in Fig. 27), and the interconnection layer (UGBL in Fig. 22) is isolated from the semiconductor substrate 202 (Fig. 22).
Regarding claim 4, Lu further discloses the semiconductor device structure of claim 1, the transistor (AQ1 in Fig. 27) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)).
Regarding claim 6, Lu further discloses the semiconductor device structure of claim 1, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is coupled to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) of the transistor at the connection position (see “Drain to UGBL connection” in Fig. 27) through a connection contact (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) which is a highly doped semiconductor plug, or the interconnection layer (UGBL in Fig. 22) is directly coupled to the first conductive region 2202 (Fig. 22) of the transistor at the connection position.
Regarding claim 7, Lu further discloses the semiconductor device structure of claim 1, further comprising a capacitor 2602 (Fig. 27, paragraph 0151) electrically connected to the second conductive region (Drain-1 and Source-1 in Fig. 27), and the interconnection layer (see “UGBL along the X direction” in Fig. 27) is a bitline electrically connected (see Fig. 22) to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23).
Regarding claim 8, Lu further discloses the semiconductor device structure of claim 7, further comprising a wordline (“word lines” in paragraph 0127) electrically connected (see paragraph 0127, wherein “both the gates and the word lines are connected as one body of metal such as Tungsten (W)”) to the gate structure (“gates” in paragraph 0127), and the wordline (“wordlines” in Fig. 11) penetrates through (see Fig. 11, wherein “wordlines” penetrate through “Cross-point square active region”) the second conductive region (not shown in Fig. 11 but see Drain-1 and Source-1 in Fig. 27).
Regarding claim 9, Lu further discloses the semiconductor device structure of claim 1, further comprising a dielectric plug 1902 (Fig. 27, paragraph 0144) between the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) and the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23).
Regarding claim 10, Lu discloses a semiconductor device structure comprising:
a semiconductor substrate 202 (Fig. 27, paragraph 0140) with a semiconductor surface (top surface of 202 in Fig. 27);
a first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 22), a second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 22), and a shallow trench isolation (STI) region (STI, Oxide-1 spacer, and CVD-STI-Oxide2 in Fig. 22) between the first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 22) and the second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 22);
a transistor (AQ1 in Fig. 27, paragraph 0141) formed based on the first active region (upper portion of 202 in Fig. 27) and comprising a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131), a first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23 and “UGBL along the X direction” in Fig. 27), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139), wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) covers a bottom of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) and extends upward along two sidewalls of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15); and
an interconnection layer (element is not shown in Fig. 27 but see 2402 in Fig. 24B, paragraph 0148) within the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and electrically coupled to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) of the transistor (AQ1 in Fig. 27), wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) is below the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of the transistor (AQ1 in Fig. 27).
Regarding claim 11, Lu further discloses the semiconductor device structure of claim 10, wherein a side surface of the interconnection layer (element is not shown in Fig. 27 but see 2402 in Fig. 24B, paragraph 0148) abuts against a side surface of a connection contact (element number is not shown in Fig. 27 but see upper portion of 2202 in Fig. 23) which directly connects the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) of the transistor.
Regarding claim 12, Lu further discloses the semiconductor device structure of claim 10, wherein the interconnection layer (element is not shown in Fig. 27 but see 2402 in Fig. 24B) extends along the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and is positioned under the semiconductor surface (top surface of 202 in Fig. 27).
Regarding claim 14, Lu further discloses the semiconductor device structure of claim 10, wherein a side surface of the interconnection layer (element is not shown in Fig. 27 but see 2402 in Fig. 24B) abuts against a side surface of the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) of the transistor.
Regarding claim 15, Lu further discloses the semiconductor device structure of claim 10, further comprising a capacitor 2602 (Fig. 27, paragraph 0151) electrically connected to the second conductive region (Drain-1 and Source-1 in Fig. 27), and the interconnection layer (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) is a bitline electrically connected to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27).
Regarding claim 16, Lu further discloses the semiconductor device structure of claim 15, further comprising a wordline (“word lines” in paragraph 0127) electrically connected (see paragraph 0127, wherein “both the gates and the word lines are connected as one body of metal such as Tungsten (W)”) to the gate structure (“gates” in paragraph 0127), wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15), and the wordline (“wordlines” in Fig. 11) penetrates through (see Fig. 11, wherein “wordlines” penetrate through “Cross-point square active region”) the two sub-regions of the second conductive region (not shown in Fig. 11 but see Drain-1 and Source-1 in Fig. 27).
Regarding claim 21, Lu discloses a semiconductor device structure comprising:
a semiconductor bulk substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27);
an active region (upper portion of 202 in Fig. 27) within the semiconductor bulk substrate 202 (Fig. 27), wherein the active region (upper portion of 202 in Fig. 27) comprises a plurality of transistors (AQ1 in Fig. 27 and similar to AQ1 formed in second row of transistors in Fig. 28), each transistor (AQ1 in Fig. 28 and similar to AQ1 formed in second row of transistors in Fig. 28) comprises a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131) with a bottom surface (bottom surface of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15)) under the original surface (top surface of 202 in Fig. 27), a first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23, paragraph 0145) electrically coupled to the semiconductor bulk substrate 202 (Fig. 27), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139), wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) respectively, and a top surface of the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) is lower than a bottom surface of the second conductive region (Drain-1 and Source-1 in Fig. 27);
a STI region surrounding (“CVD-STI-Oxide2” in Fig. 27) the active region (upper portion of 202 in Fig. 27); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) extended beyond at least one transistor (AQ1 in Fig. 27) of the plurality of transistors and electrically coupled to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) of at least one transistor (AQ1 in Fig. 27) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of the at least one transistor.
Regarding claim 22, Lu further discloses the semiconductor device structure of claim 21, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is a bit line extended beyond the plurality of transistors (AQ1 in Fig. 28 and similar to AQ1 formed in second row of transistors in Fig. 28) and electrically coupled (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) to each of the plurality of transistors (AQ1 in Fig. 27 and similar to AQ1 formed in second row of transistors in Fig. 28) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of each transistor, respectively.
Regarding claim 23, Lu further discloses the semiconductor device structure of claim 21, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is disposed within the STI region (“CVD-STI-Oxide2” in Fig. 27) and under the original surface (upper portion of 202 in Fig. 27) and is isolated from (see Fig. 22, wherein UGBL is isolated from 202) the semiconductor bulk substrate 202 (Fig. 22), and the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) of the at least one transistor is directly or indirectly connected to a sidewall of the interconnection layer (UGBL in Fig. 22).
Regarding claim 24, Lu further discloses the semiconductor device structure of claim 21, wherein the at least one transistor (AQ1 in Fig. 27) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) of the at least one transistor is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region (Drain-1 and Source-1 in Fig. 27) of the at least one transistor through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)).
Claims 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2016/0315159) (hereafter Yang).
Regarding claim 17, Yang discloses a semiconductor device structure comprising:
a semiconductor substrate (100, 102, and 104 in Fig. 2, paragraphs 0014-0015) with a semiconductor surface (top surface of 102 and 104 in Fig. 2);
an active region (102, 104, and 112 in Fig. 2, paragraph 0015), and a STI region 106 (Fig. 2, paragraph 0015) surrounding the active region (102, 104, and 112 in Fig. 2);
a transistor 144 (Fig. 2, paragraph 0015) within the active region (102, 104, and 112 in Fig. 2), and the transistor 144 (Fig. 2) comprising a gate structure 110 (Fig. 2, paragraph 0015), a drain region 102 (Fig. 2, paragraph 0015), and a source region 112 (Fig. 2, paragraph 0015); and
an interconnection layer 128 (Fig. 2, paragraph 0018) within the STI region 116 (Fig. 2) and electrically coupled (see paragraph 0018, wherein “The sinker contact 128 is always the drain terminal for this transistor”) to the drain region 102 (Fig. 2) of the transistor 144 (Fig. 2), wherein a bottom surface of the source region 112 (Fig. 2) is above a top surface of the drain region 102 (Fig. 2), and the source region 112 (Fig. 2) comprises two sub-regions (left 112 and right 112 in Fig. 2) located on two sides of the gate structure 110 (Fig. 2) respectively.
Regarding claim 18, Yang further discloses the semiconductor device structure of claim 17, wherein the transistor 144 (Fig. 2) further comprising two vertical channel regions (left 104 and right 104 in Fig. 2) separate from each other, wherein the drain region 102 (Fig. 2) is electrically connected to the two sub-regions (left 112 and right 112 in Fig. 2) of the source region 112 (Fig. 2) through the two vertical channel regions (left 104 and right 104 in Fig. 2).
Allowable Subject Matter
1. Claims 5, 13, 19, 20, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 5 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a semiconductor substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27); two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) but fails to disclose a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region in combination with other elements of the base claims 4, 3, and 1.
In addition, claim 13 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27), a second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27), and a shallow trench isolation (STI) region (STI, Oxide-1 spacer, and CVD-STI-Oxide2 in Fig. 22) between the first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27) and the second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27); the interconnection layer (element is not shown in Fig. 27 but see 2402 in Fig. 24B, paragraph 0148) extends along the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and is positioned under the semiconductor surface (top surface of 202 in Fig. 27) but fails to disclose the STI region comprises a first spacer contacted to the first active region and a second spacer contacted to the second active region, and a material of the first spacer is different from that of the second spacer. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: the STI region comprises a first spacer contacted to the first active region and a second spacer contacted to the second active region, and a material of the first spacer is different from that of the second spacer in combination with other elements of the base claims 12 and 10.
Moreover, claim 19 would be allowable because a closest prior art, Yang et al. (US 2016/0315159), discloses a bottom surface of the source region 112 (Fig. 2) is above a top surface of the drain region 102 (Fig. 2), and the source region 112 (Fig. 2) comprises two sub-regions (left 112 and right 112 in Fig. 2) located on two sides of the gate structure 110 (Fig. 2) respectively but fails to disclose a capacitor electrically connected to each of the two sub-regions of the source region of the transistor. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: a capacitor electrically connected to each of the two sub-regions of the source region of the transistor in combination with other elements of the base claim 17. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 20 depend on claim 19.
Furthermore, claim 25 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a semiconductor bulk substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27); wherein the at least one transistor (AQ1 in Fig. 27 and similar to AQ1 formed at second top middle 206 in Fig. 11) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) of the at least one transistor (AQ1 in Fig. 27 and similar to AQ1 formed at second top middle 206 in Fig. 11) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region (Drain-1 and Source-1 in Fig. 27) of the at least one transistor through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) but fails to disclose a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region in combination with other elements of the base claims 24 and 21.
Response to Arguments
1. Applicant's arguments filed 4/8/2026 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 14) that “Therefore, because Lu obviously fails to teach or suggest the technical features "the second conductive region comprises two sub-regions located on two sides of the gate structure respectively" and "a top surface of the first conductive region is lower than a bottom surface of the second conductive region" recited by the currently amended claim 1 of the present invention, the currently amended claim 1 of the present invention should be patentable over Lu” However, Lu et al. (US 2021/0201960) disclose the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) respectively, and a top surface of the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 formed between 1902 in Fig. 23) is lower than a bottom surface of the second conductive region (Drain-1 and Source-1 in Fig. 27).
3. The applicant argues (REMARKS, first paragraph in page 14) that “Therefore, because Lu obviously fails to teach or suggest the technical features "the first conductive region covers a bottom of the gate structure and extends upward along two sidewalls of the gate structure" recited by the currently amended claim 10 of the present invention, the currently amended claim 10 of the present invention should be also patentable over Lu.” However, Lu et al. (US 2021/0201960) disclose the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23 and “UGBL along the X direction” in Fig. 27) covers a bottom of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) and extends upward along two sidewalls of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15).
4. The applicant argues (REMARKS, first paragraph in page 14) that “According to the above-mentioned arguments related to the claim 1, Lu obviously fails to teach or suggest the technical features "the second conductive region25 comprises two sub-regions located on two sides of the gate structure respectively" and "a top surface of the first conductive region is lower than a bottom surface of the second conductive region" recited by the currently amended claim 1 of the present invention, so after the original claim 21 of the present invention is amended according to the above-mentioned features recited by the currently amended claim 1 of the present invention, the currently amended claim 21 of the present invention should be also
patentable over Lu.” However, Lu et al. (US 2021/0201960) disclose the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) respectively, and a top surface of the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 between 1902 in Fig. 23) is lower than a bottom surface of the second conductive region (Drain-1 and Source-1 in Fig. 27).
Applicant's arguments with respect to claims 17-18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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