DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-12, and 14-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US 2021/0201960) (hereafter Lu).
Regarding claim 1, Lu discloses a semiconductor device structure comprising:
a semiconductor substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27);
an active region (upper portion of 202 in Fig. 27) within the semiconductor substrate 202 (Fig. 27), wherein the active region (upper portion of 202 in Fig. 27) comprises
a transistor (AQ1 in Fig. 27, paragraph 0141), the transistor (AQ1 in Fig. 27) comprises a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131) with a bottom surface (bottom surface of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15)) under the original surface (top surface of 202 in Fig. 27), a first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23, paragraph 0145), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139);
a STI region (“CVD-STI-Oxide2” in Fig. 27) surrounding the active region (upper portion of 202 in Fig. 27); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) extended beyond the transistor (AQ1 in Fig. 27) and electrically coupled (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) to the transistor (AQ1 in Fig. 27) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15).
Regarding claim 2, Lu further discloses the semiconductor device structure of claim 1, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is disposed within the STI region (“CVD-STI-Oxide2” in Fig. 27) and under the original surface (top surface of 202 in Fig. 27), and the interconnection layer (UGBL in Fig. 22) is isolated from the semiconductor substrate 202 (Fig. 22).
Regarding claim 3, Lu further discloses the semiconductor device structure of claim 1, wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) respectively, and the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) is lower than the second conductive region (Drain-1 and Source-1 in Fig. 27).
Regarding claim 4, Lu further discloses the semiconductor device structure of claim 3, the transistor (AQ1 in Fig. 27) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)).
Regarding claim 6, Lu further discloses the semiconductor device structure of claim 1, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is coupled to the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) of the transistor at the connection position (see “Drain to UGBL connection” in Fig. 27) through a connection contact (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) which is a highly doped semiconductor plug, or the interconnection layer (UGBL in Fig. 22) is directly coupled to the first conductive region 2202 (Fig. 22) of the transistor at the connection position.
Regarding claim 7, Lu further discloses the semiconductor device structure of claim 1, further comprising a capacitor 2602 (Fig. 27, paragraph 0151) electrically connected to the second conductive region (Drain-1 and Source-1 in Fig. 27), and the interconnection layer (see “UGBL along the X direction” in Fig. 27) is a bitline electrically connected (see Fig. 22) to the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23).
Regarding claim 8, Lu further discloses the semiconductor device structure of claim 7, further comprising a wordline (“word lines” in paragraph 0127) electrically connected (see paragraph 0127, wherein “both the gates and the word lines are connected as one body of metal such as Tungsten (W)”) to the gate structure (“gates” in paragraph 0127), and the wordline (“wordlines” in Fig. 11) penetrates through (see Fig. 11, wherein “wordlines” penetrate through “Corss-point square active region”) the second conductive region (not shown in Fig. 11 but see Drain-1 and Source-1 in Fig. 27).
Regarding claim 9, Lu further discloses the semiconductor device structure of claim 1, further comprising a dielectric plug 1902 (Fig. 27, paragraph 0144) between the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) and the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23).
Regarding claim 10, Lu discloses a semiconductor device structure comprising:
a semiconductor substrate 202 (Fig. 27, paragraph 0140) with a semiconductor surface (top surface of 202 in Fig. 27);
a first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27), a second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27), and a shallow trench isolation (STI) region (STI, Oxide-1 spacer, and CVD-STI-Oxide2 in Fig. 22) between the first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27) and the second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27);
a transistor (AQ1 in Fig. 27, paragraph 0141) formed based on the first active region (upper portion of 202 in Fig. 27) and comprising a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131), a first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23, paragraph 0145), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) within the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and electrically coupled to the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) of the transistor (AQ1 in Fig. 27), wherein the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) is below the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of the transistor (AQ1 in Fig. 27).
Regarding claim 11, Lu further discloses the semiconductor device structure of claim 10, wherein a side surface of the interconnection layer (UGBL in Fig. 22) abuts against a side surface of a connection contact (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) which directly connects the first conductive region 2202 (Fig. 22) of the transistor.
Regarding claim 12, Lu further discloses the semiconductor device structure of claim 10, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) extends along the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and is positioned under the semiconductor surface (top surface of 202 in Fig. 27).
Regarding claim 14, Lu further discloses the semiconductor device structure of claim 10, wherein a side surface of the interconnection layer (UGBL in Fig. 22) abuts against a side surface of the first conductive region 2202 (Fig. 22) of the transistor.
Regarding claim 15, Lu further discloses the semiconductor device structure of claim 10, further comprising a capacitor 2602 (Fig. 27, paragraph 0151) electrically connected to the second conductive region (Drain-1 and Source-1 in Fig. 27), and the interconnection layer (see “UGBL along the X direction” in Fig. 27) is a bitline electrically connected (see Fig. 22) to the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23).
Regarding claim 16, Lu further discloses the semiconductor device structure of claim 15, further comprising a wordline (“word lines” in paragraph 0127) electrically connected (see paragraph 0127, wherein “both the gates and the word lines are connected as one body of metal such as Tungsten (W)”) to the gate structure (“gates” in paragraph 0127), wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15), and the wordline (“wordlines” in Fig. 11) penetrates through (see Fig. 11, wherein “wordlines” penetrate through “Corss-point square active region”) the two sub-regions of the second conductive region (not shown in Fig. 11 but see Drain-1 and Source-1 in Fig. 27).
Regarding claim 17, Lu discloses a semiconductor device structure comprising:
a semiconductor substrate 202 (Fig. 27, paragraph 0140) with a semiconductor surface (top surface of 202 in Fig. 27);
an active region (upper portion of 202 in Fig. 27), and a STI region (“CVD-STI-Oxide2” in Fig. 27) surrounding the active region (upper portion of 202 in Fig. 27);
a transistor (AQ1 in Fig. 27, paragraph 0141) within the active region (upper portion of 202 in Fig. 27), and the transistor (AQ1 in Fig. 27) comprising a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131), a first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 contacting 1902 in Fig. 23, paragraph 0145), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) within the STI region (“CVD-STI-Oxide2” in Fig. 27) and electrically coupled (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) to the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 contacting 1902 in Fig. 23) of the transistor, wherein the second conductive region (Drain-1 and Source-1 in Fig. 27) is above the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 contacting 1902 in Fig. 23) and comprises two sub-regions (Drain-1 and Source-1 in Fig. 27) located on two sides of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131) respectively.
Regarding claim 18, Lu further discloses the semiconductor device structure of claim 17, wherein the transistor (AQ1 in Fig. 27) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see lower portion of 2202 contacting 1902 in Fig. 23) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region through the two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13)).
Regarding claim 19, Lu further discloses the semiconductor device structure of claim 17, further comprising a capacitor 2602 (Fig. 27, paragraph 0151) electrically connected to each of the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region of the transistor.
Regarding claim 20, Lu further discloses the semiconductor device structure of claim 19, wherein the capacitor 2602 (Fig. 27, paragraph 0151) comprises two electrode pillars (connection between Source-1 and 2602 and another connection from 2602 to CSN1) connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region, respectively.
Regarding claim 21, Lu discloses a semiconductor device structure comprising:
a semiconductor bulk substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27);
an active region (upper portion of 202 in Fig. 27) within the semiconductor bulk substrate 202 (Fig. 27), wherein the active region (upper portion of 202 in Fig. 27) comprises a plurality of transistors (AQ1 in Fig. 27 and similar to AQ1 formed in second row of transistors in Fig. 28), each transistor (AQ1 in Fig. 28 and similar to AQ1 formed in second row of transistors in Fig. 28) comprises a gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15, paragraph 0131) with a bottom surface (bottom surface of the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15)) under the original surface (top surface of 202 in Fig. 27), a first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23, paragraph 0145) electrically coupled to the bulk substrate 202 (Fig. 27), and a second conductive region (Drain-1 and Source-1 in Fig. 27, paragraph 0139);
a STI region surrounding (“CVD-STI-Oxide2” in Fig. 27) the active region (upper portion of 202 in Fig. 27); and
an interconnection layer (see “UGBL along the X direction” in Fig. 27) extended beyond at least one transistor (AQ1 in Fig. 27) of the plurality of transistors and electrically coupled to the at least one transistor (AQ1 in Fig. 27) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of the at least one transistor.
Regarding claim 22, Lu further discloses the semiconductor device structure of claim 21, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is a bit line extended beyond the plurality of transistors (AQ1 in Fig. 28 and similar to AQ1 formed in second row of transistors in Fig. 28) and electrically coupled (see Fig. 22, wherein 2202 is electrically connected to UGBL; and see paragraph 0145, wherein “the n+ polysilicon (or Tungsten) plug is connected to the UGBL from its sidewall of the n+ polysilicon (or Tungsten) plug to a sidewall of the UGBL inside the hole-1/2”) to each of the plurality of transistors (AQ1 in Fig. 27 and similar to AQ1 formed in second row of transistors in Fig. 28) at a connection position (see “Drain to UGBL connection” in Fig. 27) under the gate structure (element number is not shown in Fig. 27 but see 1306 in Fig. 15) of each transistor, respectively.
Regarding claim 23, Lu further discloses the semiconductor device structure of claim 21, wherein the interconnection layer (see “UGBL along the X direction” in Fig. 27) is disposed within the STI region (“CVD-STI-Oxide2” in Fig. 27) and under the original surface (upper portion of 202 in Fig. 27) and is isolated from (see Fig. 22, wherein UGBL is isolated from 202) the semiconductor bulk substrate 202 (Fig. 22), and the first conductive region 2202 (Fig. 22) of the at least one transistor is directly or indirectly connected to a sidewall of the interconnection layer (UGBL in Fig. 22).
Regarding claim 24, Lu further discloses the semiconductor device structure of claim 21, the at least one transistor (AQ1 in Fig. 27) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) of the at least one transistor is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region (Drain-1 and Source-1 in Fig. 27) of the at least one transistor through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)).
Allowable Subject Matter
1. Claims 5, 13, and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 5 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a semiconductor substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27); two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) but fails to disclose a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region in combination with other elements of the base claims 4, 3, and 1.
In addition, claim 13 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27), a second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27), and a shallow trench isolation (STI) region (STI, Oxide-1 spacer, and CVD-STI-Oxide2 in Fig. 22) between the first active region (upper portion of 202 between first STI and second STI from the left corner of Fig. 27) and the second active region (upper portion of 202 between second STI and third STI from the left corner of Fig. 27); the interconnection layer (see “UGBL along the X direction” in Fig. 27) extends along the STI region (STI and CVD-STI-Oxide2 in Fig. 27 and element number is not shown in Fig. 27 but see Oxide-1 spacer in Fig. 22) and is positioned under the semiconductor surface (top surface of 202 in Fig. 27) but fails to disclose the STI region comprises a first spacer contacted to the first active region and a second spacer contacted to the second active region, and a material of the first spacer is different from that of the second spacer. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: the STI region comprises a first spacer contacted to the first active region and a second spacer contacted to the second active region, and a material of the first spacer is different from that of the second spacer in combination with other elements of the base claims 12 and 10.
Furthermore, claim 25 would be allowable because a closest prior art, Lu et al. (US 2021/0201960), discloses a semiconductor bulk substrate 202 (Fig. 27, paragraph 0140) with an original surface (top surface of 202 in Fig. 27); wherein the at least one transistor (AQ1 in Fig. 27 and similar to AQ1 formed at second top middle 206 in Fig. 11) further comprising two vertical channel regions (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) separate from each other, wherein the first conductive region (element number is not shown in Fig. 27 but see 2202 in Fig. 23) of the at least one transistor (AQ1 in Fig. 27 and similar to AQ1 formed at second top middle 206 in Fig. 11) is electrically connected to the two sub-regions (Drain-1 and Source-1 in Fig. 27) of the second conductive region (Drain-1 and Source-1 in Fig. 27) of the at least one transistor through the two vertical channel region (vertical regions of a channel region (element number is not shown in Fig. 27 but see 1302 in Fig. 13, paragraph 0131)) but fails to disclose a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor device structure comprising: a highly doped semiconductor region next to one of the two vertical channel regions, the highly doped semiconductor region extends downward from the original surface and a dopant type of the highly doped semiconductor region is different from that of the first conductive region in combination with other elements of the base claims 24 and 21.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813