Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification submitted 10/26/2023 has been accepted by the examiner.
Drawings
The drawings submitted on 10/26/2023 have been accepted by the examiner.
Information Disclosure Statements
The information disclosure statements (IDS) submitted recently have been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 7, 10, 12, 14-15, 18, 20-22, and 24-25 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Siemieniec (cited on IDS dated 2/15/2024).
Regarding Claim 1, Siemieniec (cited on IDS dated 2/15/2024) teaches an edge termination structure for use in a charge balanced semiconductor device (the edge termination structure is capable of this use, see 2nd parag and Fig. 1b), the edge termination structure (compensation structures using a field plate in Figs. 1b, 3, and 4) comprising:
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a plurality of charge balance edge termination trenches (field plates, see Fig. 3) formed in
an edge termination region (peripheral region around source, not including the gate, see right side of Fig. 3) of the semiconductor device, the change balance edge termination trenches extending outwardly from an active region (shown radiating away from center of source region) of the semiconductor device toward the edge termination region on at least two sides of the active region when viewed in a plan view (shown on four sides in Fig. 3(right)), the charge balance edge termination trenches being orthogonal to an edge of the active region (shown orthogonal); and
a plurality of semiconductor mesa regions (p-well regions between the field plates), each of at least a subset of the semiconductor mesa regions being between adjacent charge balance edge termination trenches (shown).
Regarding Claim 2, Siemieniec teaches the edge termination structure according to claim 1, wherein at least a subset of the plurality of charge balance edge termination trenches includes one or more slots therein (see narrow vertical slot between field-plate 1 and field-plate 2), the slots configured to facilitate current flow in the edge termination region and to ensure that there is an electrical connection for all parts of the edge termination region to a top surface of the active region (see page 3, parag. 1-3).
Regarding Claim 7, Siemieniec discloses the edge termination structure according to claim 1, wherein a first subset of the plurality of charge balance edge termination trenches is oriented in a first direction and at least a second subset of the plurality of charge balance edge termination trenches is oriented in a second direction, the second direction being different than the first direction (termination trench layout in top-down view, Fig. 3, trenches horizontal and vertical, perpendicular to nearest active edge).
Regarding Claim 10, Siemieniec discloses the edge termination structure according to claim 1, wherein each of the semiconductor mesa regions includes both an n-type ("n", Fig. 3) semiconductor material and a p-type ("p") semiconductor mate1ial (" ... the semiconductor...", p. 4, 1st Para.).
Regarding Claim 12, Siemieniec discloses the edge termination structure according to claim 1, wherein the plurality of charge balance edge termination trenches arc configured to extend outwardly from the active region (Source) toward the edge termination region (surrounding Source, Fig. 3 right) on at least two adjacent sides of the active region, such that a first subset of the plurality of charge balance edge termination trenches (three) on a first side of the active region is orthogonal to a second subset of the plurality of charge balance edge termination trenches (three) on a second side of the active region adjacent to the first side (inward comer, between Gate and Source, chip layout, Fig. 3 right).
Regarding Claim 14, Siemieniec discloses the edge termination structure according to claim l, further comprising one or more corner structures, each of the corner structures being configured to provide an interface at which ends of a first subset of the plurality of charge balance edge termination trenches extending in a first direction from a first side of the active region meet corresponding facing ends of a second subset of the plurality of charge balance edge termination trenches extending in a second direction from a second side of the active region adjacent to the first side of the active region (i.e. inward comer structure between Gate and Source, Fig. 3 right).
Regarding Claim 15, Siemieniec discloses the edge termination structure according to claim 14, wherein the interface is configured to be at a prescribed angle relative to an edge of the first and second sides of the active region (a prescribed angle of 90 degrees, Fig. 3 right).
Regarding Claim 18, Siemieniec discloses the edge termination structure according to claim 1, further comprising one or more corner structures, each of the corner structures including a first group of charge balance edge termination trenches extending in a first direction perpendicular to a first side of the edge termination region adjacent to the corner structure, and a second group of charge balance edge termination trenches extending in a second direction perpendicular to the first direction, wherein the first and second groups of charge balance edge termination trenches are distributed throughout the corner structure such that the charge balance edge termination trenches in any two adjacent groups of trenches are orthogonally oriented relative to one another (i.e. all horizontal trenches are orthogonally oriented relative to all vertical trenches, in top-down view, Fig. 3 right).
Regarding Claim 20, Siemieniec discloses the edge termination structure according to claim 1, wherein the plurality of charge balance edge termination trenches extends outwardly from the active region toward the edge termination region on at least three sides of the active region, when viewed in a plan view (i.e. outwardly from active region "Source" to the termination region from six sides, chip layout, Fig. 3 right).
Regarding Claim 21, Siemieniec discloses the edge termination structure according to claim 1, wherein the plurality of charge balance edge termination trenches extends outwardly from the active region toward the edge termination region on all four sides of the active region, when viewed in a plan view (i.e. on all four [major] sides of active region "Source", chip layout, Fig. 3 right).
Regarding Claim 22, Siemieniec discloses a charge balanced semiconductor device ("charge compensation principles" for "power MOSFET", introduction, 2nd Para.; negative charges balanced by positive charges seen in Fig. lb), comprising:
an active region including at least one active element therein ("Source", Fig. 3 right); and an edge termination region ("edge termination", Fig. 3) extending around the active region when viewed in a plan view ("chip layout", Fig. 3 right) the edge termination region including at least one edge termination structure ("compensation structure[s] using a field plate", Figs. 1b, 3, and 4) comprising:
a plurality of charge balance edge termination trenches ("field plates in trenches", Fig. 3), the charge balance edge termination trenches extending outwardly from the active region of the semiconductor device toward the edge termination region on at least two sides of the active region (extends outwardly from 6 sides of the active source region, chip layout, Fig. 3 right), the charge balance edge termination trenches being orthogonal to an edge of the active region (the narrow lengths of the trenches are perpendicular to the nearest active region edge); and
a plurality of semiconductor mesa regions (field-plate of trench connected to semiconductor mesa between trenches, Fig. 3 left), each of the semiconductor mesa regions being between adjacent charge balance edge termination trenches (Fig. 3).
Regarding Claim 24, Siemieniec discloses the semiconductor device according to claim 22, wherein the plurality of charge balance edge termination trenches in the at least one edge termination structure extends outwardly from the active region toward the edge termination region on at least three sides of the active region when viewed in a plan view (from six sides of active region "Source" in top-down view, chip layout, Fig. 3 right).
Regarding Claim 25, Siemieniec discloses the semiconductor device according to claim 22, wherein the plurality of charge ha lance edge termination trenches extend outwardly from the active region toward the edge termination region on all four sides of the active region (i.e. from all four major sides, "chip layout", Fig. 3 right).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 11, 19, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in view of Mouhoubi (cited on IDS dated 2/15/2024).
Regarding Claim 3, Siemieniec fails to explicitly disclose that the slots are configured such that slots formed in one of the charge balance edge termination trenches are not aligned, when viewed in a plan view, with slots formed in an adjacent one of the charge balance edge termination trenches.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
For example, Mouhoubi is in the same or analogous field, and it teaches slots configured such that slots formed in one of the charge balance edge termination trenches are not aligned, when viewed in a plan view, with slots formed in an adjacent one of the charge balance edge termination trenches (spaced apart trenches 226, Fig. 13) which can be "advantageous ... for corner features that cause unwanted charge imbalance" (Col. 13, Lns. 56-59).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the slot configuration of Mouhoubi for the purpose of dividing the trench electrode into segments that spread the current and electric field more uniformly in the edge termination region at a corner feature for example.
Regarding Claim 11, Siemieniec fails to explicitly disclose that the slots are configured such that slots formed in one of the charge balance edge termination trenches are not aligned, when viewed in a plan view, with slots formed in an adjacent one of the charge balance edge termination trenches.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Mouhoubi teaches that a fixed charge layer in the balanced charge trench is advantageously determined as a "predetermined or desired amount of charge" (Col. 6, Lns. 22-26) for a "charge compensated filled trenches 22" (Col. 6, Ln. 19).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the fixed charge of Mouhoubi for the purpose of designing a built-in charge compensation level based on a desired design amount.
Regarding Claim 19, Siemieniec fails to explicitly disclose that each of at least a subset of the plurality of semiconductor mesa regions forms an electrically conductive structure, and each of at least a subset of the plurality of charge balance edge termination trenches forms an elect1ically non-conductive structure.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Mouhoubi teaches that the plurality of semiconductor mesa regions may form an electrically conductive structure ("semiconductor material 11 ", Col. 13, Ln. 65, Fig. 14), and the charge balance edge termination trenches may form an electrically non-conductive structure (" ... one or more dielectric materials ... ", Col. 14, Lns. 65-66).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the non-conductive charge balanced termination trench of Mouhoubi for the purpose of reliably controlling fixed charge as the amount trapped in the insulator.
Regarding Claim 23, Siemieniec fails to explicitly disclose that at least a subset of the plurality of semiconductor mesa regions in the at least one edge termination structure is an electrically conductive structure, and each of at least a subset of the plurality of charge balance edge termination trenches in the at least one edge termination structure is an electrically nonconductive structure.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Mouhoubi teaches at least a subset of the plurality of semiconductor mesa regions in the at least one edge termination structure is an electrically conductive structure ("semiconductor material 11 ", Col. 13, Ln. 65, Fig. 14), and each of at least a subset of the plurality of charge balance edge termination trenches in the at least one edge termination structure is an electrically nonconductive structure (" ... one or more dielectric materials ... ", Col. 14, Lns. 65-66).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the nonconductive charge balanced trench of Mouhoubi for the purpose of controlling the amount of fixed charge trapped in the insulator and without affecting other parts of the device.
Claims 4-6 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in view of Challa (cited on IDS dated 2/15/2024).
Regarding Claim 4, Siemieniec fails to explicitly disclose that the edge termination structure is configured such that a first amount of charge balance in the edge termination region is different relative to a second amount of charge balance in the active region of the semiconductor device.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Challa, in the field of charge balanced edge termination, teaches that the edge termination structure is configured such that a first amount of charge balance in the edge termination region is different relative to a second amount of charge balance in the active region of the semiconductor device (" ... decreasing charge ... from the active region ... ", Col. 22, Lns. 62-65).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the charge balance configuration of Challa for the purpose of optimizing device performance for the active area and breakdown voltage for the edge termination.
Regarding Claim 5, Siemieniec fails to explicitly disclose that a spacing between at least a subset of adjacent charge balance edge termination trenches in the edge termination region, when viewed in a plan view, is different relative to a spacing between adjacent charge balance trenches in the active region of the semiconductor device.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Challa teaches that a spacing between at least a subset of adjacent charge balance edge termination trenches in the edge termination region, when viewed in a plan view, is different relative to a spacing between adjacent charge balance trenches in the active region of the semiconductor device (Fig. 29A and Fig. 29B).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the differing charge balance trench spacings of Challa for the purpose of achieving desired electric field distribution for operation in the active region yet high breakdown voltage in the edge termination region.
Regarding Claim 6, Siemieniec fails to explicitly disclose a boundary trench extending around a periphery of the semiconductor device.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Challa teaches a boundary trench ("perimeter trench 3213", Fig. 32A) extending around a periphery of the semiconductor device (i.e. "perimeter").
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the boundary trench of Challa for the purpose of increasing breakdown voltage at the device periphery.
Regarding Claim 13, Siemieniec fails to explicitly disclose a boundary trench extending along a periphery of the semiconductor device, when viewed in a plan view, parallel to the plurality of charge balance edge termination trenches.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Challa teaches a boundary trench extending along a periphery of the semiconductor device, when viewed in a plan view (Fig. 32A), parallel to the plurality of charge balance edge termination trenches when provided about the entire perimeter as implied (e.g. Fig. 3 right, Siemieniec).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the boundary trench of Challa for the purpose of increasing breakdown voltage.
Claims 8, 9, 16, 17, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in view of Tamaki (cited on IDS dated 2/15/2024).
Regarding Claim 8, Siemieniec fails to explicitly disclose a field plate above at least a subset of the plurality of charge balance edge termination trenches, the field plate configured to distribute an electric field in the semiconductor device.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Tamaki, in the field of charge balanced edge termination, teaches a field plate above at least a subset of the plurality of charge balance edge termination trenches, the field plate configured to distribute an electric field in the semiconductor device ("field plate 30", Col. 43, Ln. 20, Fig. 104).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the field plate of Tamaki for the purpose of increasing breakdown voltage.
Regarding Claim 9, Siemieniec fails to explicitly disclose a guard ring defining a transition between the active region and the edge termination region.
Tamaki teaches a guard ring ("region 8", Fig. 104; "having a ring-like shape", Col. 40, Ln. 62) defining a transition between the active region (15, Fig. 104) and the edge termination region (3, Fig. 104).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the guard ring of Tamaki for the purpose of increasing breakdown voltage.
Regarding Claim 16, Siemieniec fails to explicitly disclose that ends of the first subset of the plurality of charge balance edge termination trenches are offset relative to corresponding facing ends of the second subset of the plurality of charge balance edge termination trenches.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Tamaki teaches ends of the first subset of the plurality of charge balance edge termination trenches offset relative to the corresponding facing ends of the second subset of the plurality of charge balance edge termination trenches (Fig. 100 and Fig. 101).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the termination trench layout of Tamaki for the purpose of achieving a more uniform electric field while minimizing field concentration at trench edges.
Regarding Claim 17, Siemieniec fails to explicitly disclose that the interface is configured such that an end of each of the first subset of the plurality of charge balance edge termination trenches is aligned with a mesa between adjacent trenches in the second subset of the plurality of charge balance edge termination trenches, and vice versa.
Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below.
Tamaki teaches that the interface is configured such that an end of each of the first subset of the plurality of charge balance edge termination trenches is aligned with a mesa between adjacent trenches in the second subset of the plurality of charge balance edge termination trenches, and vice versa (Fig. 100 and Fig. 101).
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the termination trench corner layout of Tamaki for the purpose of improving electric field distribution for increased breakdown voltage.
Regarding Claim 26, Siemieniec fails to explicitly disclose a guard ring of a first conductivity type (p-type), the guard ring extending around the active region when viewed in a plan view and defining a boundary between the active region and the edge termination region in the semiconductor device, wherein the plurality of semiconductor mesa regions are of a second conductivity type opposite in polarity to the first conductivity type.
Tamaki teaches a guard ring (region 8, Fig. 79 and Fig. 104) of a first conductivity type (p-type), the guard ring extending around the active region when viewed in a plan view ("ring-like") and defining a boundary between the active region and the edge termination region in the semiconductor device (Fig. 104), wherein the plurality of semiconductor mesa regions are of a second conductivity type ( 1 On, n-type, Fig. 79) opposite in polarity to the first conductivity type.
It would have been obvious to one of ordinary skill in the art before the priority date to modify Siemieniec with the guard ring of Tamaki for the purpose of increasing breakdown voltage without altering on resistance.
Conclusion
Other Pertinent prior art:
US # 20150155378
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/CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899