Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The applicant’s most recent amendment, filed on 07/31/2026, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered; the pending claims are 1-12, 15, and 21-27.
Response to Arguments
Applicant’s arguments with respect to all pending claims have been considered but are moot because the arguments do not apply to the current grounds of rejection.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following features must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Claim 12: conformally forming a first spacer layer to cover the first fin portion, the second fin portion, the first gate structure, and the second gate structure; and forming a pair of spacers to laterally cover vertical portions of the first spacer layer, which laterally cover one of the first gate structure and the second gate structure.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11, 12, and 21 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ching (US # 20210043626).
Regarding Claim 1, Ching teaches a method for manufacturing a semiconductor device, comprising:
forming a first fin portion (104, I/O device) and a second fin portion (104, core device) on a semiconductor substrate (102), the first fin portion and the second fin portion being spaced apart from each other by an isolation portion (116 in trench 502);
and depositing a first gate dielectric layer (802 of 114B) and a second gate dielectric layer (high-k dielectric of 114B) on the first fin portion and the second fin portion (see Figs. 15 and corresponding text), respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness ([0028, 46]),
wherein the first gate dielectric layer covers an upper surface and a sidewall of the first fin portion, and the second gate dielectric layer covers an upper surface and a sidewall of the second fin portion ([0027, 46, 62]).
Regarding Claim 11, Ching teaches a method for manufacturing a semiconductor device,
comprising:
forming a first fin portion (104 in I/O region) and a second fin portion (104 in core-device region) on a semiconductor substrate (102), the first fin portion and the second fin portion extending in a first direction (X-direction; [0028]) parallel to an upper surface of the semiconductor substrate, and being spaced apart from each other in a second direction (Y-direction; see Fig. 1) parallel to the upper surface of the semiconductor substrate and different from the first direction (shown);
depositing a first gate dielectric layer (802 of 114B) and a second gate dielectric layer (high-k dielectric of 114B) on the first fin portion and the second fin portion, respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness ([0028, 46]); and
forming a first gate structure (114B) and a second gate structure (114A) on the first fin portion, the second fin portion, or each of the first fin portion and the second fin portion, each of the first gate structure and the second gate structure including a gate dielectric ([0062]), which is formed by patterning a corresponding one of the first gate dielectric layer and the second gate dielectric layer ([0060]),
wherein the first gate dielectric layer covers an upper surface and a sidewall of the first fin portion ([0046]; and see Fig. 8), and the second gate dielectric layer covers an upper surface and a sidewall of the second fin portion ([0061-62]).
Regarding Claim 12, insofar as the claim scope can be ascertained in view of the 35 USC 112 rejections and/or claim objections above, Ching teaches the method as claimed in claim 11, further comprising:
conformally forming a first spacer layer (1002A) to cover the first fin portion, the second fin portion, the first gate structure, and the second gate structure; and
forming a pair of spacers (1002B) to laterally cover vertical portions of the first spacer layer, which laterally cover one of the first gate structure and the second gate structure.
Regarding Claim 21, Ching teaches the method for manufacturing a semiconductor device,
comprising:
forming a first fin portion (104 in I/O region 106) and a second fin portion (104 in I/O core-device region 108) on a semiconductor substrate (102), the first fin portion and the second fin portion being spaced apart from each other (shown);
depositing a first gate dielectric layer (114B) and a second gate dielectric layer (114A) on the first fin portion and the second fin portion, respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness ([0028, 46]); and
annealing one of the first gate dielectric layer and the second gate dielectric layer ([0046]),
wherein the first gate dielectric layer covers an upper surface and a sidewall of the first fin portion ([0046]), and the second gate dielectric layer covers an upper surface and a sidewall of the second fin portion ([0062]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 7-10, 15, 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US # 20210043626) in view of Crowder (US # 20030094660).
Regarding Claim 2, Ching teaches the method as claimed in claim 1, wherein deposition of the first gate dielectric layer and the second gate dielectric layer includes:
depositing a first dielectric material film (802) to cover the first fin portion, the isolation portion, and the second fin portion ([0046]);
forming a patterned photoresist layer (1406) to cover a portion of the first dielectric material film on the first fin portion ([0060]);
removing a remaining portion of the first dielectric material film exposed from the patterned photoresist layer ([0060]) so as to form a first gate dielectric film (802 remainder on I/O region) on the first fin portion, the first gate dielectric film including a first portion that covers a part of an upper surface of the isolation portion, a second portion that covers the upper surface of the first fin portion, and a third portion that connects the first portion and the second portion and that laterally covers the sidewall of the first fin portion (802 covers across the top of STI 116 and the fins);
depositing a second gate dielectric film (114; [0062]) on the first gate dielectric film, the isolation portion, and the second fin portion, so as to form the first gate dielectric layer on the first fin portion and the second gate dielectric layer on the second fin portion (114B), the first gate dielectric layer including the first gate dielectric film and a first portion of the second gate dielectric film disposed on the first gate dielectric film, the second gate dielectric layer including a second portion of the second gate dielectric film, the first thickness of the first gate dielectric layer being greater than the second thickness of the second gate dielectric layer ([0046]).
Although Ching discloses much of the claimed invention, it does not explicitly teach the method steps comprising removing the patterned photoresist layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder is in the same or analogous field, and it teaches a set of method steps comprising removing the patterned photoresist layer ([0033, 37]).
A person having ordinary skill in the art would have recognized that modifying the method steps of Ching with the step suggested by Crowder would be obvious. Specifically, the modification suggested by Crowder would be to employ a set of method steps comprising removing the patterned photoresist layer. The rationale for this obvious modification is that removing the photoresist provides space and interfaces for the other parts of the device ([0033]). This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of photo-resist-removal are well known in the art (see MPEP 2144.01).
Regarding Claim 7, although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 1, wherein formation of the first gate dielectric layer and the second gate dielectric layer includes:
forming a patterned photoresist layer to cover the first fin portion;
treating the second fin portion with a nitrogen doping process;
removing the patterned photoresist layer; and
depositing a gate dielectric material film on the first fin portion and the second fin portion, so as to simultaneously form the first gate dielectric layer and the second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first thickness of the first gate dielectric layer being greater than the second thickness of the second gate dielectric layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder is in the same or analogous field, and it teaches masking with a patterned photoresist (7; [0033]), implanting nitrogen into the unmaked region ([0034]), stripping the resist ([0037]); forming the dielectric in a single step, the nitrogen-implanted region receiving the thinner layer because nitrogen “retards the subsequent thermal oxidation rate” ([0019, 36]).
A person having ordinary skill in the art would have recognized that modifying the method steps of Ching with the masked I/O fin suggested by Crowder would be obvious. Specifically, the modification suggested by masked the I/O fin, implanted nitrogen into the exposed portion of the fin, stripped the mask, and formed the gate dielectric because the implant then allows for different thicknesses with fewer method steps ([0017, 38]).
Regarding Claim 8, Crowder, as applied to claim 7, teaches the method as claimed wherein the nitrogen doping process is conducted by implantation or thermal diffusion ([0034]).
Regarding Claim 9, Crowder, as applied to claim 8, teaches the method as claimed wherein the nitrogen doping process is conducted by implantation at an energy ranging from 1 KeV to 400 KeV ([0034-35]).
Regarding Claim 10, Crowder, as applied to claim 8, teaches the method as claimed in claim 8, wherein the nitrogen doping process is conducted by implantation at a dose ranging from 1x 1010 atoms/cm2 to 1x1016 atoms/cm2 ([0034-35]).
Regarding Claim 15, although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 11, wherein formation of the first gate dielectric layer and the second gate dielectric layer includes:
forming a patterned photoresist layer to cover the first fin portion;
treating the second fin portion with one of a fluorine doping process and a nitrogen doping process;
removing the patterned photoresist layer; and
depositing a gate dielectric material film on the first fin portion and the second fin portion, so as to integrally form the first gate dielectric layer on the first fin portion and the second gate dielectric layer on the first fin portion and the second fin portion, respectively.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder is in the same or analogous field, and it teaches a method as claimed wherein formation of a first gate dielectric layer and a second gate dielectric layer includes:
forming a patterned photoresist layer to cover a device region ([0033]);
treating a second fin portion with one of a fluorine doping process and a nitrogen doping process ([0034] describes halogen implant);
removing a patterned photoresist layer ([0037]); and
depositing a gate dielectric material film with multiple thicknesses ([0036-38]).
The sequence of the doping steps may be reversed ([0028]).
A person having ordinary skill in the art would have recognized that modifying the method steps of Ching with the masked I/O fin suggested by Crowder would be obvious. Specifically, the modification suggested by masked the I/O fin, implanted nitrogen into the exposed portion of the fin, stripped the mask, and formed the gate dielectric because the implant then allows for different thicknesses with fewer method steps ([0017, 38]).
Regarding Claim 24, Ching teaches the method as claimed in claim 21, wherein the first thickness of the first gate dielectric layer is greater than the second thickness of the second gate dielectric layer ([0046, 60]),
Although Ching discloses much of the claimed invention, it does not explicitly teach the method wherein the second fin portion is doped with a plurality of nitrogen ions.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder is in the same or analogous field, and it teaches a method wherein an unmasked region is doped with a plurality of nitrogen ions ([0034, 36, 38]).
A person having ordinary skill in the art would have recognized that modifying the dielectric formation steps of Ching with the nitrogen-ion doping suggested by Crowder would be obvious. Specifically, the modification suggested by Crowder would be to employ a method wherein the second fin portion is doped with a plurality of nitrogen ions. The rationale for this obvious modification is that the ion implant then allows for different dielectric thicknesses with fewer method steps ([0017, 38]).
Regarding Claim 25, Ching teaches the method as claimed in claim 2, wherein the second portion of the second gate dielectric film (114A portion in the core-gate-trench) includes a first part ([0062]) that covers a remaining part of the upper surface of the isolation portion, a second part that covers the upper surface of the second fin portion, and a third part that connects the first part of the second gate dielectric film and the second part of the second gate dielectric film and that laterally covers the sidewall of the second fin portion ([0027] raised channel 112).
Regarding Claim 26, although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 11, wherein the first gate dielectric layer and the second gate dielectric layer are simultaneously deposited to form a continuous layer structure.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder is in the same or analogous field, and it teaches a method wherein an unmasked region is doped with a plurality of nitrogen ions such that two dielectric features are simultaneously deposited to form a continuous layer structure ([0034, 36, 38]).
A person having ordinary skill in the art would have recognized that modifying the dielectric formation steps of Ching with the continuous layer structure suggested by Crowder would be obvious. Specifically, the modification suggested by Crowder would be to employ a method as claimed in claim 11, wherein the first gate dielectric layer and the second gate dielectric layer are simultaneously deposited to form a continuous layer structure. The rationale for this obvious modification is that the ion implant then allows for different dielectric thicknesses along a continuous layer, which results in fewer method steps ([0017, 38]).
Claims 3-6 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ching (US # 20210043626) in view of Crowder (US # 20030094660), and Ting (US # 20200357802).
Regarding Claim 3, although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 1, wherein formation of the first gate dielectric layer and the second gate dielectric layer includes: forming a patterned photoresist layer to cover the first fin portion; treating the second fin portion with a fluorine doping process; removing the patterned photoresist layer; and depositing a gate dielectric material film on the first fin portion and the second fin portion, so as to simultaneously form the first gate dielectric layer and the second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first thickness of the first gate dielectric layer being less than the second thickness of the second gate dielectric layer.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Crowder teaches masking a first region with patterned photoresist ([0029]), implanting a growth-rate modifying species into the unmasked region ([0030]), removing the photoresist ([0033]), and forming a dielectric layer that has multiple thicknesses ([0038]). Ting teaches a fluorine implant may be performed to increase oxide growth ([0024]).
A person having ordinary skill in the art would have recognized that modifying the method steps of Ching with the masking and implant steps suggested by Crowder and Ting would be obvious. Specifically, the modification suggested by Crowder and Ting would be to employ a method as claimed in claim 1, wherein formation of the first gate dielectric layer and the second gate dielectric layer includes: forming a patterned photoresist layer to cover the first fin portion; treating the second fin portion with a fluorine doping process; removing the patterned photoresist layer; and depositing a gate dielectric material film on the first fin portion and the second fin portion, so as to simultaneously form the first gate dielectric layer and the second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first thickness of the first gate dielectric layer being less than the second thickness of the second gate dielectric layer. The rationale for this obvious modification is that fluorine-treated fins provide greater thickness and makes it possible to decrease the number of steps for forming the dielectrics with different thicknesses ([0017, 38]).
Regarding Claim 4, Crowder and Ting, as applied to claim 3, teaches the method wherein the fluorine doping process is conducted by implantation or thermal diffusion (Crowther [0030] and Ting [0024]).
Regarding Claim 5, Crowder, as applied to claim 4, teaches the method as claimed in claim 4, wherein the fluorine doping process is conducted by implantation at an energy ranging from 1 KeV to 400 KeV ([0030-31]).
Regarding Claim 6, Crowder, as applied to claim 4, teaches the method as claimed in claim 4, wherein the fluorine doping process is conducted by implantation at a dose ranging from 1x 1010 atoms/cm2 to 1x1016 atoms/cm2 ([0030]).
Regarding Claim 23, although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 21, wherein the first thickness of the first gate dielectric layer is less than the second thickness of the second gate dielectric layer, and the second fin portion is doped with a plurality of fluorine ions.
Although Ching discloses much of the claimed invention, it does not explicitly teach the method as claimed in claim 21, wherein the first thickness of the first gate dielectric layer is less than the second thickness of the second gate dielectric layer, and the second fin portion is doped with a plurality of fluorine ions.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Ting is in the same or analogous field, and it teaches a portion is doped with a plurality of fluorine ions ([0024]). Crowder teaches a method wherein the first thickness of the first gate dielectric layer is less than the second thickness of the second gate dielectric layer ([0030, 38]).
A person having ordinary skill in the art would have recognized that modifying the method steps of Ching with the dielectric formation steps suggested by Ting and Crowder would be obvious. Specifically, the modification suggested by Ting and Crowder would be to employ a method as claimed in claim 21, wherein the first thickness of the first gate dielectric layer is less than the second thickness of the second gate dielectric layer, and the second fin portion is doped with a plurality of fluorine ions. The rationale for this obvious modification is that implanted fluorine ions into the fin active region because it provides it affects the thickness of the gate dielectric layer and minimizes the number of method steps in the formation of a variety of gate-dielectric thicknesses.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Ching (US # 20210043626) in view of King (US # 20040110337).
Regarding Claim 22, Ching teaches the method as claimed in claim 21, wherein the one of the first gate dielectric layer and the second gate dielectric layer is annealed ([0046])
Although Ching discloses much of the claimed invention, it does not explicitly teach the gate dielectric method annealing at a temperature ranging from 500 °C to 1600 °C.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, King is in the same or analogous field, and it teaches a gate dielectric (1040) method annealing at a temperature ranging from 500°C to 1600°C ([0181-82]).
A person having ordinary skill in the art would have recognized that modifying the anneal temperature of Ching with the temperature suggested by King would be obvious. Specifically, the modification suggested by King would be to employ a gate dielectric method annealing at a temperature ranging from 500 °C to 1600 °C. The rationale for this obvious modification is that this temperature range provides improved material quality, such as damage repair ([0046]).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Ching (US # 20210043626) in view of Crowder (US # 20030094660), and further in view of Gardner (US # 5882993).
Regarding Claim 27, Crowder, as applied to claim 15, teaches the method as claimed in claim 15, wherein the one of the fluorine doping process and the nitrogen doping process (0034)
Although Ching in view of Crowder discloses much of the claimed invention, it does not explicitly teach the method wherein the doping process is conducted by thermal diffusion.
Nonetheless the prior art before the effective filing date of the claimed invention renders such non-explicit feature differences obvious, as explained below.
For example, Gardner is in the same or analogous field, and it teaches a method wherein the doping process is conducted by thermal diffusion (col. 5, lns. 46-52; col. 6, lns. 1-4; gate dielectric 118 is formed on top of that region after diffusion of nitrogen).
A person having ordinary skill in the art would have recognized that modifying the halogen doping process of Ching in view of Crowder with the thermal diffusion process suggested by Gardner would be obvious. Specifically, the modification suggested by Gardner would be to employ a method wherein the doping process is conducted by thermal diffusion. The rationale for this obvious modification is that thermal diffusion provides the same growth-retarding species in the same mask-defined regions and may then produce the same differential in gate-dielectric thickness (col. 6, lns. 55-64). This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of implantation and thermal diffusion are well known in the art (see MPEP 2144.01). These two techniques were art-recognized alternatives for accomplishing the identical purpose. See MPEP 2413(I)(B).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A JOHNSON/Primary Examiner, Art Unit 2899
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