DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1 and 6 stand rejected under Section 102 in view of Goktepeli. Claims 1 and 7 stand rejected under Section 102 in view of Chinthakindi. Claims 2-4, 9, 13, 15, 21, and 22 stand rejected under Section 103 in view of Chinthakindi and Tran. Claims 5 and 11 stand rejected under Section 103 in view of Chinthakindi, Tran, and Forster. Claim 8 stands rejected under Section 103 in view of Chinthakindi and Chakihara. Claim 10 stands rejected under Section 103 in view of Chinthakindi, Tran, and Waldemer. Claim 12 stands rejected under Section 103 in view of Chinthakindi and Tran, with evidence from Lee. Claim 6 stands rejected under Section 103 in view of Chinthakindi and Chao. Claims 14 and 23-25 stand rejected under Section 103 in view of Chinthakindi, Tran, and Chao. The specification stands objected to. Claims 16-20 were previously canceled.
Applicants amended claims 1, 9, and 21, canceled claim 6. Applicants provided amendments to the specification. Applicants argue that the application is in condition for allowance.
Turning first to the specification: Applicants’ amendments address the previously noted specification objections and are accepted and entered. No new matter has been added. The previously noted specification objections are withdrawn.
Section 102 rejections: Applicants’ amendments overcome the previously noted Section 102 rejections. These rejections are withdrawn.
Section 103 rejections: Applicants’ amendments overcome the Section 103 rejections of claims 1-5, 7, and 8, but not the Section 103 rejections of claims 9-15 and 21-25. The amendments to independent claim 1 include subject matter from claim 6 as well as a requirements that (1) the conductive structure include a second gate electrode; and that (2) the substrate, the silicide layer, the first dielectric layer, the metal structure, the second dielectric layer, and the conductive structure are stacked and aligned along a second axis, which is perpendicular to a first axis along which the substrate extends. (The Office notes a Section 112(a) written description rejection, see below, that is directly to the latter set of additional claim limitations. The former claim limitation is supported by the originally filed disclosure—see applicants’ specification ¶ 32.) Applicants argue that independent claims 9 and 21 recite analogous elements, but upon review and comparison of these claims with claim 1, the Office finds that they are different. Thus, the rejections of independent claims 9 and 21 and their dependent claims are updated to reflect the current language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5, 7, and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1: This claim is rejected on two bases. Claim 1 has been amended to require “a substrate extending along a first axis; […] wherein the substrate, the silicide layer, the first dielectric layer, the metal structure, the second dielectric layer, and the conductive structure are stacked and aligned along a second axis perpendicular to the first axis.” The drawings show the silicide layer, the first dielectric layer, the metal structure, the second dielectric layer, and the conductive structure being aligned along a second axis perpendicular to the first axis, but there is insufficient information as to whether the substrate is aligned along with the silicide layer, the first dielectric layer, the metal structure, the second dielectric layer, and the conductive structure along the second axis. The drawings show a substrate, but this substrate would be a center section of the device’s substrate or side portion of the substrate on which other items are placed. Because the originally filed disclosure does not specifically disclose the substrate being aligned with the silicide layer, the first dielectric layer, the metal structure, the second dielectric layer, and the conductive structure along the second axis, claim 1 is rejected for failing to meet the written description requirement.
Claims 2-5, 7, and 8 are rejected for depending from rejected base claim 1.
Regarding claim 7, which depends from claim 1: Claim 1 has been amended to require that “the second dielectric layer traverses both a bottom surface and a sidewall surface of the conductive structure….” (emphasis added). Claim 7, which depends from claim 1, requires that “the second dielectric layer traverses only a bottom surface but not a sidewall surface of the conductive structure.” (emphasis added). Because the requirements of claim 7 conflict with the requirements of its parent claim, claim 1, claim 7 is rejected as indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 13, 15, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi, U.S. Pat. No. 2007/0057343, Figure 9A, and further in view of Tran, U.S. Pat. Pub. No. 2013/0175666, Figure 1A.
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Regarding claim 9: Chinthakindi Figure 9A discloses a semiconductor structure (901), comprising: a substrate (31); and a capacitor over the substrate (31), comprising: a silicide layer (141B) over the substrate (31); a first dielectric layer (160) over the silicide layer (141B); a metal gate structure (138M) over the first dielectric layer (160), wherein a top portion of the metal gate structure (138M) is over the substrate (31); a second dielectric layer (140C) over the metal gate structure (138M); and a conductive structure (242) over the second dielectric layer (140C), wherein the second dielectric layer (140C traverses a bottom surface of the conductive structure (242). Chinthakindi specification ¶¶ 134-150. Chinthakindi does not disclose that the bottom portion of the metal gate structure (138M) extends into the substrate (31), or that the second dielectric layer (140C) traverses both a bottom surface and a sidewall surface of the conductive structure (242). As for the requirement that the second dielectric layer (140C) traverse a sidewall surface of the conductive structure (242), applicants’ disclosure does not indicate the patentable significance of the shape of the second dielectric layer (140C). Furthermore, another dielectric layer in the form of blanket dielectric layer (149) is present along the sidewall surface of conductive structure (242). Id. ¶ 147. Because the shape of the second dielectric layer (140C) is not patentably significant, and another dielectric layer (149) covers the sidewall surface of the conductive structure (242), the requirement that the second dielectric layer (140C) traverse both the bottom surface and the sidewall surface of the conductive structure (242) is an obvious variant over the prior art.
Tran Figure 1A, directed to similar subject matter, discloses a capacitor in which lower and upper electrodes (110, 112) are embedded in trenches (104) in a substrate (102), with the upper electrode (112) including a top portion over the substrate (102) and a bottom portion that extends into the substrate (102). Tran specification ¶¶ 15-23. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to include the Tran design because the modification would increase capacitor storage capacity.
Regarding claim 13, which depends from claim 9: Chinthakindi discloses wherein the second dielectric layer (140C) includes a high-k dielectric material. Chinthakindi specification ¶ 135.
Regarding claim 15, which depends from claim 9: The combination discloses that the substrate (Chinthakindi (35); Tran (102)) includes: a doped region (Chinthakindi (35); Tran (106)) that surrounds the bottom portion of the metal gate structure (Chinthakindi (138M); Tran (112)); and source/drain regions (Tran (N+ regions); see also Chinthakindi’ s unnumbered regions where vias (145T) contact the silicide layer (141B)) disposed in the doped region (Tran (106)), wherein the bottom portion of the metal gate structure (Tran (112)) is interposed between the source/drain regions (Tran (N+ regions)), and wherein the silicide layer (Chinthakindi (141B)) extends over the source/drain regions (Tran (N+ regions)/Chinthakindi’ s unnumbered regions). Chinthakindi specification ¶¶ 134-150; Tran specification ¶¶ 15-23.
Regarding claim 21: Chinthakindi Figure 9A discloses semiconductor device (901), comprising: a well region (35) disposed along an active surface of a semiconductor device (901); and a gate structure (141B, 160, 138M, 140C, 242) coupled with the well region (35), the gate structure (141B, 160, 138M, 140C, 242) comprising: a lateral surface extending over and configured to gate a conduction of a conduction channel extending through the well region (35); a conductive structure (138M), wherein the lateral surface traverses a bottom of the conductive structure (138M); wherein the lateral surface comprises a contiguous layer of a silicide layer (141B) conformal to a gate dielectric (160). Chinthakindi does not disclose that the gate structure comprises a plurality of lateral surfaces extending over and configured to gate a conduction of a conduction channel extending through the well region; that the at least one lateral surface of the plurality of lateral surfaces traverses both a bottom surface and a sidewall surface of the conductive structure; and a plurality of fingers extending downward into the well region from the plurality of lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous layer of a silicide layer conformal to a gate dielectric.
Tran Figure 1A, directed to similar subject matter, discloses a gate structure in which lower and upper electrodes (110, 112) are embedded in trenches (104) in a substrate (102), with the lower electrode (110) comprising a plurality of lateral surfaces extending over and configured to gate a conduction of a conduction channel extending through the well region (106); a conductive structure (112), wherein at least one lateral surface of the plurality of lateral surfaces traverses both a bottom surface and a sidewall surface of the conductive structure (112); and a plurality of fingers extending downward into the well region (106) from the plurality of lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous lower electrode layer (110) conformal to a gate dielectric (114). Tran specification ¶¶ 15-23. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to include the Tran design because the modification would increase capacitor storage capacity. Once combined, the combination discloses the gate structure comprises a plurality of lateral surfaces extending over and configured to gate a conduction of a conduction channel extending through the well region; a conductive structure, wherein at least one lateral surface of the plurality of lateral structures traverses both a bottom surface and a sidewall surface of the conductive structure; and a plurality of fingers extending downward into the well region from the plurality of lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous layer of a silicide layer conformal to a gate dielectric.
Regarding claim 22, which depends from claim 21: The combination discloses wherein the gate structure (141B, 160, 138M, 140C, 242) includes a metal structure (138M) comprising: a first portion disposed above the silicide layer (141B) and the gate dielectric (160); and a plurality of second portions corresponding to the plurality of fingers, laterally bounded by the silicide layer (141B). See Chinthakindi Figure 9A.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Waldemer, U.S. Pat. Pub. No. 2022/0415573, Figure 4.
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Regarding claim 10, which depends from claim 9: The combination discloses the bottom portion of the metal gate structure includes a trench surrounded by the first dielectric layer and the silicide layer, see Tran specification ¶¶ 19, 20, but not that the metal gate structure includes at least one column structure surrounded by the first dielectric layer and the silicide layer.
Waldemer Figure 4, directed to similar subject matter, discloses a capacitor with an upper electrode (middle (406)) which includes at least one column structure surrounded by a capacitor dielectric (410) and a lower electrode (lower (406)). Waldemer specification ¶¶ 70-73. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use columns instead of trenches because the modification would have involved the substitution of an equivalent known for the same purpose.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Forster, U.S. Pat. Pub. No. 2003/0068867, Figures 1-7.
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Regarding claim 11, which depends from claim 9: The combination is silent as to the presence of a rough surface on the bottom portion of the metal gate structure.
Forster Figures 1-7, directed to similar subject matter, discloses a technique for roughening portions of trenches where capacitors are located. Forster specification ¶¶ 49-61. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Forster design because the Forster design increases capacitor storage capacity. Once combined, the combination discloses bottom portion of the metal gate structure has a rough surface.
Claim 12 is are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, with evidence from Lee, U.S. Pat. Pub. No. 2016/0035631.
Regarding claim 12, which depends from claim 9: Chinthakindi is silent about the specific metal in the embodiment shown in its Figure 9A, but discloses in a related embodiment that a suitable metal for another metal capacitor electrode is TiN, Chinthakindi specification ¶ 49. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the TiN material for the metal gate structure because the modification would have involved the substitution of an equivalent known for the same purpose. Chinthakindi is silent as to whether titanium nitride is a work function metal. Lee, directed to similar subject matter, discloses that titanium nitride is a work function metal. Lee specification ¶ 90.
Claims 14 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Chao, U.S. Pat. Pub. No. 2004/0077142, Figures 1-6.
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Regarding claim 14, which depends from claim 9: The combination does not disclose a third dielectric layer between the metal gate structure and the second dielectric layer, the third dielectric layer having a composition different from the second dielectric layer.
Chao Figures 1-6, directed to similar subject matter, disclose the use of two different capacitor dielectric layers (30’ (aluminum oxide), 34’ (tantalum oxide)) between capacitor electrodes. Chao specification ¶¶ 28-60. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use Chao capacitor dielectric bi-layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 23, which depends from claim 22: The combination does not disclose a high-k dielectric layer having a lower surface coplanar to the metal structure, and a U-shaped upper surface partially enclosing a conductive structure.
Chao, directed to similar subject matter, discloses a manufacturing method in which the high-k dielectric (30, 34) is deposited in an opening on the lower capacitor electrode (28), resulting in the claimed shape: a high-k dielectric layer (30, 34) having a lower surface coplanar to the lower electrode (28), and a U-shaped upper surface partially enclosing a conductive structure (38). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use Chao capacitor dielectric layer arrangement because the modification would have involved the substitution of an equivalent known for the same purpose. In the alternative, applicants have not indicated the patentable significance of the high-k dielectric layer’s shape. Thus, the requirements directed to this shape are patentably insignificant shape variations over the prior art.
Regarding claim 24, which depends from claim 23: The combination discloses the high-k dielectric layer (30, 34) includes: a first portion configured to directly interfaced with the metal structure (138M); and a second portion (vertical section of high-k dielectric layer (30, 34)), distinct from and thicker than the first portion. See Chao Figure 6.
Regarding claim 25, which depends from claim 24: The combination discloses the high-k dielectric layer (30, 34) is a dielectric of a capacitor having a first electrode (138M) comprising the metal structure and a second electrode comprising the conductive structure (242).
Allowable Subject Matter
Claims 1-5, 7, and 8 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(a) and 35 U.S.C. 112(b), set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 1: The claim has been found allowable because the prior art of record does not disclose “wherein the conductive structure includes a second gate electrode” in combination with the remaining limitations of the claim.
With regard to claims 2-5, 7, and 8: The claims have been found allowable due to their dependency from claim 1 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
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/Victoria K. Hall/ Primary Examiner, Art Unit 2897
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