DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15 in the reply filed on February 3, 2026 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
Page 6, paragraph 26, line 1: Change “S1of” to “S1 of”.
Page 6, paragraph 28, line 1: Change “S1includes” to “S1 includes”.
Page 7, paragraph 29, line 1: Change “S1includes” to “S1 includes”.
Page 8, paragraph 32, line 1: Change “S1includes” to “S1 includes”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 6 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Goktepeli, U.S. Pat. No. 9,812,580, Figure 5.
PNG
media_image1.png
396
433
media_image1.png
Greyscale
Regarding claim 1: Goktepeli Figure 5 discloses a semiconductor structure, comprising: a substrate (540); a silicide layer (554) over the substrate (540); a first dielectric layer (522) over the silicide layer (554); a metal structure (520) over the first dielectric layer (522), wherein the metal structure (520) includes a gate electrode; a second dielectric layer (504) over the metal structure (520); and a conductive structure (570) over the second dielectric layer (504). Goktepeli specification, co. 8, l. 1, - col. 9, l. 35.
Regarding claim 6, which depends from claim 1: Goktepeli discloses the second dielectric layer (504) traverses both a bottom surface and a sidewall surface of the conductive structure (570) See Goktepeli Figure 5.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chinthakindi, U.S. Pat. No. 2007/0057343, Figure 9A.
PNG
media_image2.png
381
438
media_image2.png
Greyscale
Regarding claim 1: Chinthakindi Figure 9A discloses a semiconductor structure (901), comprising: a substrate (31); a silicide layer (141B) over the substrate (31); a first dielectric layer (160) over the silicide layer (141B); a metal structure (138M) over the first dielectric layer (160), wherein the metal structure (138M) includes a gate electrode; a second dielectric layer (140C) over the metal structure (138M); and a conductive structure (242) over the second dielectric layer (140C). Chinthakindi specification ¶¶ 134-150.
Regarding claim 7, which depends from claim 1: Chinthakindi discloses the second dielectric layer (140C) traverses only a bottom surface but not a sidewall surface of the conductive structure (242). See Chinthakindi Figure 9A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 9, 13, 15, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi, and further in view of Tran, U.S. Pat. Pub. No. 2013/0175666, Figure 1A.
PNG
media_image3.png
350
532
media_image3.png
Greyscale
Regarding claim 2, which depends from claim 1: Chinthakindi discloses the metal structure (138M) includes a first portion over the substrate (31), but does not disclose that the metal structure (138M) includes a plurality of second portions embedded in the substrate (31).
Tran Figure 1A, directed to similar subject matter, discloses a capacitor in which lower and upper electrodes (110, 112) are embedded in trenches (104) in a substrate (102), with the upper electrode (112) including a first portion over the substrate (102) and a plurality of second portions embedded in the substrate (102). Tran specification ¶¶ 15-23. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to include the Tran design because the modification would increase capacitor storage capacity.
Regarding claim 3, which depends from claim 2: The combination discloses the silicide layer (141B) and the first dielectric layer (160) are between the first portion of the metal structure (138M) and the substrate (31), and between the plurality of second portions of the metal structure (138M, as modified by Tran) and the substrate (31).
Regarding claim 4, which depends from claim 2: The combination discloses the substrate (Chinthakindi (31); Tran (102)) includes a doped region (Chinthakindi (35); Tran (108)) that embeds the plurality of second portions. See Tran Figure 1A, Tran specification ¶ 16; Chinthakindi Figure 9A, Chinthakindi specification ¶ 135.
Regarding claim 9: Chinthakindi Figure 9A discloses a semiconductor structure (901), comprising: a substrate (31); and a capacitor over the substrate (31), comprising: a silicide layer (141B) over the substrate (31); a first dielectric layer (160) over the silicide layer (141B); a metal gate structure (138M) over the first dielectric layer (160), wherein a top portion of the metal gate structure (138M) is over the substrate (31); a second dielectric layer (140C) over the metal gate structure (138M); and a conductive structure (242) over the second dielectric layer (140C). Chinthakindi specification ¶¶ 134-150. Chinthakindi does not disclose that the bottom portion of the metal gate structure (138M) extends into the substrate (31).
Tran Figure 1A, directed to similar subject matter, discloses a capacitor in which lower and upper electrodes (110, 112) are embedded in trenches (104) in a substrate (102), with the upper electrode (112) including a top portion over the substrate (102) and a bottom portion that extends into the substrate (102). Tran specification ¶¶ 15-23. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to include the Tran design because the modification would increase capacitor storage capacity.
Regarding claim 13, which depends from claim 9: Chinthakindi discloses wherein the second dielectric layer (140C) includes a high-k dielectric material. Chinthakindi specification ¶ 135.
Regarding claim 15, which depends from claim 9: The combination discloses that the substrate (Chinthakindi (35); Tran (102)) includes: a doped region (Chinthakindi (35); Tran (106)) that surrounds the bottom portion of the metal gate structure (Chinthakindi (138M); Tran (112)); and source/drain regions (Tran (N+ regions); see also Chinthakindi’ s unnumbered regions where vias (145T) contact the silicide layer (141B)) disposed in the doped region (Tran (106)), wherein the bottom portion of the metal gate structure (Tran (112)) is interposed between the source/drain regions (Tran (N+ regions)), and wherein the silicide layer (Chinthakindi (141B)) extends over the source/drain regions (Tran (N+ regions)/Chinthakindi’ s unnumbered regions). Chinthakindi specification ¶¶ 134-150; Tran specification ¶¶ 15-23.
Regarding claim 21: Chinthakindi Figure 9A discloses semiconductor device (901), comprising: a well region (35) disposed along an active surface of a semiconductor device (901); and a gate structure (141B, 160, 138M, 140C, 242) coupled with the well region (35), the gate structure (141B, 160, 138M, 140C, 242) comprising: a lateral surface extending over and configured to gate a conduction of a conduction channel extending through the well region (35); wherein the lateral surface comprises a contiguous layer of a silicide layer (141B) conformal to a gate dielectric (160). Chinthakindi does not disclose that the gate structure comprises a plurality of lateral surfaces extending over and configured to gate a conduction of a conduction channel extending through the well region; and a plurality of fingers extending downward into the well region from the lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous layer of a silicide layer conformal to a gate dielectric.
Tran Figure 1A, directed to similar subject matter, discloses a gate structure in which lower and upper electrodes (110, 112) are embedded in trenches (104) in a substrate (102), with the lower electrode (110) comprising a plurality of lateral surfaces extending over and configured to gate a conductive of a conduction channel extending through the well region (106); and a plurality of fingers extending downward into the well region (106) from the lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous lower electrode layer (110) conformal to a gate dielectric (114). Tran specification ¶¶ 15-23. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to include the Tran design because the modification would increase capacitor storage capacity. Once combined, the combination discloses the gate structure comprises a plurality of lateral surfaces extending over and configured to gate a conduction of a conduction channel extending through the well region; and a plurality of fingers extending downward into the well region from the lateral surfaces, wherein the plurality of fingers and the plurality of lateral surfaces comprise a contiguous layer of a silicide layer conformal to a gate dielectric.
Regarding claim 22, which depends from claim 21: The combination discloses wherein the gate structure (141B, 160, 138M, 140C, 242) includes a metal structure (138M) comprising: a first portion disposed above the silicide layer (141B) and the gate dielectric (160); and a plurality of second portions corresponding to the plurality of fingers, laterally bounded by the silicide layer (141B). See Chinthakindi Figure 9A.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Forster, U.S. Pat. Pub. No. 2003/0068867, Figures 1-7.
PNG
media_image4.png
538
896
media_image4.png
Greyscale
Regarding claim 5, which depends from claim 2: The combination does not disclose each of the plurality of second portions of the metal structure has a roughened surface.
Forster Figures 1-7, directed to similar subject matter, discloses a technique for roughening portions of trenches where capacitors are located. Forster specification ¶¶ 49-61. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Forster design because the Forester design increases capacitor storage capacity. Once combined, the combination discloses each of the plurality of second portions of the metal structure has a roughened surface.
Regarding claim 11, which depends from claim 9: The combination does not disclose that the bottom portion of the metal gate structure has a rough surface.
Forster Figures 1-7, directed to similar subject matter, discloses a technique for roughening portions of trenches where capacitors are located. Forster specification ¶¶ 49-61. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the Forster design because the Forester design increases capacitor storage capacity. Once combined, the combination discloses bottom portion of the metal gate structure has a rough surface.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi, and further in view of Chakihara, U.S. Pat. No. 9,543,315, Figures 3-6.
PNG
media_image5.png
382
441
media_image5.png
Greyscale
PNG
media_image6.png
586
801
media_image6.png
Greyscale
PNG
media_image7.png
384
810
media_image7.png
Greyscale
Regarding claim 8, which depends from claim 1: Chinthakindi does not disclose that a spacer along a sidewall of the metal structure and the conductive structure. However, Chinthakindi Figure 8A, an alternative embodiment, discloses a spacer (139) along a sidewall of a silicide middle electrode (138C) and a polysilicon middle electrode (138P). Chinthakindi specification ¶ 123.
Chakihara Figures 3-6, directed to similar subject matter, disclose a spacer (SW) along the sidewall of a lower capacitor (CE2A) and an upper capacitor electrode (CE3A). Chakihara specification, col. 12, l. 26 – col. 15, l. 30. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to use the spacers because the modification protects the sidewalls.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Waldemer, U.S. Pat. Pub. No. 2022/0415573, Figure 4.
PNG
media_image8.png
477
645
media_image8.png
Greyscale
Regarding claim 10, which depends from claim 9: The combination discloses the bottom portion of the metal gate structure includes a trench surrounded by the first dielectric layer and the silicide layer, see Tran specification ¶¶ 19, 20, but not that the metal gate structure includes at least one column structure surrounded by the first dielectric layer and the silicide layer.
Waldemer Figure 4, directed to similar subject matter, discloses a capacitor with an upper electrode (middle (406)) which includes at least one column structure surrounded by a capacitor dielectric (410) and a lower electrode (lower (406)). Waldemer specification ¶¶ 70-73. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use columns instead of trenches because the modification would have involved the substitution of an equivalent known for the same purpose.
Claim 12 is are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, with evidence from Lee, U.S. Pat. Pub. No. 2016/0035631.
Regarding claim 12, which depends from claim 9: Chinthakindi is silent about the specific metal in the embodiment shown in its Figure 9A, but discloses in a related embodiment that a suitable metal for another metal capacitor electrode is TiN, Chinthakindi specification ¶ 49. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use the TiN material for the metal gate structure because the modification would have involved the substitution of an equivalent known for the same purpose. Chinthakindi is silent as to whether titanium nitride is a work function metal. Lee, directed to similar subject matter, discloses that titanium nitride is a work function metal. Lee specification ¶ 90.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi, and further in view of Chao, U.S. Pat. Pub. No. 2004/0077142, Figs 1-6.
PNG
media_image9.png
622
811
media_image9.png
Greyscale
Regarding claim 6, which depends from claim 1: Chinthakindi does not disclose that the second dielectric layer traverses both a bottom surface and a sidewall surface of the conductive structure.
Chao Figures 1-6, directed to similar subject matter, discloses a second dielectric layer (30, 34) that, due to the method by which the capacitor is made, results in a the second dielectric layer (30, 34) traversing both a bottom surface and a sidewall surface of the upper electrode (38). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify Chinthakindi to use the Chao capacitor dielectric arrangement because the modification would have involved the substitution of an equivalent known for the same purpose. In the alternative, applicants have not indicated the patentable significance of the second dielectric layer’s shape. Thus, the requirements directed to this shape are patentably insignificant shape variations over the prior art.
Claims 14 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chinthakindi and Tran, and further in view of Chao, Figures 1-6.
Regarding claim 14, which depends from claim 9: The combination does not disclose a third dielectric layer between the metal gate structure and the second dielectric layer, the third dielectric layer having a composition different from the second dielectric layer.
Chao Figures 1-6, directed to similar subject matter, disclose the use of two different capacitor dielectric layers (30’ (aluminum oxide), 34’ (tantalum oxide)) between capacitor electrodes. Chao specification ¶¶ 28-60. One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use Chao capacitor dielectric bi-layer because the modification would have involved the substitution of an equivalent known for the same purpose.
Regarding claim 23, which depends from claim 22: The combination does not disclose a high-k dielectric layer having a lower surface coplanar to the metal structure, and a U-shaped upper surface partially enclosing a conductive structure.
Chao, directed to similar subject matter, discloses a manufacturing method in which the high-k dielectric (30, 34) is deposited in an opening on the lower capacitor electrode (28), resulting in the claimed shape: a high-k dielectric layer (30, 34) having a lower surface coplanar to the lower electrode (28), and a U-shaped upper surface partially enclosing a conductive structure (38). One having ordinary skill in the art at a time before the effective filing date would be motivated to modify the combination to use Chao capacitor dielectric layer arrangement because the modification would have involved the substitution of an equivalent known for the same purpose. In the alternative, applicants have not indicated the patentable significance of the high-k dielectric layer’s shape. Thus, the requirements directed to this shape are patentably insignificant shape variations over the prior art.
Regarding claim 24, which depends from claim 23: The combination discloses the high-k dielectric layer (30, 34) includes: a first portion configured to directly interfaced with the metal structure (138M); and a second portion (vertical section of high-k dielectric layer (30, 34)), distinct from and thicker than the first portion. See Chao Figure 6.
Regarding claim 25, which depends from claim 24: The combination discloses the high-k dielectric layer (30, 34) is a dielectric of a capacitor having a first electrode (138M) comprising the metal structure and a second electrode comprising the conductive structure (242).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTORIA KATHLEEN HALL whose telephone number is (571)270-7567. The examiner can normally be reached Monday-Friday, 8 a.m.-5 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Victoria K. Hall/Primary Examiner, Art Unit 2897
Prosecution Insights