DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendment
Applicant's amendment to the claims, filed on April 7th, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Election/Restrictions
Applicant's election without traverse of Invention I, species A (claims 1-10 and new claims 21-30) in the reply filed on April 7th, 2026, is acknowledged.
Claim 4 recites “the through-via is formed after the first device die is bonded with the second device die” which being described as through-via 27A formed after device dies 20 bonded to device die 120’ as shown in non-elected species of Figs. 8-9. Claim 4 is also withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21, 23-26 and 28 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by NAKATSUKA (Pub. No.: US 2023/0395546 A1).
Regarding claim 21, NAKATSUKA discloses a method in Fig. 4 comprising: forming a first device die (chip 10_1) comprising: a first integrated circuit (memory array 11_1) (see [0016]); forming a second device die (chip 20) comprising a power switch (transistor Tr) (see [0065]); and bonding the second device die to the first device die (bonding through electrodes PD1 and PD2 at bonding surface BF1), wherein the power switch is electrically connected to the first integrated circuit (see [0063]), and wherein the power switch is configured to (transistors Tr control memory cell array 11): cut off power to the first integrated circuit in response to a first control signal (apply voltage at 0V to turn off memory array 11); and provide power to the first integrated circuit in response to a second control signal (apply voltage at 5V to turn on memory array 11) (see [0065]).
Regarding claim 23, NAKATSUKA discloses the method of claim 21, further comprising forming a control circuit (voltage generation circuit 22) configured to provide the first control signal and the second control signal, wherein the control circuit is outside of the first device die (see Fig. 1 and [0026-0027]).
Regarding claim 24, NAKATSUKA discloses the method of claim 23, wherein the control circuit is formed in the second device die (voltage generation circuit 22 is inside chip 20) (see Fig. 1 and [0026-0027).
Regarding claim 25, NAKATSUKA discloses the method of claim 21, wherein the first device die is bonded to the second device die through face-to-face bonding (see Fig. 4 and [0063]).
Regarding claim 26, NAKATSUKA discloses the method of claim 21, wherein the power switch comprises a transistor (transistor Tr) (see [0065]).
Regarding claim 28, NAKATSUKA discloses the method of claim 21, wherein the first device die further comprises a second integrated circuit, wherein a power supplying path (a separate path of SGS from row decoder) for supplying power to the second integrated circuit (another transistor Tr) is decoupled from the power switch (see Figs. 1-2, 4 and [0023-0032], [0065]).
Claims 21-22 and 27 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dutta et al. (Pub. No.: US 2024/0429128 A1), hereinafter as Dutta.
Regarding claim 21, Dutta discloses a method in Fig. 2A comprising: forming a first device die (chip 251) comprising: a first integrated circuit (transistors 260) (see [0021]); forming a second device die (chip 201) comprising: a power switch (MOSFET 210A); and bonding the second device die to the first device die (bonding through via 295 and 245), wherein the power switch is electrically connected to the first integrated circuit (through contacts and conductive wires in MOL and BEOL layers), and wherein the power switch is configured to: cut off power to the first integrated circuit in response to a first control signal (MOSFET 210A would stop sending power from source region 211 to transistor 260 when a voltage of 0V applied to the gate of MOSFET 210A); and provide power to the first integrated circuit in response to a second control signal (sending power to transistor 260 when a voltage of 5V applied to the gate of MOSFET 210A) (see Dutta and Fig. 2A).
Regarding claim 22, Dutta discloses the method of claim 21, wherein the forming the first device die comprises a logic die (transistor 260 can acts as logic circuit), and the forming the second device die comprises an input/output die (MOSFET 210A can acts as in/out circuit) (see Dutta and Fig. 2A).
Regarding claim 27, Dutta discloses the method of claim 21, wherein a power supplying path for supplying power to the first integrated circuit (transistor 260) comprises: a first part (via 292b) penetrating through the first device die to reach the power switch (MOSFET 210A) (power come from via 292b reach to MOSFET 210A); and a second part (via 245) having a first portion in the first device die, and a second portion (via 295) in the second device die (signal or power send to MOSFET 210A from via 292b and can reach back to source region 261 of transistor 260 by source region 211 of MOSFET 210A through vias 295 and 245) (see Fig. 2A and [0019]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (Pub. No.: US 2024/0429128 A1), hereinafter as Dutta in view of DeLaCruz et al. (Pub. No.: US 2023/0090121 A1), hereinafter as DeLaCruz.
Regarding claim 1, Dutta discloses a method in Fig. 2A comprising: forming a first device die (chip 251) comprising: a first integrated circuit (transistors 260) (see [0021]); a first bond pad (left via 295) at a first surface of the first device die, wherein the first integrated circuit is electrically connected to the first bond pad (through contact 283 and conductive wires 281 in BEOL region 259 and MOL region 258) (see [0025] and [0040]); forming a second device die (chip 201) comprising: a power switch (MOSFET 210A) comprising: a first source/drain region (source 211) (see [0033]); a second source/drain region (drain 212); a second bond pad (middle via 245) electrically connecting to the first source/drain region (through contact and conductive wires in MOL region 208 and BEOL region 209) (see [0028] and [0036]); and a third bond pad (left via 245) electrically connecting to the second source/drain region (see [0036]); bonding the first device die with the second device die to form a first package (3DIC structure 200a), with the first bond pad bonding to the third bond pad (left via 295 bonding to left via 245) (see [0040]).
Dutta fails to disclose the method comprising bonding the first package to a package component.
DeLaCruz discloses a method comprising bonding a first package of first device die (IC 212-A) and a second device die (IC 214-A) to a package component (package substrate 232) (see Fig. 2A and [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the package component of DeLaCruz into the method of Dutta for bonding the first device die of first package (chip 251) to the package component because the modified structure would reduce footprint, increase bandwidth and performance with shorter interconnects and improve thermal management.
Regarding claim 5, the combination of Dutta and DeLaCruz discloses the method of claim 1, wherein the first device die is bonded between the second device die and the package component (see Fig. 2A of Dutta and Fig. 2A of DeLaCruz).
Regarding claim 7, the combination of Dutta and DeLaCruz discloses the method of claim 1, wherein the first device die is bonded with the second device die through face-to-face bonding (see Fig. 2A of Dutta).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (Pub. No.: US 2024/0429128 A1), hereinafter as Dutta in view of DeLaCruz et al. (Pub. No.: US 2023/0090121 A1), hereinafter as DeLaCruz, as applied to claim 1 and further in view of KABE et al. (Pub. No.: US 2016/0190103 A1), hereafter as Kabe.
Regarding claim 2, the combination of Dutta and DeLaCruz discloses the method of claim 1, wherein the forming the first device die further comprises forming a through-via (via 292b) penetrating through a substrate of the first device die (layers 290 and 254), wherein after the first device die is bonded with the second device die, the through- via is electrically coupled to the first source/drain region (see Dutta, Figs. 2A, 4.8 and [0025], [0045]).
The combination of Dutta and DeLaCruz fails to disclose the substrate being semiconductor.
Kabe discloses a method comprising a substrate (substrate 121) being semiconductor (silicon) (see Fig. 1 and [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate semiconductor material of substrate of Kabe into the method of Dutta for making the substrate of Dutta because silicon is well known and low-cost material for making substrate with high performance.
Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. (Pub. No.: US 2024/0429128 A1), hereinafter as Dutta in view of DeLaCruz et al. (Pub. No.: US 2023/0090121 A1), hereinafter as DeLaCruz and further in view of KABE et al. (Pub. No.: US 2016/0190103 A1), hereafter as Kabe.
Regarding claim 29, Dutta discloses a method in Fig. 2A comprising: a method comprising: a first device die (chip 251), wherein the first device die comprises: a substrate (layer 290 and 254) (see [0026]); an integrated circuit (transistors 260) on the substrate (see [0021]); a through-via (drain via 292b) penetrating through the substrate (see [0025]); and bonding a second device die (chip 201) over the first device die, wherein the second device die comprises a power switch (MOSFET 210A), and wherein the power switch comprises: a first source/drain region (right drain region 212) electrically connecting to the through-via in the first device die (see [0033]); and a second source/drain region (source region 211) connecting to the integrated circuit in the first device die (connecting to transistor 260 through contacts and conductive wires in MOL 208 and BEOL 209) (see [0033-0034]).
Dutta fails to disclose the method comprising bonding the first device die over a package substrate and the substrate being semiconductor.
DeLaCruz discloses a method comprising bonding a first device die (IC 212-A) to a package substrate (package substrate 232) (see Fig. 2A and [0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the package substrate of DeLaCruz into the method of Dutta for bonding the first device die of first package (chip 251) to the package substrate because the modified structure would reduce footprint, increase bandwidth and performance with shorter interconnects and improve thermal management.
The combination of Dutta and DeLaCruz fails to disclose the substrate being semiconductor.
Kabe discloses a method comprising a substrate (substrate 121) being semiconductor (silicon) (see Fig. 1 and [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate semiconductor material of substrate of Kabe into the method of Dutta for making the substrate of Dutta because silicon is well known and low-cost material for making substrate with high performance.
Regarding claim 30, the combination of Dutta, DeLaCruz discloses the method of claim 29, wherein the power switch is configured to cut off or provide power to the integrated circuit in response to different control signals that control operations of the power switch (MOSFET 210A would stop sending power from source region 211 to transistor 260 when a voltage of 0V applied to the gate of MOSFET 210A and sending power to transistor 260 when a voltage of 5V applied to the gate of MOSFET 210A) (see Dutta and Fig. 2A).
Allowable Subject Matter
Claims 3, 6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having: wherein the through-via is formed before the first device die is bonded with the second device die as recited in claim 3.
Wherein the first device die is bonded to the package component through a power bump that receives an ungated voltage from the package component, and is connected to the first integrated circuit through an electrical path, and wherein the electrical path comprises: a first part from the power bump to the power switch, and a second part from the power switch to the first integrated circuit as recite in claim 6.
Wherein the first device die further comprises a second integrated circuit, wherein the second integrated circuit is configured to receive power when the first integrated circuit is cut from power by the power switch as recited in claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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